JPH07105444B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular, allows the logic circuits of a plurality of logic levels to be mixed on the same semiconductor substrate, and enables the optimum design of the system on-chip. The present invention relates to a semiconductor integrated circuit device.

[Conventional technology]

Conventionally, regarding a semiconductor integrated circuit device in which a bipolar transistor and a MOS transistor are mixed on the same semiconductor substrate, see Proceedings of 1984, IEE, ICD, pp.428-433.
Page, October, 1984 (Proceedings of 1984 IEEE ICCD, PP.4
28-433, Oct. 1984). A bipolar transistor and a CMOS (Complementary MOS) transistor are formed on the same single semiconductor substrate plate, and these 2
By combining two transistors in the basic circuit, it is possible to realize a high-performance semiconductor integrated circuit device that has both high-speed performance of bipolar and low power consumption of CMOS. In this semiconductor integrated circuit device, the internal circuit is bipolar
It is composed of a CMOS composite logic circuit or a CMOS logic circuit. By selecting these two logic circuits appropriately,
A higher performance system can be designed. The input / output circuit is CMOS or TTL (transistor-transistor).
logic) compatible, ECL chip, bipolar, CM
It is also possible to interface with OS chips. An example in which a system, which is a chip of a plurality of logic level circuits, is constructed around this chip is shown in FIG. 201 to 204 are 1
Two semiconductor integrated circuit devices, 201 is bipolar CMO
S composite logic circuit, 202 is CMOS logic circuit, 203 is ECL circuit, 20
Reference numeral 4 is a chip composed of TTL circuits.
The system can be optimally designed by taking advantage of the features of each logic circuit. For example, a logic operation unit requiring high speed is composed of 203 ECL chips, a memory unit requiring high integration is composed of 202 CMOS chips, and logic requiring both high speed and high integration is required. It is conceivable that the part is composed of 205 bipolar CMOS chips, and the other part is composed of 204 TTL chips. At this time, the interface section 205 of the 201 bipolar CMOS chip and the ECL chip of 203 performs at the ECL logic level, and the interface with the TTL chip of 204 is TT.
201 bipolar / CM as usual when done at L logic level
The OS chip can access signals according to the logic level of the chip of the other party to interface. As shown in this example, by constructing the entire system by utilizing the features of each logic circuit, a high-performance system as a whole can be constructed.

[Problems to be solved by the invention]

There are two problems with the conventional technique, and the following description will be given. First, there is a problem that the delay time required for the interface between chips is long. For example, consider the delay time required for the interface between the bipolar CMOS chip and the ECL chip in FIG. The signal flow from the ECL chip to the bipolar CMOS chip is shown in Fig. 3 (a). The signal of the internal circuit 311 in the ECL chip 302 is output to the outside of the chip via the output buffer 308. Output signal is E
This is a CL level signal. On the other hand, bipolar CMOS chips
301 receives a signal by a receiver 307 inside the chip, level-converts it from an ECL level to a bipolar CMOS level signal by a level conversion circuit A306, and further, through an input buffer 305, an internal circuit of the bipolar CMOS. A signal is transmitted to 310. In this example, the factors that increase the interface delay time are the output buffer 308 in the ECL chip 302 and the level conversion circuit 306 in the bipolar CMOS chip 301. Since the output buffer 308 outputs the output signal to the outside of the chip, it is necessary to drive a large load and the delay time becomes long. Further, the level conversion circuit (A) 306 is provided with an ECL level signal (normally V _OH = −0.9 V, V _OL
= -1.75V) is a bipolar CMOS level signal (usually V _OH
= + 5V, V _OL = 0V). GND (0V) to V _EE (−5.
2V) ECL signal operating from V _CC (+ 5V) to GN
As described above, a large level shift and amplitude amplification are required to convert to a bipolar CMOS level signal operating with a D (0V) power supply, and the time required for level conversion is long. . Due to the delay due to the output buffer 308 and the level conversion circuit 306, the delay time required for the interface between the chips 301 and 302 becomes long.

A second problem is that the degree of freedom in design is limited, which leads to an increase in mounting area. For example, in the system shown in FIG. 2, the logic operation unit required to have high speed is constituted by the ECL chip 203, which cannot be realized by the speed performance of the chips of other logic level circuits. Therefore, the logic operation unit has no choice but to use the ECL chip. Next, this system has a register section and frequently accesses data with the logical operation section. Therefore, we would like to realize this register part with an ECL chip as well, but since ECL consumes a large amount of power and has a low degree of integration, it is not suitable for a register configuration. Therefore, the register section is configured by bipolar CMOS or CMOS with low power consumption and high integration. As seen in this general system configuration example, the logical operation unit and the register unit cannot be realized in one chip due to the performance limit of each logical chip. The arithmetic unit and the register unit are composed of separate chips, and the packages are packaged to connect the chips to each other on the board, resulting in a large mounting area.

As described above, the conventional technique has two problems that the delay time of the inter-chip interface is long and the mounting efficiency is low.

An object of the present invention is to provide a semiconductor integrated circuit device having a short delay time and high mounting efficiency.

[Means for Solving Problems] The above object is achieved by integrating and forming logic blocks including at least logic circuits of different logic levels such as ECL and CMOS in the same chip and operating with power supplies having the same potential. To be done.

[Action]

By integrating logic blocks containing logic circuits of different logic levels formed in the same chip in the same chip, the conventional I / O buffer between the logic blocks becomes unnecessary. Moreover, since the logic blocks are operated by substantially the same power source, the amount of level conversion is reduced,
Delay time is reduced.

〔Example〕

As shown in FIG. 1, in one embodiment of the present invention, a semiconductor substrate
101 has a region 102 which is a logic block composed of an ECL circuit, a region 103 which is a logic block composed of a bipolar CMOS circuit, and a region 104 which is a logic block composed of a CMOS. is doing. On this semiconductor chip, the bipolar transistor and the MO
It is possible to form an S-transistor. A bipolar transistor is formed in the ECL region 102, and no MOS transistor is formed. On the contrary, in the CMOS area 104, M
The OS transistor is formed, and the bipolar transistor is not formed. Both bipolar transistors and MOS transistors are formed in the bipolar CMOS region 103. In each area, ECL circuit, CMOS circuit, bipolar
A CMOS circuit is configured, and these circuits are operated by power supplies having the same potential level.

In the above description, only the bipolar transistor was formed in the ECL region, and only the MOS transistor was formed in the CMOS region.However, a bipolar transistor and a MOS transistor are formed in a certain proportion in the entire chip, and in any region of the chip, the bipolar transistor is formed. Both Logic and CMOS Logic can be configurable. In addition to the above ECL, CMOS, and bipolar / CMOS circuits, I ² L (Integrated Injection Lo
It is also possible to form other types of logic circuits such as gic) and NTL (Non Threshold Logic).

It will be described with reference to FIG. 3 that the delay time required for the interface, which is the first problem, can be reduced according to one embodiment of the present invention. According to the prior art of FIG. 3 (a), the output buffer 308, the receiver 307, the level conversion, as shown in FIG. 3 (a), before the ECL internal signal is received by the bipolar CMOS internal circuit. A signal is propagated through the circuit (A) 306 and the buffer 305. As described above, the output buffer 308 and the level conversion circuit (A) 306 are the major causes of the delay.

On the other hand, consider a signal propagation path according to an embodiment of the present invention with reference to FIG. In one embodiment of the present invention, the ECL internal circuit and the bipolar CMOS circuit are on the same semiconductor substrate. In the figure, the ECL circuit part is the ECL block 304, and the bipolar CMOS circuit part is the bipolar CMOS block 30.
Write 3. When transmitting a signal from the ECL block to the bipolar CMOS block, the input / output buffer is not necessary because it is on the same chip. Therefore, the output buffer 308 and the input buffer 305 of FIG. 3 (a) are unnecessary, and the signal can be transmitted only by the receiver 307 and the level conversion circuit (B) in FIG. 3 (b). it can. Therefore, in comparison with the prior art, in the embodiment of the present invention, the delay of the output buffer and the input buffer can be eliminated.

Further, comparing the level conversion circuit (A) of the prior art with the level conversion circuit (B) used in the embodiment of the present invention, the level conversion circuit (B) is the level conversion circuit (A).
The delay time becomes smaller. This will be described below. When converting the level of the ECL signal into a bipolar CMOS signal, it is necessary to perform two conversion operations of level shifting and amplification of the signal. In the case of the conventional technology, FIG.
The ECL signal which is the output signal of V _OH1 = _-0.9 V, V _OL1 = -1.
The signal has a logic level of 75 V, and V _th1 = −1.325 V when the intermediate potential of the signal is V _th . Also, FIG. 3 (a) 310
The internal signal of the bipolar CMOS signal is V _OH2 = + 5
This is a signal having a logic level of V, V _OL2 = 0 V, and V _th2 = + 2.5 V when the intermediate potential of the signal is V _th . Therefore, the level conversion circuit (A) 306 performs the level shift of ΔV _th = V _th2 −V _th1 = 3.825 V, Signal amplification must be performed. On the other hand, in the level conversion circuit (B) 309 of FIG. 3B according to the present invention, the bipolar CMOS circuit operates at the same potential level as the ECL circuit. Therefore, bipolar CMOS signals are
V _OH2 ′ = 0 V, V _OL2 ′ = −5.2 V, V _th2 ′ = −2.6 V, and the level conversion circuit (B) eventually has a level shift of ΔV _th ′ = V _th2 ′ −V _th1 = 1.275 V, It is only necessary to amplify the signal of. Compared with the conventional technology,
The absolute amount of signal amplification is almost the same, but the level cyst amount may be about 1/3 of the conventional technique. As a result, the delay of the level conversion circuit (B) is about the same as that of the level conversion circuit (A).
It becomes 1/5. As described above, the removal of the input / output buffer intervening in the signal propagation and the speedup of the level conversion circuit are made possible by the embodiment of the present invention, and the interface which is the first problem of the prior art is concerned. It is possible to reduce the day time.

Next, although it is obvious that the present invention solves the second problem of the conventional technique, that is, the problem of mounting efficiency, a brief description will be given below. In the prior art, as described above, when it is necessary to use a plurality of types of logic circuits due to system optimization, these different types of logic circuits are separate semiconductor substrates, as shown in FIG. These separate chips are each packaged and connected to each other on the board. On the other hand, in the embodiment of the present invention, different kinds of logic circuits are integrated and realized on a single semiconductor substrate as shown in FIG. 1, so that different logic circuits can be interconnected on-chip. . Therefore, the implementation efficiency is dramatically improved.

Specific embodiments of the present invention will be described below with reference to FIGS. 4, 5, and 6.

In FIG. 4, reference numerals 401, 402, and 403 denote logic circuit blocks inside the semiconductor substrate, which are composed of a plurality of types of logic circuits each having a different logic level. As an example, 401 is a logic circuit block configured by an ECL circuit, 402 is a logic circuit block configured by a bipolar CMOS circuit, and 403 is a logic circuit block configured by a CMOS circuit. . Of course, the types of logic circuits and the number of logic blocks are not limited to those in the above example, and various logic circuits and the number of logic circuit blocks can be taken. In the above example, 404 is an interface circuit between blocks. These circuits are different depending on the interface circuit between the logic circuit blocks 401 and 402, the interface circuit between the logic circuit blocks 402 and 403, and the direction of the interface. An input / output circuit 405 interfaces the inside and the outside of the chip. Although four circuits 405 are shown in the figure, these four circuits have different configurations and their input / output signal levels. 40
Reference numeral 6 is a first power supply line having a first power supply potential, and in this example, V _CC = + 5V. Reference numeral 407 is a third power supply line having a third power supply potential, and GND = 0V. 408 is a second power supply line of the second power supply potential, and V _EE = −5.2V. Reference numeral 409 indicates the inside of the semiconductor substrate (chip), and the above logic circuit block and various interface circuits are all on the same chip.
It's in 409. Further, all the internal circuits in the logic circuit blocks 401, 402, 403 are connected to the power source line 407 of the third potential and the power source line 408 of the second potential, that is, GND (= 0V) and V
It operates between _EE (= -5.2V). The interface circuit 404 between the blocks is also connected to the power supply lines 407 and 40 like the internal circuit.
Connected to 8 and. On the other hand, the circuit 405 for interfacing the inside and the outside of the chip uses the ECL signal (V _OH = −0.9V, V _OL =
Circuit to input and output -1.75 V) is connected to the power supply line 407 and 408, TTL signal _{(V OH = + 3V, V} OL = 0V) and a CMOS signal (V _OH =
A circuit for inputting / outputting + 5V, V _OL = 0V) is connected to power supply lines 406 and 407. In this embodiment, logic block circuit 40
Although 1,402 and 403 are respectively configured by ECL, bipolar CMOS, and a logic circuit of a different type from CMOS,
It operates with power supplies of the same potential. Therefore, the point of accelerating the interface between blocks is as described above.

According to this embodiment, different types of logic circuits can be interfaced at high speed, and different types of logic circuits can be mounted at high density. Further, in the case of this embodiment, the internal logic circuit is operated by the negative power supply. Therefore, when considering the interface with the outside of the chip, it can be said that the power supply configuration can speed up the interface of the ECL signal.

Next, the embodiment shown in FIG. 5 is a case where the internal logic circuit is operated by a positive power supply. Internal circuit in logic circuit block 401, 402, 403 and interface circuit between each logic block
All of 404 are connected to a power supply line 406 having a first potential and a power supply line 407 having a third potential. In the interface circuit 405 with the outside of the chip, circuits for inputting / outputting TTL and CMOS signals are connected to power supply lines 406 and 407, and circuits for inputting / outputting ECL signals are connected to power supply lines 407 and 408. In this embodiment, the effect of speeding up the interface between different logic circuits and improving the mounting efficiency is the same as in the case of the example of the negative power supply operation described above. It is characterized in that it operates on a power supply. In this example, TTL
It is a power supply configuration that can speed up the interface of CMOS signals.

Another embodiment is shown in FIG.

In the present embodiment, the first and the first used in the above two embodiments are used.
Power supply lines of fourth and fifth potentials different from the second and third potentials are provided. The fourth potential is, for example, V _CC ′ = + 3V, and the fifth potential is V _EE ′ = −2V. In this embodiment, the internal circuits in the logic circuit blocks 401, 402, 403 and the interface circuit 404 between the blocks and the interface circuit 405 with the outside of the chip are all connected to the power supply lines 601 and 602. This embodiment differs from the above two embodiments in that the TTL
It is characterized in that the internal circuit operates at an intermediate potential level where CMOS and ECL signals are mixed. In addition to the effects common to the above-described two embodiments, the effects of the present embodiment enable high-speed interface with any level of TTL, CMOS, and ECL signals in the interface with the outside of the chip. The reason is that the internal circuit operates at the intermediate potential level, so the potential level difference between the external input / output signal and the internal circuit signal is small, and the level shift amount of the signal at the interface between the outside of the chip and the inside of the chip is small. It is in.

Next, taking a negative power source operation example shown in FIG. 4 as an example, FIG. 9 shows a concrete example of an internal circuit used for the blocks 1 ... 401, blocks 2 ... 402, and blocks 3 ... 403. FIG. 10 shows a specific embodiment of the inter-block interface circuit 404 shown in FIG. As shown in FIG. 9, one embodiment of the blocks 401 to 403 is an ECL logic circuit,
It is a bipolar CMOS logic circuit or CMOS logic circuit, and the circuit configuration is as shown in the figure. At least one of these logic circuits is used to perform a desired logic operation in each block. The blocks are connected by an inter-block interface 404. The internal circuit in each block operates by a power supply line 407 having a common potential and a power supply line 408 having a common potential different from 407.

FIG. 10 shows blocks 401 and 4 in the embodiment.
An example of the interface circuit connecting 02 is shown. The interface circuit 111 converts the ECL signal into a bipolar CMOS signal, and the interface circuit 112 converts the bipolar CMOS signal into an ECL signal. The circuit of this embodiment enables a high-speed interface between the blocks 401 and 402.

Of course, the internal circuit and the interface circuit described above are examples of specific embodiments, and the internal circuit and the interface circuit can be realized by a circuit configuration different from that of the circuit of this embodiment. Further, a power supply configuration system in which the negative power supply operation example shown in FIG. 4 and the positive power supply operation example shown in FIG. That is, a certain area inside the chip uses a power supply system operating with a negative power supply, and another area uses a power supply system operating with a positive power supply. The effect of this embodiment is that the speed of the interface with the outside of the chip can be maximized. That is, the TTL and CMOS level external signals are processed in the positive power supply operating region and output again as TTL and CMOS signals to the outside of the chip. The ECL level external signal is processed in the negative power supply operating region and is output again as an ECL signal to the outside of the chip. By doing so, high-speed interface is possible for any signal level of TTL, CMOS, and ECL.

According to the embodiments of the present invention, it is possible to realize all kinds of logic circuits on one chip.

Therefore, as shown in FIG. 7, at least one macro cell including various logic blocks optimally designed for each logic circuit is registered and stored as a macro cell library, and necessary macro cells are selected from the macro cell library. You can choose freely. With conventional technology,
For example, in the case of a CMOS chip, cells are selected only from the CMOS macrocell library, so the degree of freedom in selection is small. However, according to the embodiment of the present invention, the macro cell can be selected from all logic circuits, so that the degree of freedom of selection is increased. The horizontal axis of the graph in FIG. 8 shows the number of gates, and the vertical axis shows the delay time, showing the performance region of CMOS, bipolar CMOS, and ECL as an example. The CMOS macro cell covers the low speed / high integration area indicated by 801 and the ECL macro cell covers the high speed / low integration area indicated by 803.
Bipolar CMOS macrocells cover the performance range between COS and ECL. In the conventional technology, for example, in the case of a CMOS chip, a macro cell is selected only from the performance area of 801. Therefore, the resulting chips are also limited to this performance area. On the other hand, in the present invention, 801, 802, 80
Macro cells can be selected from any of the three performance areas. That is, the macro cell can be freely selected from the wide performance area 804 indicated by the broken line. Therefore, it is possible to realize a chip that covers the high-performance area corresponding to the 804.

〔The invention's effect〕

According to the present invention, a semiconductor integrated circuit device having a short delay time and high mounting efficiency can be obtained.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a chip of an embodiment of the present invention, FIG. 2 is a conceptual diagram of a conventional example, and FIG. 3 is an explanatory view of the effect of the embodiment of the present invention, FIGS. 4, 5, and 6. FIG. 9, FIG. 9 and FIG. 10 are power supply system configuration diagrams of an embodiment of the present invention, FIG. 7 is an explanatory diagram of a design system of the embodiment of the present invention, and FIG. 8 is an explanatory diagram of effects of the present invention. . 101 ... Chip, 102-104 ... Logical block, 105 ... Block-to-block interface, 201-204 ... Various logical chips, 205 ... Chip-to-chip interface, 301,302 ... Chip, 303,304 ... Logic block, 305 ~ 309 ... interface circuit, 310, 311 ... internal circuit, 401 to 403 ... logic block, 404, 405 ... interface circuit, 406 to 408
...... Power supply line, 409 …… Inside the chip, 601,602 …… Power supply line,
701 ... Macrocell Library, 702 ... Chip, 703
…… Logic block, 801-803 …… Each logic macrocell performance area.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/06 321 J

Claims (5)

[Claims] 1. An input circuit block for inputting a signal from the outside, an output circuit block for outputting a signal to the outside, a first circuit block including a field effect transistor, and a composite circuit of a bipolar transistor and a field effect transistor. A second circuit block and a third circuit block composed of a bipolar transistor are formed on the same semiconductor substrate, and the first circuit block, the second circuit block and the third circuit block are the same. A semiconductor integrated circuit which supplies operating power and has a unidirectional signal level conversion unit between the first circuit block, the second circuit block and the third circuit block. apparatus. 2. The semiconductor integrated circuit device according to claim 1, wherein the operating power supply is supplied by three different power supply potential lines. 3. The power supply potential line according to claim 2, wherein the three different power supply potential lines are a first potential line having a high potential, a second potential line having a low potential, and the first potential line. A semiconductor integrated circuit device comprising: a third potential line which is a potential between the second potential line and the second potential line. 4. The input circuit and the output circuit according to claim 3, wherein power is supplied by the first potential line and the third potential line, and the internal circuit is the first potential line. A semiconductor integrated circuit device characterized in that power is supplied by a line and a second potential line. 5. The input circuit, the output circuit, and the internal circuit according to claim 3, wherein the first circuit is the first circuit.
A semiconductor integrated circuit device characterized in that power is supplied by the second potential line and the second potential line.