JPH07104950B2 - Image processing circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing circuit, and in particular, to a digital image stored in an image memory, in real time, the average gray value in the horizontal and vertical directions of the image is obtained. The present invention relates to a desired image processing circuit.

[Conventional technology]

A conventional image processing circuit will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an example of a conventional image processing circuit.

The image processing circuit shown in FIG. 2 includes (A) an image memory circuit 1 storing a digital image, (B) a horizontal serial read circuit 102 for reading the image data in the horizontal direction, and (C) data read in the horizontal direction. (D) A horizontal image accumulation memory 5 for finally storing the addition data, and (E) Vertical reading of image data in the image memory circuit 1 in the vertical direction. A serial read circuit 105, (F) a cumulative adder 106 that sequentially accumulates the data read in the vertical direction row by row, and (G) a vertical image cumulative memory 10 that finally stores the added data. It is configured to include.

The grayscale value of each pixel is read out in the horizontal direction from the image memory circuit 1 by the horizontal serial read circuit 102.

In this case, the read position changes for each raster scan.

The pixel data signal p is the horizontal data p and the cumulative adder 10
3 is entered and stored in the horizontal image accumulation memory 5 for each horizontal line.

The same process is repeated for all lines, and finally the average gray value of each horizontal line is obtained.

Next, the pixel data signal s is transferred to the vertical serial read circuit 105.
Then, the data is read in the vertical direction, and the vertical adder 106 cumulatively adds one line in the vertical direction as vertical data t.

The accumulated data is stored as the vertical addition value u in the vertical image accumulation memory 10 for each vertical line.

The same process is repeated for all lines, and finally the average gray value of each vertical line is obtained.

[Problems to be Solved by the Invention]

The above-described conventional image processing circuit first reads the image data in the horizontal direction, obtains the cumulative image gray value of each column in the horizontal direction, then reads it in the vertical direction, and obtains the cumulative image gray value of each column in the vertical direction. Therefore, it is necessary to read the grayscale data of each pixel twice, which is disadvantageous in that the processing takes time.

[Means for Solving the Problems]

The image processing circuit of the present invention comprises: (A) a read signal synchronizing circuit which generates a synchronizing signal and a first address signal which is incremented each time data is read from the image memory and corresponds to a column of each vertical line; B) A second address signal corresponding to the line number is obtained by finding the number of the horizontal line based on the sync signal.
A counter circuit which outputs first and second clear signals; (C) an image memory circuit which stores a digital image to be processed and outputs a pixel data signal; (D) synchronizes the pixel data signal with the synchronization signal A serial read circuit that sequentially reads out in the horizontal direction and outputs a grayscale value signal, (E) A first adder that adds the grayscale value signal and the cumulative value signal, and outputs a first addition value signal, (F) A buffer circuit which is initialized by the first clear signal, temporarily holds the first addition value signal, sends the cumulative value signal toward the first adder, and outputs a cumulative result signal; G) A horizontal image accumulation memory for storing the accumulation result signal at each address designated by the second address signal, (H) The gray value signal and the shift data signal initialized by the second clear signal And a second adder for outputting a second added value signal, (I) delaying the second added value signal by one horizontal line, and transmitting the shift data signal to the second adder. A shift register having the same number of stages as the number of pixels in the horizontal direction of the digital image, which is sent to the (J) vertical image storing the second addition value signal at each address specified by the first address signal It includes a cumulative memory and.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The image processing circuit shown in FIG. 1 includes (A) a read signal that generates a synchronization signal b and a first address signal l that is incremented each time data is read from the image memory and that corresponds to a column of each vertical line. Synchronizing circuit 6, (B) Based on the synchronizing signal b, the second address signal h corresponding to the line number is obtained by finding the number of the horizontal line.
Counter circuit 7 for outputting first and second clear signals f, k, (C) Image memory circuit 1 for storing a digital image to be processed and outputting pixel data signal a, (D) Synchronizing pixel data signal a A serial read circuit 2 that sequentially reads out in the horizontal direction in synchronization with the signal b and outputs a grayscale value signal c. (E) The grayscale value signal c and the cumulative value signal d are added and a first added value signal e is output. First adder 3, which is initialized by (F) clear signal f, and adds value signal e
Buffer circuit 4 for temporarily storing the accumulated value signal d toward the adder 3 and outputting the accumulated result signal g, and (G) storing the accumulated result signal g at each address designated by the address signal h. Horizontal image accumulation memory 5, (H) Initialized by clear signal k, and gray value signal c
And the shift data signal j are added to obtain a second added value signal i
A second adder 8 for outputting (I) The added value signal i is delayed by one horizontal line, and the shift data signal j is sent to the adder 8 which is the same as the number of pixels in the horizontal direction of the digital image. A shift register 9 having a number of stages, and (J) a vertical image accumulation memory 10 for storing an added value signal i at each address designated by an address signal l.

The vertical image cumulative memory 10 stores the cumulative gray value for each horizontal line of the digital image, and the average horizontal gray value is obtained by arbitrarily cutting the lower bit data.

Finally, when all the pixel data signals a have been read, the cumulative gray value for each vertical line is stored at each address in the vertical image cumulative memory 10.

〔The invention's effect〕

In the image processing circuit of the present invention, instead of providing a circuit for reading the gray value of the image in the horizontal and vertical directions, a circuit for sequentially accumulating the data read in the horizontal direction and the gray value read in the horizontal direction. 1 pixel per pixel is added by adding a circuit for inputting to the shift register for the number of pixels in the direction and adding the output of the shift register and the gray value described above.
Since the average gray value for each column in both the horizontal direction and the vertical direction can be obtained by reading the data once, it is possible to perform the processing in real time in synchronization with the image input timing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1 ... Image memory circuit, 2 ... Serial read circuit, 3
...... Adder, 4 ... Buffer circuit, 5 ... Horizontal image accumulation memory, 6 ... Read signal synchronizing circuit, 7 ... Counter circuit, 8 ... Adder, 9 ... Shift register, 10 ... Vertical image Cumulative memory, a ... Pixel data signal, b ... Sync signal, c ... Gray value signal, d ... Cumulative value signal, e ... Addition value signal, f ... Clear signal, g ... Cumulative result signal, h ...
... address signal, i ... added value signal, j ... shift data signal, k ... clear signal, l ... address signal.

Claims (1)

[Claims] 1. A read signal synchronizing circuit for generating a synchronizing signal and a first address signal which is incremented each time data is read from an image memory and which corresponds to a column of each vertical line, (B) A second address signal corresponding to the line number is obtained by finding the number of the horizontal line based on the synchronization signal.
A counter circuit which outputs first and second clear signals; (C) an image memory circuit which stores a digital image to be processed and outputs a pixel data signal; (D) synchronizes the pixel data signal with the synchronization signal A serial read circuit for sequentially reading out in the horizontal direction and outputting a gray value signal, (E) A first adder for adding the gray value signal and the cumulative value signal and outputting a first added value signal, (F) A buffer circuit which is initialized by the first clear signal, temporarily holds the first addition value signal, sends the cumulative value signal toward the first adder, and outputs a cumulative result signal; G) A horizontal image accumulation memory for storing the accumulation result signal at each address designated by the second address signal, (H) The gray value signal and the shift data signal initialized by the second clear signal And a second adder for outputting a second added value signal, (I) delaying the second added value signal by one horizontal line, and transmitting the shift data signal to the second adder. A shift register having the same number of stages as the number of pixels in the horizontal direction of the digital image, which is sent to the (J) vertical image storing the second addition value signal at each address specified by the first address signal An image processing circuit comprising: an accumulating memory;