JPH07104801B2 - Program development equipment - Google Patents

Description

The present invention relates to a program development device.

[Conventional technology]

The configuration and operation of a conventional program development device (hereinafter referred to as ICE) will be described with reference to FIG. An application system 310 using a microcomputer is a socket 311 in which the microcomputer is mounted and an R storing a program.
The ICE300 includes the OM312, the ICE300 performs the same operation as the macro computer (hereinafter referred to as the EVA chip) 301, the EVA chip 301 on the application system 310.
The contents of the ROM 312 are sequentially executed, and the break control circuit 304 for stopping the evaluation chip 301 (hereinafter, referred to as a break) when a predetermined state is set, the condition for breaking the evaluation chip 301, and the display device (hereinafter, CRT) are set. It is composed of a supervisor 302 that controls the break of the 303.

The ICE 300 is connected to the socket 311 in which the microcomputer of the application system 310 is mounted, and the evaluation chip 301 can be controlled in the same manner as when the microcomputer is actually executing the program to develop the program.

Here, the control when the user actually causes the ICE300 to perform a break operation will be described.

The supervisor 302 sets a break condition set by the user of the ICE 300, for example, a condition such as a break when the program 100 is executed, to the break control circuit 304 via the break setting line 306. The break control circuit 304 monitors the evaluation chip status 307 as to whether the evaluation chip 301 executes the instruction at address 100.

When the evaluation chip 301 executes the instruction at address 100 and the break condition is met, the break control circuit 304 outputs the break output 305.
Is output to stop the evaluation chip 301 and notify the supervisor 302.

Here, the supervisor 302 separates the evaluation chip 301 from the application system 310, causes the evaluation chip 301 to output the contents and status of various registers according to a predetermined procedure, and the supervisor 302 displays this on the CRT 303 or the like.

During this period, the evaluation chip 301 is separated from the application system 310 and performs processing for outputting the contents of various registers to the supervisor 302, so that the program on the ROM 312 cannot be executed. This is an application system 310
Is a big problem when the motor control is performed. The application system 310 is connected to the motor, which must be microcomputer controlled,
When a break occurs, the evaluation chip 301 is separated from the application system 310 and the process of outputting the contents of the register to the supervisor 302 is performed. Therefore, the motor is not controlled and the application system 310 may run out of control. is there.

Even if the evaluation chip 301 performs high-speed output processing of register contents and the like and immediately reconnects to the application system 310, it does not mean that the program is executed in real time (hereinafter, referred to as real time), and the microcomputer does not actually execute. The operation timing is different from when the program is executed and the function as ICE cannot be achieved.

[Problems to be Solved by the Invention]

In the above-mentioned conventional ICE, when a break occurs when the application system controls the operating part such as a motor,
Since the evaluation chip in the ICE is separated from the application system, there is a drawback that the motor etc. may become uncontrollable and run out of control.

[Means for Solving the Problems]

The program development apparatus of the present invention executes a program on an application system to which an ICE is connected in parallel and breaks when a predetermined break condition is detected, and a first evaluation chip group that always breaks in real time without breaking. The first evaluation chip is provided with means for sequentially stopping when a corresponding stop condition is detected.

〔Example〕

 The present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The ICE 100 is configured to include an evaluation chip 101 for which break conditions cannot be set, and evaluation chips 102, 103, 104 that break when the break conditions set by the supervisor 108 are satisfied.

Each evaluation chip is connected in parallel to the application system 110, and the output 113 from the ICE 100 to the application system 110 uses the output of the evaluation chip 101 and the output 114 from the application system 110.
Are connected in parallel to each evaluation chip 101, 102, 103, 104.

Break control circuits 105, 106, 107 are evaluation chips 102, 103, 104.
It is set corresponding to each, and supervisor 10
The break conditions set by 8 are compared with the statuses 109, 110, 111 output by the evaluation chip, and if they match, the break outputs 112, 113, 114 are output, the supervisor 108 is notified, and at the same time the corresponding evaluation chip is stopped.

If the break condition set in the break control circuit 105 is satisfied here, the supervisor 108 sets the evaluation chip 1
Disconnect 02 from application system 110, break it,
The status of various registers at that time is retained.

Since the other evaluation chips 101, 103, 104 are not stopped, the supervisor 108 can read out various statuses when the evaluation chip 102 breaks and display them on the CRT 109 or the like in parallel with the real-time execution of the program of the application system 110.

Similarly, even if the evaluation chips 103 and 104 break, the evaluation chip 101 does not break, so that the contents of the ROM 112 on the application system 110 can always be executed in real time, so that the application system 110 does not run out of control and become uncontrollable.

Even after the break, various statuses at each break are held by the corresponding evaluation chip, so that the status can be read and secured later. Further, in this embodiment, the number of break points can be set up to 3, but the number of break points can be freely increased by adding an evaluation chip and a break control circuit.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In the first embodiment, a break cannot be made if the number of break points exceeds 3, but in the present embodiment, even if a break occurs up to three break points, the program is executed in real time and four or more break points are required. In this case, the program cannot be executed in real time, but a break is possible. The difference from the first embodiment is the evaluation chip.
The break control circuit 201 is only added to 101. The operations of the evaluation chips 102, 103, 104 are similar to those of the first embodiment. Even if these evaluation chips break, the application system 110 can execute the program in real time by the evaluation chip 101.

EVA chip when a break of 4 points or more is required
Using 101, the supervisor 108 sets the break condition in the break control circuit 201, and when the break condition is satisfied, the evaluation chip 101 is disconnected from the application system 110 and notifies the supervisor 108 of the internal status and the like. Since the ICE of this embodiment can perform two types of operations for breaks, the breaks during the routine in which the movable part in the application system is operating are the evaluation chips 102, 103, 104.
Is used, and the evaluation chip 101 is used for others, and efficient program development can be performed.

〔The invention's effect〕

The ICE of the present invention has an effect that a program on the application system can be executed in real time without being separated from the application system even while executing output processing of various registers due to the break.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a conventional technique. 110,310 …… Application system, 110,310 …… Socket, 112,
312 …… ROM, 101,102,103,104,301 …… Evaluation chip, 10
5,106,107,201,304 …… Break control circuit, 108,302 ……
Supervisor, 109,303 …… CRT, 100,300 …… ICE.

Claims (1)

[Claims] 1. A program development apparatus for a microcomputer that stops when a preset stop condition is detected and can monitor the state at the time of stop. A first evaluation microcomputer group that stops when the stop condition is detected. And a second evaluation microcomputer that always operates in real time without stopping, and the first and second evaluation microcomputers execute programs in an application system to which a program development device is connected in parallel. The first evaluation microcomputer is provided with means for sequentially stopping when the corresponding stop condition is detected, and the various internal states at the time of stop can be monitored in parallel with executing the program in real time. A program development device characterized by.