JPH07101885B2 - Bridge circuit that interconnects networks - Google Patents

Description

The present invention relates to a bridge circuit for interconnecting networks, and more particularly to a processing time for determining whether to transmit a received message to another network. , A bridge circuit capable of shortening the processing time for automatically learning the stations constituting a network.

[Prior Art] FIG. 3 shows a local area network LANa having a plurality of stations 111a, 112a and 113a and a plurality of stations 111b, 112b and 11a.
A conventional example in which a local area network LANb having 3b is interconnected by a bridge circuit 41 is shown. Here, the bridge circuit 41 performs the operation described in JP-A-60-152145.

The details are shown in FIG.

As shown in FIG. 4, the bridge circuit 41 is a communication control IC.
53, 55, microprocessor unit (MPU) 61, memory controller 65, internal buses 67, 69, MPU bus 71, program RAM 77, ROM 73, filtering table RAM 75, signal lines 81, 83, timer 91.

Here, the interconnected networks are ISO8802-4.
Adopts token passing bus and communication control IC
Reference numeral 53 corresponds to the lance described in the above publication, and a token bus controller (TBC) is used. The filtering table RAM 75 corresponds to the lookup control unit, lookup RAM, and new source RAM described in the above publication. RAM7 for this filtering table
5 is a memory for storing the station address, and of the station addresses stored in the memory, the station address to be compared is stored, or the address of the memory to be stored is determined from the station address by the hash circuit. It is composed of a circuit.

In the figure, 51a and 51b are transmission lines of LANa and LANb, respectively.

Hereinafter, automatic learning and relay determination by software using the MPU 61 will be described with reference to FIGS. 4 to 6.

Automatic Learning of Source Stations Constituting Network As described in the above publication, the bridge circuit 41 is
The source address of the received message and the network to which the source station belongs are stored in the filtering table RAM 75 of the bridge circuit 41 by automatically learning.

For example, now the message from the station 111a is sent to the bridge circuit 41
Is received.

The communication control IC 53, after checking the error of the message, transmits the message to the memory controller 65 via the internal bus 67 and instructs the memory controller 65 to store the received message in the buffer memory 63. And signal line 81
Issue an interrupt signal to the MPU 61 via.

The MPU 61 searches whether or not the station address of the station 111a and the information that the station 111a belongs to the network "a" are stored in the filtering table RAM 75, and if not stored, that is, learning (Steps 501 and 502 in FIG. 5).

FIG. 6A shows the learning result of the above example in which the station 111a belonging to the network LANa is the transmission source. It should be noted that FIG. 6B shows the learning result when the station 112b belonging to the network LANb instead of the station 111a becomes the transmission source after the above example.

In this way, the learning results of the networks LANa and LANb are commonly stored in the filtering table RAM 75.
Therefore, in the above example, in the search from this table, the addresses of all the stations stored in the filtering table RAM 75 are compared with the station addresses of the transmission source station 111a one by one until they match.

Relay determination of whether to send a received message As described in the above publication, the bridge circuit 41,
In order to check which network the station having the destination address of the received message belongs to, the source station address stored in the filtering table RAM 75 by automatic learning and the network to which the source station belongs To retrieve information (Steps 503 and 50 in Fig. 5)
Four).

Even in this search, since the table is common to the networks LANa and LANb, the addresses of all the stations stored in the filtering table RAM 75 are compared with the address of the receiving destination or the address of the transmitting station point by point. .

(1) In the case where the address of the receiving station and the information indicating which network the receiving station belongs to are stored in the filtering table RAM 75 (5th
(YES in step 503 in the figure), if the receiving station and the transmitting station do not belong to the same network, the message is transmitted to the network to which the receiving station belongs (steps 504 and 505 in FIG. 5).

If they belong to the same network, nothing is done (steps 504 and 506 in FIG. 5).

(2) If the address of the receiving station and the information indicating which network the receiving station belongs to are not stored in the RAM 75 for the filtering table, the data is sent to all networks (step in FIG. 5). 503, 507).

Specific Description of Relay Determination (I) Consider, for example, communication between stations 111a and 112b (different network communication).

The bridge circuit 41 receives the message from the station 111a, and checks the network to which the station 112b, which is the receiving station, belongs, in the filtering table RAM 75.
Instruct to search whether the address of 12b is stored.

(1) When the address of the station 112b and the information that the station 112b belongs to the network "b" are stored in the filtering table RAM 75, the bridge circuit 41 fetches the message from the buffer memory 63 and outputs the message. Instruct the communication control IC 55 to transmit to "b" (5th
(Fig. Steps 503, 504, 505).

(2) If it is not stored, it is unknown which network the station 112b is connected to, so an instruction is sent to the communication control IC 55 to similarly transmit the message (steps 503 and 507 in FIG. 5).

(II) Consider communication between the station 111a and the station 113a (same net communication).

The bridge circuit 41 receives the message from the station 111a, and in order to check which network the station 113a, which is the receiving station, belongs to, the station 1 is stored in the filtering table RAM 75.
Instruct to search whether the address of 13a is stored.

(1) If the address of the station 113a and the information that the station 113a belongs to the network "a" are stored in the filtering table RAM 75, the message is not transmitted to the network "b" (step in FIG. 5). 503,504,50
6).

(2) If it is not stored, it is transmitted (steps 503 and 507 in FIG. 5) as in the case of communication between the stations 111a and 112b ((I) and (2)).

[Problems to be Solved by the Invention] However, in the above-mentioned conventional technique, a filtering table is used in the case of determining whether to transmit the received message to the other network and in the case of automatically learning the stations on the network. Since the RAM for common use is commonly used by multiple networks, it is necessary to compare the addresses of all the stations stored in the RAM for the filtering table with the addresses of the receiver or the source station one by one by software. . Therefore, if the number of stations stored in the filtering table RAM increases, the time for comparison increases and the processing time of the bridge circuit increases.

In addition, when the transmission speed of the network is high and many messages flow on the network, the bridge circuit may be in a congested state and a frame that cannot be relayed may occur.

An object of the present invention is to harden the source address and the destination address of the received data before storing the data received from the network in the memory (filtering table RAM) and before processing by the communication control IC and the like. By detecting with ware, the drawbacks of the above-mentioned conventional technology are resolved,
It is an object of the present invention to provide a bridge circuit that interconnects networks, which can reduce the processing time for determining whether to relay a received message and the processing time for automatically learning the stations that form the network.

[Means for Solving the Problems] A bridge circuit for interconnecting networks of the present invention is
A bridge circuit for interconnecting at least two networks having a plurality of stations, each station configured to send and receive a message including at least a destination station address and a source station address, the bridge circuit comprising: The circuit comprises a filtering table RAM, a decision circuit, a communication control logic circuit means for controlling the operation to the network, a message storage means for storing the message, and an MPU for controlling the entire bridge circuit. The above-mentioned message is temporarily stored in the message storage means, and then the message is relayed to another network as necessary. At least a part of the station addresses of a plurality of stations included in each network is stored in the network. Filtering table RAM for storing each The first logic that detects the address of the receiving station from the message, determines the match / mismatch between the detected address of the receiving station and the storage address stored in the filtering table RAM, and determines the relay / discard of the message. A circuit and a second logic circuit that detects a source station address from the message and stores the source station address regardless of whether the memory of the filtering table RAM stores the source station address. The determination circuit provided as the following hardware is arranged in the preceding stage of the message storage means and the communication control logic circuit means.

Here, the reason why the address of at least a part of the station address is used is that the entire station address may not be required to identify the station, and this case is also included.

[Operation] When a plurality of stations included in each network become a transmission source station and a common memory is provided to store the station information in common in each network in order to learn the station, It is necessary to store the station address and information on which network the station belongs to as the station information in the common memory. This is because station addresses belonging to other networks are also stored in a mixed manner, so that it is necessary to distinguish them. As a result, in order to obtain specific station information, the contents of the memory means must be compared one by one. This comparison is software intensive and time consuming.

However, for multiple stations in each network,
When the memory means for storing the station address for each network is individually provided, as long as the station address stored in the memory means corresponding to the network to which the source station of the message belongs is retrieved from the message, The station address stored in the memory means is always limited to the network to which the transmission source station belongs, and the station address of another network is not stored. That is,
The memory means for identifying the network need only store the station address of its own network as the transmission source. As a result, high-speed search by hardware becomes possible.

The present invention was created from such a viewpoint.

Before storing the message received from the network in the message storing means and before processing it by the communication control logic circuit means, the source station address and the destination station address of the received message are detected.

Then, based on the detected destination station address and the address data of the memory means stored at the address corresponding to this address, whether or not to relay the message to another network is determined. The comparison time with the station address stored in the means is reduced.

Further, the detected source address is stored in the memory means in order to automatically learn the stations constituting the network. At this time, it is determined whether or not the address of the source station is stored in the memory means. If the address of the transmission source station is stored in the memory means without doing so, the learning time is shortened.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows a state in which local networks LANa and LANb are interconnected by a bridge circuit. Here, it is assumed that both LANa and LANb use the ISO8802-4 token passing bus. The subscript a attached to the components of the bridge circuit is the LANa side component, and the subscript b is
Each of the components on the LANb side is shown, and each component is individually provided except for the 2-port memory. It should be noted that the reference numbers with the subscripts omitted are commonly used for both.

11a and 11b are transmission lines of LANa and LANb, and 12a and 12b are modems, which are connected between the transmission lines 11a and 11b and the bridge circuit, and perform modulation / demodulation of signals transmitted from each network and the bridge circuit. 13a and 13b are connected to the modems 12a and 12b, respectively, and a decision circuit forming a main part of the present invention, and 14a and 14b are for communication control for receiving respective outputs from the decision circuits 13a and 13b and performing protocol control of the token passing bus. It is an IC (Token Bus Controller). 15a and 15b are the decision circuits 13a and 13b
RAM for filtering table that is connected to MPU 16a, 16b and stores a filtering table used for automatic learning and frame relay judgment, and 16a, 16b are microprocessor units (MP that control the entire bridge circuit.
U), 17a, 17b are communication control ICs 14a, 14b, 2-port memory 18
A bus of the MPUs 16a and 16b connected to, and a two-port memory 18 connected between the buses 17a and 17b for storing received data to be relayed.

Here, the point to be noted is that the determination circuits 13a and 13b that perform determination of storage and relay of address information are provided as hardware separately from the MPUs 16a and 16b operated by software,
In addition, it is provided before the communication control ICs 14a, 14b or the filtering table RAMs 15a, 15b. In addition, the filtering table RAMs 15a and 15b are provided on each network side.

Next, details of the determination circuits 13a and 13b (13) are shown in FIG. 20 and 21 are 48-bit shift registers, 20 for a source address and 21 for a destination address. Note that 48 bits is an example. 22 is a comparator that determines whether the received frame is a control frame or a data frame while allowing the received frame to pass through. 23 is a delay circuit that delays the through frame output of the comparator 22 for a predetermined time. 24 is a comparison for determination. A frame passage control circuit for controlling the passage of frames according to the comparison result of the comparator 22 or the comparator 29, and 25 and 26 are 48
Data latch for bits, 25 for source address 48
For the source address that latches the source address stored in the bit shift register, 26 is the 48bit for the destination address
This is for a destination address that latches the destination address stored in the shift register 21. The reference numeral 27 is a control circuit (hereinafter referred to as a hash function) which reads the station address output of the latches 25 and 26 when the output of the judgment comparator 22 is output, and performs the automatic learning and the judgment processing as to whether the received frame is relayed to another network. Circuit control section). 28 is a hash circuit that obtains an address to be referred to in the filtering table RAM 15 from the 48-bit station address input via the hash control circuit 27, and 29 is the station address read from the filtering table RAM 15 and sent from the latch 26. The comparators 30 to 35 for comparing the received address with each other are signal lines connecting these components.

The 48-bit shift register 21 for receiving address, the control / data frame judging comparator 22, the delay circuit 23, the frame passing control circuit 24, the 48-bit data latch for receiving address.
The first logic circuit means of the present invention is constituted by 26, the hash circuit controller 27, the hash circuit 28, and the comparator 29. The 48-bit shift register 20 for the source address, the 48-bit data latch 25 for the source address, the hash circuit controller 27, and the hash circuit 28 constitute the second logic circuit means of the present invention.

Here, the operation of the bridge circuit of FIG. 1 which is an embodiment of the present invention when receiving the token bus frame shown in FIG. 7 from the network LANa will be described with reference to FIG. Although FIG. 8 is written so as to be processed by software for convenience, it is actually processed by hardware.

The received frame is first signal-demodulated by the modem 12a and input to the determination circuit 13a shown in FIG. In the determination circuit 13a, as shown in FIG. 2, the frame passes through the shift registers 20, 21, the comparator 22, the delay circuit 23, and the frame passage control circuit 24 in this order.

A field indicating whether the input frame contains user data or network control, that is, when the FC field of the ISO8802-4 token bus frame reaches the comparator 22, the comparator
22 checks the FC field and determines whether or not the frame is a control frame (step 801 in FIG. 8).

If the frame is a control frame, the frame passing control circuit 24 is requested to operate so as to pass the frame through the signal line 30 (step 802).

If the frame contains user data, a latch signal is sent to the latches 25 and 26 via the signal line 31.

Here, like the ISO8802-4 token passing bus, control frames other than user data frames, such as token frames containing the address of the destination station,
Even for frames that can be used for automatic learning, the signal line
A latch signal may be similarly sent via 31.

The latch 25 latches the source station address field SA (see FIG. 7) passing through the shift register 20, and the latch 26 latches the destination station address field DA passing through the shift register 21 (step 803).

The hash circuit control unit 27 starts its operation by the signal from the comparator 22 sent from the signal line 31. The hash circuit control unit 27 first receives the destination station address latched by the latch 26 via the signal line 33, and then receives the hash circuit 28.
(Step 804).

The hash circuit 28 uses the hash function to filter the received 48-bit destination station address for the filtering table.
It is converted into the address of RAM15, the 48-bit station address stored at that address is taken out from RAM15a, and sent to the comparator 29 via the signal line 34 (step 805).

The comparator 29 compares the address of the receiving station of the frame received from the signal line 33 with the station address read from the filtering table RAM 15. That is, it is checked whether or not the receiving station is on the network that received the frame (step 806).

This inspection is a relay judgment.

If they are different as a result of the comparison, that is, if the destination station of the frame is not in the network that received the frame, the comparator 29 instructs the frame passage control circuit 24 to pass the frame through the signal line 35. Send (step 807).

The received frame receives a delay circuit during these series of processing.
The time is adjusted within 23, and when the frame passing control circuit 24 controls to pass the frame, it is configured to pass the delay circuit 23 exactly.

Then, as shown in FIG. 1, the communication control IC 4a and the MPU 16a perform reception processing and store the data in the 2-port memory 18 (steps 808 and 809).

MPU16a to MPU16b connected to the network on the other side,
Request to send a frame, communication control IC 14b,
The frame is relayed to LANb via the modem 12b (step 810).

On the other hand, when the two are the same, that is, when the destination station of the frame is on the network that received the frame,
Through the signal line 35, the comparator 29 sends an instruction to the frame passing control circuit 24 to discard the frame (step 81).
1).

While these processes are being performed, the hash circuit control unit 27
Shows the source station address latched by the latch 25 on the signal line 32.
And sends it to the hash circuit 28 (step 81).
2).

Hash circuit 28 uses the hash function to filter the received 48-bit source station address for the filtering table.
The address is converted into the address of the RAM 15a, and the source address of 48 bits transmitted via the signal line 32 is stored in the address (step 813).

This storage is the automatic learning of addresses of stations connected to LANa.

At this time, each entry of the filtering table RAM 15 is provided with the age field described in the above publication, and the filtering table RAM 15a generated by the hash circuit 28 is provided.
It is also possible to read the stored data from this address and update the age field when trying to store the same station address.

Further, when storing the station address in the address of the filtering table RAM 15a generated by the hash circuit 28, if the area has already been used by information of a different station address, a means for storing the most efficiently may be further provided. It is possible.

Next, the learning result of the above embodiment will be described with reference to FIGS. 3 and 9.

Now, it is assumed that the bridge circuit 41 receives a message from the station 111a belonging to the network LANa. Judgment circuit 13a
Searches whether the station address of the station 111a is stored in the filtering table RAM 15a on the LANa side. Where the station
The reason why the information that 111a belongs to the network "a" is not dared to search is because that is included in searching the filtering table RAM 15a on the LANa side. As a result of the search, if not stored, it is stored in the RAM 15a for the filtering table on the address LANa side of this station 111a (Fig. 9 (1)).
(A)). Next time, similarly, the bridge circuit 41 receives the message from the station 112a, and if the result of the search is that it is not stored, the address of this station 112a is stored (9th).
Figure (1) (b)).

Next, it is assumed that the bridge circuit 41 next receives a message from the station 112b belonging to the network LANb. Judgment circuit
13b searches whether the station address of the station 112b is stored in the filtering table RAM 15b on the LANb side. If not stored, enter this station address 112b to LANb
It is stored in the RAM 15b for the side filtering table (9th
Figure (2) (a)). Next time, similarly, the bridge circuit 41 receives the message from the station 113b, and if the result of the search is that it is not stored, the address of this station 113b is stored (Fig. 9 (2) (b)).

In FIG. 9, addresses ... ADi, ADi + 1 ..., ADj, AD
j + 1 ... is the table R converted using the hash function
It is the address of AM15a, 15b.

In this way, the learning results of the source station addresses of the networks LANa and LANb are separately stored in the filtering table RAMs 15a and 15b. That is, in the table on the LANa side
Only station addresses of stations belonging to LANa are stored by automatic learning, and only station addresses of stations belonging to LANb are stored in the table on the LANb side.

Therefore, it is necessary to compare the addresses of all the stations stored in the RAM75 for the filtering table with the addresses of the receiving station or the station address of the transmitting station, as in the conventional search, until they match. Instead, it is possible to judge whether or not to relay the data frame by a single hardware comparison between the address of the receiving station and the RAM address where this address should be stored as address data. . As a result, the comparison time can be significantly reduced.

In addition, in step 806 for making the relay determination in FIG.
When the destination station of the frame is not in the network that received the frame, the destination station belongs to the network of the receiving side, but the destination station is not yet learned, There is a case where the destination station does not belong to the receiving side network. In these cases, since the data is transmitted together in the present embodiment, the same result as in the conventional case can be obtained without any problem.

Further, in steps 812 and 813 for performing learning in FIG. 8, since learning is performed without determining whether or not the address of the transmission source station is stored in the RAM, transmission sources already learned The station address will be registered redundantly, but the source station address and RAM address will be 1
Since it corresponds to the one-to-one correspondence, it is overwritten without any problem. The time required for overwriting does not matter because it is not judged by software.

As described above, according to this embodiment, the determination circuit 13 is provided in front of the communication control IC 14 and the filtering table RAM 15, and the relay determination of the message is performed by the hardware before the message is stored in the 2-port memory 13. Since it is done with the above, it is not necessary to compare every address of all stations stored in the filtering table RAM with the address of the receiving destination or the address of the transmitting station by software. Even if the number of stations stored in the RAM increases, the comparison time does not increase and the processing time of the bridge circuit does not increase.

Further, since the processing time is shortened, even if the transmission speed of the network is high and a large number of messages flow on the network, the bridge circuit is not congested and a frame that cannot be relayed does not occur.

[Effect] The present invention has the following effects.

(1) According to the bridge circuit of the present invention, before the received message is stored in the message storing means and the communication control IC
Since all are configured by hardware before passing through, the received message is processed by the communication control logic circuit means and stored in the message storage means as before, and then relay judgment and automatic learning processing are performed. The processing time for determining whether to relay the received message and the processing time for automatically learning the stations that compose the network can be greatly improved as compared with those of the above system.

(2) Further, in the conventional processing method, it is necessary to configure the relay determination and the automatic learning in accordance with the processing specifications of the communication control IC, but according to the present invention, it depends on the processing specifications of the communication control IC. It is possible to provide relay determination and automatic learning processing that does not occur.

(3) According to the bridge circuit learning method of the present invention, the transmission source station address is stored regardless of whether the transmission source station address is stored. Therefore, it is determined whether the transmission source station address is stored. It is possible to perform learning more efficiently than the conventional method in which learning is performed later.

[Brief description of drawings]

FIG. 1 is a block diagram of a bridge circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of the decision circuit of FIG. 1, and FIG. 3 is a network block diagram common to the prior art and the present invention. Fig. 5 is a block diagram of the bridge circuit of the conventional example, and Fig. 5 is a learning circuit of the conventional example.
Judgment processing flowchart, FIG. 6 is a diagram showing the table contents of the common filtering table RAM after learning in the conventional example, FIG. 7 is a block diagram of the token bus frame, and FIG. Judgment process explanatory diagram,
FIG. 9 is a diagram showing the contents of the table on the side of each network after learning in this embodiment. 11a and 11b are transmission lines, 12a and 12b are modems, 13a and 13b are determination circuits as first logic circuit means and second logic circuit means,
14a and 14b are communication control I as communication control logic circuit means.
C, 15a and 15b are filtering table RAMs as memory means, 16a and 16b are MPUs, 17a and 17b are MPU buses, 18 is a 2-port memory as message storing means, 20 is a 48-bit shift register for source address, 21 Is for the recipient address 4
8bit shift register, 22 control / data frame judgment comparator, 23 delay circuit, 24 frame passing control circuit, 25
Is a 48-bit data latch for a source address, 26 is a 48-bit data latch for a destination address, 27 is a hash circuit control unit, 28 is a hash circuit, 29 is a comparator, and 30 to 35 are signal lines.

Claims (1)

[Claims] 1. A bridge circuit for interconnecting at least two networks having a plurality of stations, each station being configured to send and receive messages comprising at least a destination station address and a source station address. The bridge circuit includes a filtering table RAM, a determination circuit, a communication control logic circuit unit for controlling the operation to the network, a message storage unit for storing the message, and an MPU for controlling the entire bridge circuit. The method further comprises the step of temporarily storing the received message in the message storing means, and then relaying the message to another network as necessary, and at least the station addresses of a plurality of stations included in each network. RAM for filtering table to store a part of address for each network, Detecting the address of the receiving station from the message, determining the match / mismatch between the detected address of the receiving station and the storage address stored in the RAM for the filtering table, and determining whether to relay / discard the message. One logic circuit and a second logic circuit that detects a source station address from the message and stores the source station address regardless of whether the memory of the filtering table RAM stores the source station address A bridge circuit for interconnecting networks, characterized in that it is configured by arranging a determination circuit provided as hardware consisting of (1) and (2) before the message storing means and the communication control logic circuit means.