JPH04237232A - Inter-lan connection equipment - Google Patents

Abstract

PURPOSE:To implement abort control of an undesired relay packet independently at a high speed by a microprocessor controlling the entire inter-LAN connection equipment. CONSTITUTION:A FAT memory 33 registering information including an address (filtering address) of a node on a LAN 10 learned by a microprocessor 40. A transmission packet from the LAN 10 is received by a device 30 and its DA is detected by a circuit 31, then the FAT memory address compressing the DA is generated by a circuit 34 and a relevant entry in the memory 33 is accessed. Thus, the filtering address in the information read from the memory 33 is compared with the detected DA by a comparator 36. When the result of comparison indicates coincidence and the said information is effective, a signal 38 is outputted from the circuit 37 thereby allowing a LAN controller 39 to abort the packet received from the LAN 10.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a LAN (Local Area Network) and an inter-LAN connection device that relays between LANs, and in particular learns MAC (Multiple Access Control) addresses, which are addresses on the LAN, and relays packets. The present invention relates to a bridge device.

0002

[Prior Art] Conventionally, a LAN using a MAC address learning method
The connecting device (bridge device) receives all packets from the LAN, and among the received packets, packets destined for a node on the same LAN (relay is not necessary; if relayed, unnecessary packets are It was common practice for a microprocessor to perform the operation of discarding the data without relaying it (because the transmission efficiency of the relay destination LAN would deteriorate) according to a control program. The specific operation of this microprocessor will be explained below.

First, a microprocessor in a LAN connection device instructs a LAN controller to perform all reception operations. Next, the microprocessor learns the destination address and source address of the packet received by the receiving operation of the LAN controller, and does not perform a relay operation if both the destination and source nodes are on the same LAN. Then, the packet is discarded.

0004

[Problems to be Solved by the Invention] As mentioned above, in the conventional LAN connection device, it is difficult to relay/relay packets from the LAN.
All decisions regarding disposal were made through microprocessor program processing. For this reason, when there is a lot of communication within the same LAN, the LAN-to-LAN connection device takes a lot of time to discard packets rather than the original relay operation, and even if a high-speed microprocessor is used, it will not perform well. It was difficult to improve.

The present invention has been made in view of the above circumstances, and its purpose is to provide an inter-LAN connection device that can control the discarding of packets that do not need to be relayed at high speed independently of a microprocessor, thereby improving the performance of the entire device. There is a particular thing.

[0006]

[Means for Solving the Problems] The LAN-to-LAN connection device of the present invention includes a table memory having a plurality of entries for registering filtering address information including filtering addresses, and a table memory that receives transmission packets from a specific LAN and receives transmission packets from a specific LAN. A microprocessor with an address learning function that registers filtering address information including a source address as a filtering address in an entry in a table memory specified by a table memory address generated by compressing the same source address, and transmitting from a specific LAN. A destination address detection circuit that receives a packet and extracts its destination address, and a table that compresses the destination address extracted by this destination address detection circuit using compression data (for example, a generator polynomial) and provides a corresponding (CRC code). A table memory address generation circuit that generates (as) a memory address, and a filtering address and a destination address in the filtering address information read from the table memory in accordance with the specification of the table memory address generated by this table memory address generation circuit. A comparison circuit that compares the destination address extracted by the detection circuit and a packet discard signal generation circuit that instructs discarding the received packet from a specific LAN based on the comparison result of the comparison circuit are provided. This system is characterized in that packets received from a specific LAN are filtered based on a packet discard instruction from a signal generation circuit.

[0007]

[Operation] In the above configuration, the microprocessor:
Address learning is performed in which a transmission packet from a specific LAN is received in a specific mode, and filtering address information including the source address as a filtering address is registered in an entry in the table memory corresponding to the same address. At this time, the registered entry address uses a CRC code generated by compressing the source address based on compression data (for example, a generator polynomial).

After address learning by the microprocessor, the destination address of a received packet from a specific LAN,
A comparison circuit compares the filtering address in the filtering address information registered in the entry in the table memory corresponding to the same address. if,
If a match is detected by this comparison circuit and the filtering address information at that time is valid, the destination of the received packet is a node on the same LAN (specific LAN), so the packet discard signal generation circuit detects a valid filter address. A packet discard signal is generated. This packet discard signal is given to a LAN controller that controls packet input/output to and from a specific LAN, and the LAN controller discards the received packet without relaying it. In this way, the microprocessor is freed from packet discard control.

[0009] The above-mentioned filtering address information includes duplication information indicating that a registration entry of the same information is redundantly assigned to a plurality of nodes (terminals). This duplicate information is detected by a comparison circuit, and
In addition, when the filtering address information including the same duplicate information is valid, the duplicate display state is set. The microprocessor appropriately refers to the table memory in which the filtering address information is stored, and if there is a large proportion of entries in the table memory in which duplicate information is displayed in duplicate, the microprocessor determines whether duplicate information has been duplicately allocated to multiple nodes. If there are many entries, all entries in the table memory are invalidated. Then, the microprocessor rewrites the compression data used for address generation in the table memory address generation circuit so that the optimal filtering operation for the specific LAN can be performed while using a small-capacity table memory.

0010

[Embodiment] FIG. 1 is a block diagram showing the configuration of a connection interface portion on a specific LAN side of a LAN-to-LAN connection device according to an embodiment of the present invention, and FIG. 2 shows a connection between two LANs by the LAN-to-LAN connection device in FIG. FIG. 2 is a block diagram of a LAN system.

In FIG. 2, 10 and 20 are LANs, 30
connects between LAN10 and 20, and this LAN10 and 20
This is an inter-LAN connection device (bridge device) that relays packets between LANs. In this embodiment, the LANs 10 and 20 are bus-type LANs. 11, 12, 13... are nodes (terminals) connected to LAN 10, 21, 22, 23... are LAN
This is a node (terminal) connected to 20.

In the inter-LAN connection device 30 of FIG.
1 is a destination address detection circuit (hereinafter referred to as a DA detection circuit) that detects, for example, a 48-bit destination address (hereinafter referred to as DA) included in a transmission packet from the LAN 10; 32 is a DA of the DA detection circuit 31; This is a timing generation circuit that generates timing signals for controlling each part according to detection timing. Reference numeral 33 denotes a filtering address table memory (hereinafter referred to as FAT memory) having a plurality of entries for registering filtering address information including filtering addresses that are address learning results of the microprocessor 40, which will be described later. The address (entry address) of this FAT memory 33 corresponds to the filtering address (in the filtering address information) registered in the entry, and in this embodiment, it is generated based on the filtering address and a certain generator polynomial. CRC (Cyclic
Redundancy Check) code is used.

FIG. 3 shows the format of the filtering address information. As is clear from the figure, this filtering address information includes a 48-bit address (node address, LAN address, MAC address), and a count value indicating the period during which the same information (of the registered entry in the FAT memory 33) is not accessed. (access count value), a valid/invalid bit (hereinafter referred to as the V bit) indicating whether the same information is valid, and an entry in the FAT memory 33 in which the same information is registered.
It has a duplication presence/absence bit (hereinafter referred to as the O bit) indicating that it is redundantly allocated to multiple nodes on 0.

Referring again to FIG. 1, 34 is the LAN 10
The 48-bit DA (destination address) included in the packet sent from
This is a FAT memory address generation circuit for generating an entry address in the FAT memory 33. In this embodiment, the FAT memory address generation circuit 34 is a CRC circuit, and a generation polynomial (compression data) set by a 48-bit DA and a microprocessor 40, which will be described later.
Based on 48-bit DA, the CRC code corresponding to 48-bit DA is
Generates an 8-bit DA as a compressed FAT memory address.

35 is 48 for serially inputting and holding the DA included in the transmission packet from the LAN 10.
Bit DA holding register (shift register), 36
is a comparator. The comparator 36 is connected to the DA holding register 3
DA held in 5 and FAT memory address generation circuit 3
4 is compared with the 48-bit address (FAT memory data) in the filtering address information read from the FAT memory 33 in accordance with the designation of the FAT memory address generated in step 4. This comparator 36 is used to detect that the DA held in the DA holding register 35 matches the address (filtering address) learned by the microprocessor 40.

37 inputs the comparison result of the comparator 36 and the V bit in the filtering address information from the FAT memory 33, and when a match is detected by the comparator 36 and the V bit is in a valid display state (on state). In some cases, a packet discard signal generation circuit 39 outputs a packet discard signal 38 instructing a LAN controller 39 to discard the packet, which will be described below, to discard the packet. Reference numeral 39 is a LAN controller. The LAN controller 39 controls packet transmission and reception with the LAN 10, and has a serial/parallel conversion function and the like.

Reference numeral 40 denotes a microprocessor that controls the entire LAN connection device 30, and calculates the address (hereinafter referred to as SA) of a node connected to the LAN 10 based on the source address (hereinafter referred to as SA) of the transmission packet from the LAN 10. It has an address learning function that learns filtering addresses). The microprocessor 40 also has an address learning function for learning the addresses of nodes connected to the LAN 20. 41 is an access arbitration circuit for arbitrating FAT memory access requests from the microprocessor 40 and the timing generation circuit 32.

Note that the LAN connection device 30 includes the above-mentioned DA detection circuit 31, timing generation circuit 32, FAT
Memory 33, FAT memory address generation circuit 34, DA
Components similar to the holding register 35, comparator 36, packet discard signal generation circuit 37, LAN controller 39, and access arbitration circuit 41 are also provided on the LAN 20 side, but are omitted in FIG.

Next, the operation of one embodiment of the present invention will be explained. The LAN connection device 30 includes a microprocessor 40
controlled by. At the time of initialization, the microprocessor 40 sets all contents of each entry in the FAT memory 33 to an invalid state. This is FAT memory 33
This is achieved by turning off the V bit of each entry.

Next, the microprocessor 40 sets up the LAN controller 39 in all reception mode and starts operating as a bridge. This allows the LAN
All transmission packets from the LAN controller 10 are initially received by the LAN controller 39. Packets from the LAN 10 received by the LAN controller 39 are temporarily stored in a buffer (not shown), and relayed to the LAN 20 by the LAN controller on the LAN 20 side.

Now, in all reception mode, the microprocessor 40 extracts the SA (source address) in the received packet from the LAN 10 stored in the buffer as a filtering address, and uses the same address (48 bits) as a filtering address.
The filtering address information including the address is written to the entry in the FAT memory 33 corresponding to the same address. At this time, the access count value of the filtering address information is all “0”, and the V bit is on (“1”).
), and the O bit is off (“0”). Note that the address (write address) of the entry in the FAT memory 33 is determined by the microprocessor 40 converting the 48-bit SA (filtering address) in the received packet into certain compression data (a certain generating polynomial for CRC code generation).
This is a CRC code generated by compressing (for example, about 8 to 16 bits) using .

The above is the address learning by the microprocessor 40. After learning this address, LAN1
Among the packets received from FAT memory 33, for those packets having a DA of the same value as the SA registered in the FAT memory 33, a packet discard signal 38 is output from the packet discard signal generation circuit 37 to the LAN controller 39. Therefore, it is no longer received by the LAN controller 39. The details of the operation after address learning will be explained below. Note that address learning by the microprocessor 40 is performed regularly, and SAs not registered in the FAT memory 33
When a packet with SA is received, filtering address information with that SA as the filtering address is registered in the FAT memory 33.

[0023] First, the transmission packet from the LAN 10 is
It is received via a serial interface (not shown) and guided to the DA detection circuit 31, FAT memory address generation circuit 34, DA holding register 35, and LAN controller 39 shown in FIG. The DA detection circuit 31
When a 48-bit DA is detected from a packet received from 0 (received packet) (when DA reception is completed), the timing generation circuit 32 is notified of this fact. The timing generation circuit 32 issues an address generation start instruction to the FAT memory address generation circuit 34, a shift stop instruction to the DA holding register 35, a memory access signal to the FAT memory 33, and a comparison signal according to the timing of DA detection by the DA detection circuit 31. A comparison operation instruction is given to each device 36.

[0024] The FAT memory address generation circuit 34
D in the received packet detected by the A detection circuit 31
A is compressed using certain compression data (generator polynomial) (preset by the microprocessor 40) at the address generation start instruction timing from the timing generation circuit 32 to generate a FAT memory address. Here, a 48-bit DA CRC code (approximately 8 to 16 bits) is generated as the FAT memory address.

On the other hand, the 48-bit DA holding register 3
5 performs a shift operation of sequentially inputting and shifting packets received via the serial interface from the beginning. This shift operation of the register 35 is stopped at the timing of a shift stop instruction from the timing generation circuit 32. At this time, the register 35 includes the DA detection circuit 31
The 48-bit DA in the received packet detected by is held.

Now, the FAT memory address generation circuit 34
The FAT memory address generated and output by
The data is supplied to the memory 33. As a result, the FAT address specified by the address from the FAT memory address generation circuit 34 is
An entry in the memory 33 is accessed at the memory access timing from the timing generation circuit 32, and filtering address information registered in the entry is read out.

The filtering address in the filtering address information read from the FAT memory 33 is D.
Comparator 3 together with DA held in A holding register 35
6. The comparator 36 is the timing generation circuit 32
The above two addresses are compared in accordance with a comparison operation instruction from , and a comparison result indicating match/mismatch is output. Comparator 36
The comparison result is supplied to the packet discard signal generation circuit 37. This packet discard signal generation circuit 37 is also supplied with the V bit in the filtering address information read from the FAT memory 33. Packet discard signal generation circuit 37
The comparison result of the comparator 36 indicates a match, that is, LAN1
If the destination of the received packet from 0 matches the address of the previously learned node and the V bit is on (if the filtering address information is valid), a packet discard signal 38 is output to the LAN controller 39. do. In this case, the LAN controller 39 discards the packet from the LAN 10 without receiving it.

Now, in addition to controlling read access to the FAT memory 33 described above, the timing generation circuit 32 also controls read access to the FAT memory 33.
The following write access control is performed according to the validity/invalidity (state of the V bit) of the filtering address information read from the FAT memory 33 by this read access, and the comparison result of the comparator 36.

First, when the filtering address information is valid and the comparison result of the comparator 36 shows a match (that is, when the packet discard signal 38 is output from the packet discard signal generation circuit 37), the timing generation circuit 3
2 rewrites (resets) the access count values in the same entry in the FAT memory 33 to all "0". One of the reasons for this rewriting is that once the address of a node on the LAN 10 is learned, the microprocessor 40 will no longer receive a reception event regarding a packet addressed to that node from the same LAN 10.
This is because the access count value "0" notifies the microprocessor 40 that a packet has been transmitted on the same LAN 10 addressed to that node. Another reason will be discussed later.

Next, the operation of the timing generation circuit 32 when the filtering address information is valid and the comparison result of the comparator 36 shows a mismatch will be explained. This case indicates that the same entry in the FAT memory 33 is redundantly allocated to the node specified by the filtering address in the filtering information and a destination node different from the same node. Although it is considered that such a situation rarely occurs, it is also possible that the compressed data (generating polynomial) used in the FAT memory address generation circuit 34 was not selected properly. Therefore, the timing generation circuit 32 turns on the O bit (duplication presence/absence bit) in the same entry of the FAT memory 33 in order to notify the microprocessor 40 of this event. Note that when the filtering address information is invalid, write access control to the FAT memory 33 by the timing generation circuit 32 is not performed.

Now, the microprocessor 40 sequentially refers to all entries in the FAT memory 33 at regular intervals, checks for valid entries whose V bit is on, and counts up the access count value in the entry. If packets whose destination address is the filtering address registered in that entry are received almost regularly, the access count value will reach a certain value (by the microprocessor 40's count-up operation). will be reset to On the other hand, if no reception is performed during a certain period, the access count value of that entry reaches a certain value.

When the microprocessor 40 detects an entry whose access count value has reached a certain value, the microprocessor 40 turns off the V bit in the entry to invalidate the entry. Therefore, entries whose access count values are reset almost regularly remain valid. This is another reason mentioned above.

If the microprocessor 40 attempts to access the FAT memory 33 at the same time as the timing generation circuit 32, the access request is arbitrated by the access arbitration circuit 41. In this case, the access request from the timing generation circuit 32 is prioritized, and the access from the microprocessor 40 is made to wait.

Furthermore, the microprocessor 40 appropriately checks for entries (duplicate entries) whose V bit (duplication presence/absence bit) is on among the valid entries in the FAT memory 33. If the ratio of duplicate entries exceeds the reference value, the microprocessor 40 determines that the compression data set in the FAT memory address generation circuit 34 is not appropriate. In this case, the microprocessor 40 temporarily invalidates all entries in the FAT memory 33, then rewrites the compression data in the FAT memory address generation circuit 34 to different data, and continues the operation. In this way, since the compression data optimal for the address of each node on the LAN 10 is automatically created and operated, even if the small capacity FAT memory 33 is used, the optimal filtering operation for the LAN 10 can be realized.

In the above embodiment, it is assumed that the FAT memory address generation circuit 34 is composed of a CRC circuit, and generates a FAT memory address by compressing the DA (destination address) using a generator polynomial for generating a CRC code. Although described above, the circuit is not limited to a CRC circuit as long as it compresses a DA using compression data.

Further, in the above embodiment, the discard control (packet filtering) of received packets from the LAN 10 was explained, but by providing the same configuration as in FIG. (Can be shared with the connection interface part of), L
Similar discard control can be performed for packets received from the AN 20 side. In addition, although we have explained the case where it is applied to a LAN-to-LAN connection device that connects bus-type LANs, it is also applicable to a LAN-to-LAN connection device that connects a bus-type LAN and a ring-type LAN, and furthermore, a LAN that connects ring-type LANs.
It is similarly applicable to interconnection devices.

Furthermore, in the above embodiment, by comparing the DA (destination address) of the received packet from the LAN with the data (learned filtering address) in the FAT memory 33 (by DA filtering), the discarding of the received packet is controlled. I explained the case where it is applied, but SA
By comparing the (source address) with data in the FAT memory 33, it can also be used for relay control. This SA filtering can be applied to a LAN-to-LAN connection device called a "transparent bridge," which requires a function to detect and discard packets relayed to a ring-type LAN that circulate around the same LAN and return.

[0038]

[Effects of the Invention] As detailed above, according to the present invention,
Discarding control of packets sent and received on the same LAN can be performed using a dedicated hardware circuit based on the filtering address learned by the microprocessor, so the microprocessor is freed from packet discard control, and relay The original work, mainly control, can be performed efficiently, and the performance of the entire device can be improved.

Further, according to the present invention, whether or not each entry of the table memory for registering filtering address information including filtering addresses is redundantly allocated to a plurality of nodes can be determined by checking the filtering address information in the filtering address information. The configuration is indicated by duplicate information, and when the rate of duplicate entries is high, the compression data used to generate the table memory address is rewritten to the optimal one, so even if a small capacity table memory is used. Optimal filtering can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a connection interface portion on a specific LAN side of an inter-LAN connection device according to an embodiment of the present invention.

[Figure 2] Two LANs are connected by the LAN connection device in Figure 1.
FIG. 2 is a block configuration diagram of a LAN system connected to the LAN system.

FIG. 3 is a format diagram of filtering address information registered in the FAT memory 33 shown in FIG. 1;

[Explanation of symbols]

10, 20... LAN, 30... LAN connection device, 31...
DA detection circuit, 32...timing generation circuit, 33...FA
T memory, 34...FAT memory address generation circuit, 35
...DA holding register, 36... Comparator, 37... Packet discard signal generation circuit, 39... LAN controller.

Claims (3)

[Claims] [Claim 1] L connecting at least two LANs
The inter-AN connection device includes a table memory having a plurality of entries for registering filtering address information including filtering addresses, and a table memory having a plurality of entries for registering filtering address information including filtering addresses;
An address learning function that receives a transmission packet from and registers filtering address information including the source address as a filtering address in the entry in the table memory specified by the table memory address generated by compressing the source address. a destination address detection circuit that receives a transmission packet from the specific LAN and extracts its destination address; and a destination address detection circuit that compresses the destination address extracted by the destination address detection circuit based on compression data. a table memory address generation circuit that generates an address of the table memory corresponding to the same address; and the filtering address information read from the table memory in accordance with the designation of the table memory address generated by the table memory address generation circuit. a comparison circuit that compares the filtering address in the filtering address with the destination address extracted by the destination address detection circuit; and a packet discard signal that instructs to discard the received packet from the specific LAN based on the comparison result of the comparison circuit. a packet discard signal generation circuit that outputs a packet discard signal generation circuit, and a packet discard received from the specific LAN is discarded by a packet discard signal from the packet discard signal generation circuit. 2. In the filtering address information, duplicate information indicating that a registered entry of the same information is redundantly assigned to multiple nodes is provided, and the comparison circuit detects a mismatch, and the table memory 2. The inter-LAN connection device according to claim 1, wherein when said filtering address information read from said filtering address information is valid, said duplicate information in said filtering address information is set to a duplicate display state. 3. The microprocessor generates the table memory address according to a ratio of entries in which the duplicate information is displayed in duplicate among the entries in the table memory in which the valid filtering address information is registered. 3. The LAN-to-LAN connection device according to claim 2, wherein compression data used for address generation in the circuit is rewritten.