JPH07101391B2 - Watch / dog / timer inhibit circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention is a watch that resets a microcomputer in a hardware manner when it abnormally operates, restarts it from an initial operation, and returns the operation to a normal state. -It relates to the dog timer.

[Conventional technology]

The watch dog timer is a routine that retriggers the watch dog timer in the operating program, and if the CPU cannot retrigger the watch dog timer within a certain period of time, the CPU will fail. By resetting the CPU after determining that the operation has been performed, the operation is restarted from the initial operation and then returned to the normal operation.

However, since it is not possible to always run a routine that retriggers the watch dog timer while testing or debugging a program, it is absolutely necessary to disable the watch dog timer.

Conventionally, as means for prohibiting the operation of the watch dog timer, there has been one shown in FIGS. 2 and 3.

In FIG. 2, 1 is a CPU, 2 is a watch dog timer, 3 is a CPU address bus, a data bus buffer, 4 is a ROM storing a program, 5 is RAM, 6 is an input / output unit (hereinafter "I / O"), and I / O6 also works by sending a pulse to the watchdog timer in software. 7 is a watch dog prohibition permission change switch,
8 is a capacitor that determines the time constant of the watch dog, 9
Is a power-on reset circuit. In the system of FIG. 2, a normal power-on reset circuit 9 composed of a combination of C, R and a diode is used as the reset input of the CPU in order to inhibit the watch dog.

FIG. 3 is a system diagram showing another means, in which the same or corresponding parts as those in FIG. 2 are designated by the same reference numerals. The system of FIG. 3 inhibits the watchdog by forcibly charging capacitor 8 when transistor 10 is turned on. In FIG. 3, the reason why the logic circuits 11 and 12 are required is that the power-on reset does not work if the capacitor 8 remains charged at the time of power-on.

[Problems to be Solved by the Invention]

Of the above-mentioned conventional means for prohibiting the watch dog, the means shown in FIG. 2 has a completely different reset circuit, so that even if the watch dog timer 2 has a built-in power supply voltage monitoring function. , Will be completely invalid.

Further, the means shown in FIG. 3 has a drawback in that although the function of monitoring the power supply voltage of the watch dog timer 2 works, there are many external parts and the prohibition circuit becomes complicated.

[Means for Solving the Problems]

In order to eliminate such drawbacks, the present invention provides an ALE signal, an RD signal, a WR signal, an RD signal, a WR signal, which are output from the CPU, in a circuit for inhibiting the operation of the watch dog timer which has a role of monitoring the abnormal operation of the CPU. A watch dog prohibition permission changeover switch for prohibiting the operation of the watch dog timer by adding a control signal such as a chip select signal as a retrigger pulse to the watch dog timer is provided.

[Action]

In the watch dog timer prohibiting circuit according to the present invention, the watch dog can be prohibited with a simple circuit having a small number of parts, and the power-on reset and power supply voltage monitoring functions of the watch dog timer can be utilized. .

〔Example〕

FIG. 1 is a system diagram showing an embodiment of a watch dog timer prohibiting circuit according to the present invention. In FIG.
1 is a CPU, 2 is a watch dog timer, 3 is a CPU address bus, a data bus buffer, 4 is a ROM storing a program, 5 is RAM, 6 is an input / output unit (hereinafter referred to as "I /
"O"), and I / O6 may also work by sending a pulse to the watchdog timer in software. Reference numeral 7 is a watch dog prohibition permission changeover switch, and 8 is a capacitor for determining the time constant of the watch dog.

In the watch dog timer prohibit circuit according to the present invention,
The watchdog prohibition is realized by adding the ALE signal of the CPU1 to the clock input terminal CK of the watchdog timer 2. In this method, instead of retriggering the watch dog timer 2 by a program, a signal periodically output from the CPU 1 is used to retrigger it in hardware. In this circuit, the reset output of the watch dog timer 2 and the capacitor that determines the time constant are in the same state as when the watch dog is not disabled, so the function of the watch dog timer 2 is not impaired. In addition, the power-on reset and the reset function by monitoring the power supply voltage are effective, and the number of parts can be significantly reduced. Also, for some reason, CPU1 becomes abnormal.
Since the reset is applied when the CPU control signal is interrupted, it is possible to keep the CPU1 operating normally without incorporating a retrigger routine for the watch dog timer of the program.

Although the ALE signal is used as the retrigger pulse of the watch dog timer in this embodiment, the same effect can be obtained by using other CPU control signals such as the RD signal, the WR signal, and the chip select signal.

〔The invention's effect〕

As described above, the present invention provides a watchdog timer that inhibits the operation of the watchdog timer by adding the control signal output from the CPU to the watchdog timer.
By providing the dog prohibition permission changeover switch, the watchdog can be prohibited with a simple circuit with a small number of parts, and the power-on reset of the watchdog timer and the power supply voltage monitoring function can be effectively used. is there. In addition, when the CPU fails for some reason and the control signal stops, the control signal is reset and the CPU returns to normal. In this respect, it is more reliable than the conventional watch dog timer prohibit circuit.

INDUSTRIAL APPLICABILITY The present invention can be applied to all microcomputer application circuits, and in particular, it has a great advantage when it is used in a device that requires miniaturization and reliability.

[Brief description of drawings]

FIG. 1 is a system diagram showing a watch dog timer inhibiting circuit according to the present invention, and FIGS. 2 and 3 are system diagrams showing a conventional watch dog timer inhibiting circuit. 1 ... CPU, 2 ... Watchdog timer, 3 ...
Buffer, 4 …… ROM, 5 …… RAM, 6 …… I / O, 7 ……
Watch dog prohibition permission changeover switch, 8 ... Capacitor.

Claims (1)

[Claims] 1. A circuit for prohibiting the operation of a watch dog timer, which has a role of monitoring an abnormal operation of a CPU,
Watchdog prohibit enable / disable switch for prohibiting the operation of the watchdog timer by adding control signals such as ALE signal, RD signal, WR signal, and chip select signal output from the CPU to the watchdog timer as retrigger pulses A watch dog timer prohibition circuit characterized by having a switch.