JPH0697920A - Radio receiving equipment - Google Patents

Abstract

PURPOSE:To effectively execute reception even in the case of a response speed to a receiving signal level is increased and a receiving signal level fluctuation is quick little by little by detecting a receiving signal by dividing it into a phase modulation component and an amplitude modulation component, and thereafter, synthesizing them. CONSTITUTION:A first receiving wave from a terminal 11 passes through a limiter amplifier 21 and is supplied to a phase detecting circuit 31 and a phase modulation component of the receiving wave is detected, and outputted through a reproducing circuit 41. On the other hand, an envelope detecting circuit 61 is averaged by an average arithmetic circuit 91, an amplitude modulation component is detected, and both the components are synthesized and demodulated by a synthesis/demodulation processing circuit 5. With respect to a second receiving wave from a terminal 12, as well, the same processing executed, feedback control, etc., are unnecessary and the equipment is not influenced by a time constant, etc., and even in the case of a response speed to a level receiving signal can be increased and a receiving signal level fluctuation is quick little by little, reception is executed effectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a radio receiver for demodulating a linear modulation signal. The present invention is suitable for use in mobile radio communication. INDUSTRIAL APPLICABILITY The present invention is suitable for use in wireless communication for receiving burst signals and time division multiple access (TDMA) communication. The present invention is suitable for wireless communication in which the reception level changes rapidly due to fading or the like. The present invention has a great effect when used for diversity reception.

Here, the linear modulation signal means a signal including both a phase modulation component and an amplitude modulation component modulated by the same modulation signal. In this specification, "phase modulation"
Is defined as a concept including phase modulation and frequency modulation in a narrow sense.

A linearly modulated signal is a digital signal which is inevitably accompanied by an amplitude modulation component by allowing a phase-modulated signal to pass through a filter having a narrow pass frequency band in order to effectively use radio waves. It is widely used in mobile radio communication systems of modulation or analog voice modulation.

[0004]

2. Description of the Related Art When a modulated wave is received by radio communication or the like, the level of the received wave is often greatly changed due to the influence of fading or the like. When the modulation format is constant amplitude modulation such as frequency modulation (FM), a limiter amplifier is used as a reception amplifier. At this time, the amplitude of the output becomes constant irrespective of the input level, but since the frequency or phase is originally modulated with a constant amplitude, there is no deterioration of the transmission characteristics due to the constant amplitude.

On the other hand, the linear modulation method, which is more efficient in frequency utilization than the constant amplitude modulation, cannot apply the above-described limiter amplifier because the amplitude component also has information. Therefore, in general, in order to receive a linearly modulated wave, an automatic gain adjustment type (AG
C) Linear amplification detectors using amplifiers have been used.
A conventional example will be described with reference to FIG. FIG. 18 is a block diagram of a conventional device. FIG. 18A shows a configuration for performing diversity reception. 18B shows a specific example of the linear amplification detectors 54 and 55 in FIG. 18A. The signal received by the antenna of the diversity receiver is amplified and frequency-converted, passes through the bandpass filters 50 and 51, is amplified by the AGC amplifier 60, and the complex envelope is extracted by the IQ detector 61.
Further, the envelope component of the signal amplified by the AGC amplifier 60 is extracted by the envelope detector 62, and the average level of the output signal is made constant via the gain control circuit 63.
The gain of the amplifier 60 is controlled. In addition, the gain control signal 6
4 is also output for diversity combination.

Various methods can be considered for the diversity combining process. FIG. 18A shows a method when a pseudo random signal for amplitude / phase estimation is inserted in a transmission signal. The operation of the amplitude and phase estimators 52 and 53 will be described in detail below. This pseudo-random signal is used as the amplitude / phase estimator 5
Input to a correlation detector (not shown) at 2 and 53,
When the complex correlation is taken, the amplitude and phase of the carrier component of the complex envelope are extracted. The actual level of the received wave is obtained by performing correction according to the gain of the AGC amplifier 60 with the amplitude extracted by the correlation. First, the phase and amplitude of the carrier component extracted by the complex correlation are represented by the complex amplitude w _n . For w _n , generate its complex conjugate w _n ^* . Since the complex envelope and the complex amplitude w _n are extracted from the AGC amplified signal, the true input level value cannot be obtained without correcting the gain of the AGC amplifier 60 in the linear amplification detectors 54 and 55. Therefore, the gain of each branch is corrected. First, it is necessary to divide the complex envelope of each branch by the amplitude gain G _on of each branch. Similarly, the complex conjugate w _n ^* needs to be w _n ^* / G _on .
In FIG. 18, the complex multipliers 56 and 57 of each branch perform the weighting of these two correction diversity combinations at the same time. That is, a product signal of the complex envelope and w _n ^* / G _on ² is created and synthesized. Finally, the combined signal is judged and the result is output. Although the above description is a method for obtaining the maximum ratio combination, a complex envelope having a high level is selected from the gain control signal, that is, the complex conjugate w _n.
Selective synthesis can be obtained by setting ^* to 0 or 1. further,
If w _n ^* / (G _ON | w _n |) is multiplied, the complex envelope has a gain correction of 1 / G _on , and all the branches have a gain of 1. Therefore, the product signals of the respective branches are combined. Gives equal gain combining.

[0007]

When the automatic gain control circuit connected to the negative feedback is used in the main circuit for demodulating the linear modulation signal as described above, the time constant of the negative feedback is set to a large value for stable control. is necessary. Therefore, although it responds well to slow fluctuations in the received signal level, when the fluctuations in the received signal level are small and fast, a control delay occurs in the control loop and the average output level cannot be kept constant. That is, when the fading repetition period is short, sufficient response characteristics cannot be obtained, and the effect cannot be effectively exhibited even when diversity reception is performed. Further, in a method of transmitting and receiving burst signals intermittently, such as a time division multiple access (TDMA) communication method, the reception level becomes unstable at the beginning and end of the burst signal, which causes information error. It becomes impossible to use it properly.

The present invention is to improve this. A linear modulation signal which has a fast response speed, can be effectively received even when the level fluctuation of the received signal is small and fast, and is stable in operation. It is an object of the present invention to provide a receiving device of. INDUSTRIAL APPLICABILITY The present invention is effective even when the repeating cycle of fading is short, is effective when performing diversity reception, and intermittently transmits and receives burst signals as in a time division multiple access (TDMA) communication system. It is an object of the present invention to provide a receiving device that is effective for the system.

[0009]

A feature of the present invention is that an envelope signal which is an amplitude modulation component and a phase demodulation signal which is a phase modulation component are separately detected and then a complex envelope signal is reproduced. Detect the envelope of the signal, perform processing to suppress fluctuations in the average level of the envelope signal, use limiter means to demodulate the phase modulation component, and use the detected average level for diversity reception. Is possible.

The present invention is different from the prior art using an automatic gain control circuit including a negative feedback loop with a large time constant in the prior art.
They are different in that there is no loop with a large time constant, level normalization processing is performed with an envelope signal instead of a carrier signal, and limiter means can be used in spite of linear reception.

That is, the present invention is provided with a plurality of input terminals to which the received signals from the receiving circuits of the different systems, each of which serves as a diversity branch, are input, and the envelope detection means and the phase detection means to which the signals of these input terminals are input. And a reproducing means for reproducing a complex envelope signal from each output signal of the envelope detecting means and the phase detecting means are provided corresponding to the diversity branch, and the output of the reproducing means for each diversity branch is spread over a plurality of diversity branches. And a demodulation processing circuit for performing demodulation processing by synthesizing, the envelope detection means,
An envelope detection circuit that detects an envelope signal from the signal of the input terminal, an average calculation circuit that calculates a level average value of the envelope signal detected by the detection circuit, and an output envelope signal of the envelope detection circuit. And a normalization circuit for normalizing the output level average value of the average calculation circuit is averaged over the plurality of diversity branches to provide an average value control circuit as a reference of the normalization circuit of each diversity branch, further comprising: The phase detection means includes limiter means for limiting the amplitude of the signal to be phase-detected.

It is preferable that the conversion function of the envelope detection circuit is a non-linear function, and the output of the normalization circuit includes an inverse conversion circuit for processing an inverse conversion function corresponding to the nonlinear function.

It is preferable that the inverse conversion circuit holds a plurality of kinds of inverse conversion functions and adaptively selects one of the plurality of kinds of inverse conversion functions with respect to the demodulated signal.

The synthesis demodulation processing circuit may be configured to be controlled by applying the output of the average arithmetic circuit for each diversity branch as a control signal.

The envelope detection circuit may include a level adjustment circuit.

A buffer circuit for temporarily holding the output of the envelope detection circuit may be provided, and in this case, all processing may be digital processing.

It is preferable to provide means for adjusting the relative delay of each output signal of the envelope detecting means and the phase detecting means input to the reproducing means.

The present invention can be implemented even when diversity reception is not used. In this case, from one input terminal to which the received signal is input, the envelope detection means and the phase detection means which receive the signal of this input terminal, and the respective output signals of this envelope detection means and the phase detection means. And a reproducing means for reproducing a complex envelope signal, wherein the envelope detecting means includes an envelope detecting circuit for detecting an envelope signal from the signal at the input terminal, and an envelope signal detected by the detecting circuit. An averaging circuit that calculates the level average value,
A normalization circuit for normalizing the output envelope signal of the envelope detection circuit by the output level average value of the averaging circuit, and the phase detection means includes limiter means for limiting the amplitude of the signal for phase detection. It is characterized by including.

In the above description, a comparison with the prior art which uses an automatic gain control circuit including a negative feedback loop is described, but this does not mean that the automatic gain control circuit should not be used, and the present invention does not. It is possible to use an automatic gain control circuit with a small constant together.

[0020]

Since the amplitude modulation component and the phase modulation component are demodulated by separate circuits from the received signal, the circuit for demodulating the amplitude modulation component can be provided with a limiter to limit the amplitude. This makes it possible to reduce noise.

Even if the automatic gain control is not performed, the envelope of the received signal is detected, and the process of suppressing the variation of the average level of the envelope signal is performed (feedforward), so that the variation of the received signal level can be dealt with. , Its response speed can be reduced.

The detection of this average level can be used for diversity combining processing.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a first embodiment device of the present invention.

The present invention is provided with a plurality of input terminals 1 ₁ and 1 ₂ to which the reception signals from the reception circuits of different systems, which are the diversity branches respectively, are input, and the signals of the input terminals 1 ₁ and 1 ₂ are input and received, respectively. Envelope detecting circuits 6 ₁ and 6 ₂ which are envelope detecting means and a phase detecting circuit 3 which is phase detecting means.
_1, 3 ₂ and, the envelope detection circuit 6 _1, 6 ₂ and the phase detector circuit 3 _1, 3 reproducing circuit 4 ₁ is from ₂ of each output signal reproduction means for reproducing the complex envelope signals, 4 ₂ and is A demodulation processing circuit 5 provided for the diversity branches and combining the outputs of the reproduction circuits 4 ₁ , 4 ₂ for each diversity branch over a plurality of diversity branches to perform demodulation processing;
The envelope detection circuits 6 ₁ and 6 ₂ detect envelope signals from the signals of the input terminals 1 ₁ and 1 ₂ , and the envelope detection circuits 6 ₁ and 6 ₂ ,
Averaging circuits 9 ₁ and 9 ₂ for computing the level average value of the envelope signal detected by 6 ₂ and the envelope detecting circuit 6 ₁ .
A normalization circuit 7 ₁ , 7 for normalizing the output envelope signal of 6 _2.
And an average value control circuit 10 including ₂ and averaging the output level average values of the average arithmetic circuits 9 ₁ and 9 ₂ over the plurality of diversity branches and giving the average value as a reference of the normalization circuits 7 ₁ and 7 ₂ of each diversity branch. Equipped with the phase detection circuit 3
_1, 3 ₂ is a radio receiving apparatus characterized in that it comprises a limiter amplifier 2 _1, 2 ₂ a limiter means for limiting the amplitude of the signal phase detection. The first embodiment device of the present invention is 2
It has a branch diversity branch.

Next, the operation of the first embodiment of the present invention will be described. Received wave S of nth, where 1 ≦ n ≦ 2 = N
_n (t) it _{is, S n (t) = R} e [E n expj (2πf c t)] ... is (1). However, _Re () represents the real part in (), and E _n (t) represents the complex envelope of S _n (t). The envelope R _n (t) of the received wave is R _n (t) = | E _n (t) | (2) The signal phase θ _n (t) is θ _n (t) = Arg [E _n (t )] (3). First, the envelope detection circuits 6 ₁ and 6 ₂ convert R _n (t) by the following equation using a certain function f (), and output the level signal r _n (t). This r _n (t) becomes r _n (t) = f [R _n (t)] (4). The averaging circuits 9 ₁ and 9 ₂ receive the level signal r
_n an average value m _n of (t) (t) using a time constant T _m,

[0026]

[Equation 1] Calculate with. The average value control circuit 10 receives the _{1st to} N-th average values m ₁ (t), m ₂ (t), ..., M _n (t) as input, and normalizes the N number of values using a certain function h (). For average value m
Output _sn (t). When m _sn (t) is expressed by the following equation, m _sn (t) = h [m ₁ (t), m ₂ (t), ..., M _n (t)] (6), and the normalization circuit 7 ₁ , 7 ₂ outputs the normalized level signal r _mn (t) according to r _mn (t) = g [r _n (t), m _sn (t)] (7) using this m _sn (t). To do. The inverse conversion circuits 8 ₁ and 8 _{2 receive the} normalized level signal r _mn (t).
And the normalized average value m _sn (t), R _mn (t) = f ⁻¹ [r _mn (t), m _sn (t)] (8) Output R _mn (t). On the other hand, the limiter amplifier circuits 2 ₁ and 2 ₂ amplify the n-th received wave S _n (t) with a very large gain and output a constant amplitude signal S _cn (t). This constant amplitude signal S
_cn (t) _{is, S cn (t) = R} e {Aexp [j2πf c t + jθ n (t)]} ... a (9). However, A is a constant value. The phase detection circuits 3 ₁ , 3 ₂ receive the received wave phase θ from the constant amplitude signal.
A phase display signal representing _n (t) is output. Signal as the phase indication signal representing directly the θ _n (t), _{or, exp [jθ n (t)} ] = cosθ n (t) + jsinθ signals representing the _n (t) can be considered. The reproduction circuits 4 ₁ and 4 ₂ generate the reproduced complex envelope signal E _rn (t) using the normalized envelope signal R _mn (t) and the phase display signal. Finally, the synthesis demodulation processing circuit 5 receives the 1st to Nth complex envelope signals as inputs, synthesizes these signals, and performs demodulation. The composite demodulation processing includes AFC processing, equalization, clock extraction and signal determination. The details of the operation of each circuit will be described below.

First, the envelope detection circuits 6 ₁ and 6 ₂ are paired with the inverse conversion circuits 8 ₁ and 8 ₂ . That is, the transformation y = f (x) of the envelope detection circuits 6 ₁ and 6 ₂ performs x = f ⁻¹ (y) in the inverse transformation. The most general envelope detection means is square-law detection, that is, There is a method using f (x) = x ² . At this time, the inverse transformation is a square root, that is, f ⁻¹ (x) = x ^1/2 . However, this method cannot be applied to radio received waves with a dynamic range of several tens of dB. Therefore, a logarithmic level detector, that is, a logarithmic function f (x) = klogx is used. At this time, the inverse transformation becomes an exponential function, that is, f ⁻¹ (x) = exp (x / k).

The envelope detection circuit 6 _1, a 6 _second configuration shown in FIG. FIG. 2 is a block diagram of the envelope detection circuits 6 ₁ and 6 ₂ . Envelope in the logarithmic level detector 11 is logarithmically converted by _{r n (t) = klog [} R n (t)] ... (10). The reduction filter 12 removes the refractory component of the frequency such as the carrier component, and the AD converter 13 converts it to a digital signal.

Next, the configuration of the inverse conversion circuits 8 ₁ and 8 ₂ is shown in FIG.
Shown in. In the inverse conversion circuits 8 ₁ and 8 ₂ , the normalized level signal r
_mn (t) is exponentially converted by R _mn (t) = exp [r _mn (t) / k] (11) to output a normalized envelope signal R _mn (t). This circuit is a DSP (Data storage processor)
Alternatively, it can be realized by using a ROM table.
When this logarithmic conversion is performed, g () in the normalization circuits 7 ₁ and 7 ₂ may be simply subtraction, and g [r _n (t), m _sn (t)] = r _n (t) −m _sn (t ) ... (12) It is convenient to use a table when performing the logarithmic / exponential conversion described above, but if the range of the input level is wide, the scale of the table becomes large, so processing is performed to limit the level to a certain range. Therefore, the signal is normalized using the average value. There are two possible ways to use the average value. First, in the average value control circuit 10, from the _{1st to} Nth average values m ₁ (t), m ₂ (t), ..., M _n (t), the one having the largest value is the normalization average value m _sn ( There is a method of outputting as t), that is, h (x) = max (x). At this time, m _sn (t) = max [m ₁ (t), m ₂ (t), ..., M _n (t)] (13) However, max () is a function that finds the maximum value in (). According to this method, since the average value with the highest level is selected, the signals after normalization of the received waves of the branch with the highest level always have the same level. Further, since the average value for normalization is one value, it corresponds to the fact that the gains of all the branches are the same. However, in the above-described method, it is necessary to obtain the maximum value, and it is necessary to prepare a table for a small level in order to accurately reproduce a signal having a small level. In the control circuit 10, the _{1st to} Nth average values m ₁ (t), m ₂ (t), ..., M _n (t) are directly used as the normalization average value m _sn (t) of each branch.
That is, m _sn (t) = m _n (t) (14) In this way, the signals of the received waves of the respective branches are always at the same level, so that an exponential function table with a small range may be prepared.

Next, referring to FIG. 4, the phase detection circuit 3 ₁ ,
3 ₂ of the operation will be described. FIG. 4 shows the phase detection circuit 3 ₁ ,
3 ₂ is a block diagram of a. Using the IQ detector 61, the quasi-synchronized local oscillator 42 extracts the amplitude components of the in-phase component and the quadrature component from the outputs of the limiter amplifiers 2 ₁ and 2 ₂ . In this method, the signal phase θ _n (t) is output corresponding to the two phase display signals cos θ _n (t) and sin θ _n (t).

Next, the reproducing circuits 4 ₁ and 4 ₂ for inputting the normalized envelope signal and the phase display signal will be described with reference to FIG. FIG. 5 is a block diagram showing a reproducing circuit. FIG. 5 shows that the phase display signals cos θ _n (t) and sin θ _n (t) are input from the terminals I ₁ and I _2, and the normalized envelope signal from the terminal R is multiplied using the two multipliers 71 and 72. To do.

As the combination demodulation processing circuit 5, the selective combination, the equal gain combination and the maximum ratio combination described in the prior art can be applied, and therefore the detailed description will be omitted.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram of a second embodiment device of the present invention. In the first embodiment of the present invention, the basic operation is premised on a real-time operation, but since complicated processing is frequently used, digital signal processing is desirable. The device of the second embodiment of the present invention has a configuration suitable for digital signal processing. The feature of the second embodiment of the present invention is that it has four buffers 90 to 93 for accumulating the level signal r _n (t) and the phase display signal for a certain period of time. The normalization circuits 7 ₁ and 7 ₂ remove the fluctuations in the average level of the envelope based on the results of the average calculation circuits 9 ₁ and 9 ₂ , but if there are no buffers 90 to 93, they are as shown in equation (5). The average value used for level normalization is the value obtained from the past envelope. Therefore, when the level fluctuation becomes fast, there is a delay, and there is a possibility that the tracking cannot be performed accurately. The second embodiment of the present invention aims to accurately follow such a high-speed level fluctuation. First, the envelope data detected by the envelope detection circuits 6 ₁ and 6 ₂ are accumulated in the buffers 90 and 91. Buffer 90 and 91 and signals _{kT m ≦ t ≦ (k +} 1) T m is accumulated length as T _m. Note that since the signals are actually received in real time, the buffers 90, 9
A number of 1's are required in parallel, but here, it is assumed that there is one buffer memory. Thus, a single memory is sufficient for receiving burst signals. However, the memory length must match the burst length. Next, when data is extracted from this accumulated data and the average value is calculated,

[0034]

[Equation 2] Becomes Further, the envelope data used when obtaining the average value is again taken out from the buffers 90 and 91, and the average level of the level signal r _n (t) is normalized using the calculated average value. Data output destinations from the buffers 90 and 91 are controlled by switches 94 and 95. This switch 9
By means of Nos. 4 and 95, the average value used at the time of level normalization becomes data extracted at the same timing as the data of the envelope, and it is possible to accurately follow high-speed level fluctuations. The buffers 92 and 93 of the outputs of the phase detection circuits 3 ₁ and 3 ₂ have a function of adjusting the difference in processing speed from the envelope processing side and matching the processing timing in the reproduction circuits 4 ₁ and 4 ₂ . With the above operation, the average level can be accurately normalized.
The configuration and operation of each circuit not described here are the same as those of the first embodiment of the present invention.

Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows an envelope detection circuit 6 ₁ , 6 _2.
It is a figure which shows the input-output characteristic example of. FIG. 8 is a block diagram of the essential parts of a third embodiment of the present invention.

When the envelope detection circuits 6 ₁ and 6 ₂ cannot have a sufficient dynamic range, for example, they become constant at a low input level or a high input level, which may cause a large difference from the logarithmic conversion. Therefore, the third embodiment of the present invention is characterized by having a level adjustment circuit 150 for adjusting the input levels of the envelope detection circuits 6 ₁ and 6 ₂ based on the average value as shown in FIG. As shown in FIG. 7, the dynamic range, that is, P ₁
From P to P ₂ is usually 40 dB or more, but when it is still insufficient, the third embodiment of the present invention becomes effective. In the input / output characteristics, when the input is P ₁ or less and P ₂ or more, the dynamic range of the envelope detection circuits 6 ₁ and 6 ₂ is exceeded, so that the linearity is poor and the output is distorted. In this way, when the input exceeds the dynamic range of the envelope detection circuits 6 ₁ and 6 ₂ , the level adjustment circuit 150 adjusts the input level. The level adjusting circuit 150 can be composed of a linear amplifier or an attenuator. Here, the average arithmetic circuit 9 ₁ ,
Since the output of 9 ₂ is used as a control signal, it has a field back loop. The level adjusting circuit 150 of the third embodiment of the present invention aims to adjust the input level so as not to exceed the dynamic range of the envelope detecting circuits 6 ₁ and 6 ₂ , and the level adjusting range is the same as that of the conventional AGC amplifier. Compared to small, the loop stability is high. This point is different from the conventional AGC amplifier.

In the first and second embodiments of the present invention, when the reproduction circuits 4 ₁ and 4 ₂ generate the reproduction complex envelope, the normalized envelope and the original signal represented by the phase display signal are the same. This is very important. However, it should be noted that the processing delay differs depending on various processes.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram of the essential portions of the fourth embodiment of the present invention. The fourth embodiment of the present invention is characterized in that it has a delay adjusting circuit 160 for adjusting the input timings of the normalized envelope signal and the phase display signal to the reproducing circuits 4 ₁ , 4 ₂ . In the present invention, the phase of the received wave and the envelope are processed separately. If there is a difference in processing time between the phase and the envelope, the reproduction circuit 4
_A time difference occurs when inputting to ₁ and 4 ₂ , and an error occurs in the reproduced complex envelope. The fourth embodiment of the present invention is configured to eliminate such a time difference. In the processing of the phase and the processing of the envelope, the processing time is adjusted by inserting the delay adjusting circuit 160 in the faster processing speed. The delay adjusting circuit 160 can be easily constructed by using a shift register in digital processing which is sampled at a sufficiently high speed, and can be constructed by using a delay line or a low-pass filter in analog processing. In both of FIGS. 9A and 9B, the delay adjustment is performed just before the reproduction circuits 4 ₁ and 4 ₂ .
Other locations may be used as long as the same effect can be obtained. Further, when the sampling rate is not as high as twice the symbol rate, it is necessary to adjust the minute delay amount equal to or less than the sampling rate. Therefore, the delay adjustment circuit 160 detects the envelope so that the signals to be sampled are essentially the same. Or it must be placed immediately after the phase detection circuit.

Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a block diagram of the essential parts of a fifth embodiment of the present invention. The fifth embodiment of the present invention is characterized in that it has calibration means for calibrating the characteristics of each circuit. However, since the outputs of the limiter amplifiers 2 ₁ and 2 ₂ and the envelope detection circuits 6 ₁ and 6 ₂ are the same, the description is omitted. FIG. 10 has a calibration signal generator 180 inside the receiver, and calibrates the characteristics of each unit according to the calibration signal.

Next, a sixth embodiment of the present invention will be described with reference to FIG. FIG. 11 is a schematic view of the essential portions of the sixth embodiment of the present invention. In the sixth embodiment of the present invention, in the case of N-branch diversity configuration, the antenna is switched by the input switch 190 so that the same signal is received in all the branches in order to eliminate the variation in characteristics among the branches. , The characteristics of each part are calibrated so that the same complex envelope is obtained.

Next, the seventh and eighth embodiments of the present invention will be described with reference to FIGS. FIG. 12 is a diagram showing a π / 4 shift QPSK signal. FIG. 13 is a diagram showing a code error rate when an equalizer is used. FIG. 14 is a block diagram of the seventh embodiment of the present invention. FIG. 15 is a block diagram of an eighth embodiment of the present invention. A feature of the seventh and eighth embodiments of the present invention is that it has a function of correcting a mismatch between the logarithmic characteristic of the envelope detection circuits 6 ₁ and 6 ₂ and the exponential function characteristic of the inverse conversion circuits 8 ₁ and 8 ₂ . The constant k in the equation (10) may change depending on the average level of the inputs of the envelope detection circuits 6 ₁ and 6 ₂ . It is also conceivable that the value of k may change due to environmental changes such as temperature changes. Such a change in the value of k causes a mismatch with the exponential function characteristics of the inverse conversion circuits 8 ₁ and 8 ₂ . Constants logarithmic characteristic and k _l, a constant k _r which represents the discrepancy when the constant of the exponential function characteristic was K _e

[0042]

[Equation 3] And How the signal is distorted by the value of k _r is π / 4 shift QPSK signal (roll-off rate α =
0.5) is shown as an example in FIG. Also, the bit error rate (BER) when an equalizer based on the value of k _r is used is shown in FIG.
3 shows. The seventh and eighth embodiments of the present invention have such k
The purpose of this is to improve by the correction function when a mismatch of the exponential function characteristics of the inverse conversion circuits 8 ₁ and 8 ₂ occurs due to the variation of the value of. In the seventh embodiment of the present invention, the average arithmetic circuit 9
_The exponential function conversion table corresponding to the control signal using the outputs of ₁ and 9 ₂ and the temperature sensor is calculated by the CPU 200 and written in the RAM 202 to correspond to the change of the value of k. However, with this method,
Since the rate of change is high with respect to changes in the value of k due to level changes, it is necessary to rewrite the RAM frequently. Therefore, in the eighth embodiment of the present invention, R of exponential function conversion corresponding to m kinds of values of k (k ₁ , k ₂ , ..., K _m ).
An OM table 204 is prepared, and these are switched by a control signal using an average value m _n (t) representing a level so that a change in the value of k can be dealt with.

In the first to eighth embodiments of the present invention, the phase detection circuits 3 ₁ and 3 ₂ may have the configuration shown in FIG. 16 or 17. 16 and 17 are diagrams showing other configurations of the phase detection circuits 3 ₁ and 3 ₂ . According to the configuration of FIG. 16, the output S _ln (t) of the low-pass filter 12 for removing the harmonic component of the limiter-amplified received wave is

[0044]

[Equation 4] Can be expressed as S _ln (t) is sampled by the AD converter 13 using a sampling clock that is four times the carrier frequency f _c . Further, the sampling clock is divided by 4 by the divide-by-4 circuit 84 to generate two signals having a frequency f _c and a phase difference of 90 °. The phase display signals cos θ _n (t) and sin θ _n (t) can be extracted by switching the switch of the switch 83 using the clock divided by four.

According to the configuration of FIG. 17A, θ _n
(T) is directly obtained. The counter 81 counts with a clock of M times the carrier frequency f _c , and outputs the count number at the rising edge of the rectangular wave of the outputs of the limiter amplifiers 2 ₁ and 2 ₂ . When the time of the _qth rising edge is t _q and the count number at this time is C _n (t _q ), C _n (t _q ) is

[0046]

[Equation 5] Can be expressed as However, [x] is an integer that does not exceed x.
The first term on the right side of the equation (18) represents the count number during non-modulation, and the second term represents the change in the count number depending on the signal phase θ _n (t). Therefore, in the phase converter 82, (1
When the count number C _n (t _q ) is converted into the phase θ _n (t) by the following equation obtained by modifying the equation 6),

[0047]

[Equation 6] Becomes Since there is an error of ± π / M in this conversion, M needs to be a sufficiently large value. According to such a method, it is possible to obtain a means for extracting a phase display signal that does not require an AD converter. Further, there is an advantage that it can be easily realized by a digital circuit. In this case, c shown in FIG.
The in-phase and quadrature components may be obtained by the os converter 85 and the sin converter 86, and then the product may be obtained. The cos converter and the sin converter can be easily configured by using a ROM table.

[0048]

As described above, according to the present invention, the response speed to the reception level is fast, and the reception signal can be effectively received even when the level fluctuation of the reception signal is small and fast, and its operation is It is stable.

The present invention is also effective when the repeating cycle of fading is short, effective when diversity reception is performed, and time division multiple access (TDMA).
It is also effective for a method of intermittently transmitting and receiving a burst signal such as a communication method.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of an envelope detection circuit.

FIG. 3 is a block diagram of an inverse conversion circuit.

FIG. 4 is a block diagram of a phase detection circuit.

FIG. 5 is a block diagram of a reproduction circuit.

FIG. 6 is a block diagram of a second embodiment of the present invention.

FIG. 7 is a diagram showing an input / output characteristic example of an envelope detection circuit.

FIG. 8 is a configuration diagram of main parts of a third embodiment of the present invention.

FIG. 9 is a configuration diagram of main parts of a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram of a main part of a fifth embodiment of the present invention.

FIG. 11 is a main part configuration part of a sixth embodiment of the present invention.

FIG. 12 is a diagram showing a π / 2 shift QPSK signal.

FIG. 13 is a diagram showing a code error rate when an equalizer is used.

FIG. 14 is a configuration diagram of a main part of a seventh embodiment of the present invention.

FIG. 15 is a configuration diagram of a main part of an eighth embodiment of the present invention.

FIG. 16 is a diagram showing another configuration of the phase detection circuit.

FIG. 17 is a diagram showing another configuration of the phase detection circuit.

FIG. 18 is a block diagram of a conventional example.

[Explanation of symbols]

1 ₁ 1 ₂ Input terminals 2 ₁ 2 ₂ Limiter amplifier 3 ₁ 3 ₂ Phase detection circuit 4 ₁ 4 ₂ Regeneration circuit 5 Synthetic demodulation processing circuit 6 ₁ 6 ₂ Envelope detection circuit 7 ₁ 7 ₂ Normalization Circuits 8 ₁ and 8 ₂ Inverse conversion circuit 9 ₁ and 9 ₂ Average arithmetic circuit 10 Average value control circuit 11 Logarithmic level detector 12 Low-pass filter 13 AD converter 41 Synchronous circuit 42 Local oscillator 50, 51 Bandpass filter 52, 53 Amplitude / phase estimator 54, 55 Linear amplification detector 56, 57 Complex multiplier 60 AGC amplifier 61 IQ detector 62 Envelope detector 63 Gain control circuit 71, 72 Multiplier 81 Counter 82 Phase converter 83 Switcher 84 4 minutes Circular circuit 85 cos converter 86 sin converter 90, 91, 92, 93 buffer 94, 95 switcher 150 level adjusting circuit 160 delay adjusting circuit 180 calibration signal Raw device 181,182,190 input switching unit 200 CPU 202 RAM 204 ROM table

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 2, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

[Procedure 3]

[Document name to be corrected] Drawing

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

[Figure 8]

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 10

[Correction method] Change

[Correction content]

[Figure 10]

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 11

[Correction method] Change

[Correction content]

FIG. 11

[Procedure correction 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 18

[Correction method] Change

[Correction content]

FIG. 18

Claims (8)

[Claims] 1. An envelope detecting means and a phase detecting means, each of which has a plurality of input terminals to which a reception signal from a receiving circuit of a different system, which is a diversity branch, is input, Reproducing means for reproducing a complex envelope signal from each output signal of the envelope detecting means and the phase detecting means is provided corresponding to the diversity branch, and the output of the reproducing means for each diversity branch is combined over a plurality of diversity branches. A synthetic demodulation processing circuit for performing a demodulation process, wherein the envelope detecting means detects an envelope signal from the signal at the input terminal, and an average level of the envelope signals detected by the detection circuit. An average calculation circuit for calculating a value and a normalization circuit for normalizing an output envelope signal of the envelope detection circuit, and an output level of the average calculation circuit. An average value control circuit for averaging an average value over the plurality of diversity branches and giving the average value as a reference of the normalization circuit of each diversity branch is provided, and the phase detection means further includes a limiter for limiting the amplitude of a signal for phase detection. A wireless reception device comprising means. 2. The inverse conversion circuit according to claim 1, wherein when the conversion function of the envelope detection circuit is a non-linear function, the output of the normalization circuit includes an inverse conversion circuit that processes an inverse conversion function corresponding to the nonlinear function. Wireless receiver. 3. The radio according to claim 2, wherein the inverse conversion circuit includes means for holding a plurality of kinds of inverse conversion functions, and means for adaptively selecting one of the plurality of kinds of inverse conversion functions. Receiver. 4. The radio receiving apparatus according to claim 1, wherein the output of the average arithmetic circuit for each diversity branch is given as a control signal to the synthesis demodulation processing circuit. 5. The radio receiver according to claim 1, wherein the envelope detection circuit includes a level adjustment circuit. 6. The radio receiver according to claim 1, further comprising a buffer circuit that temporarily holds an output of the envelope detection circuit. 7. The radio receiving apparatus according to claim 1, further comprising means for adjusting a relative delay of each output signal of the envelope detecting means and the phase detecting means input to the reproducing means. 8. An input terminal for receiving a received signal,
An envelope detecting means and a phase detecting means for receiving the signal of the input terminal and a reproducing means for reproducing a complex envelope signal from each output signal of the envelope detecting means and the phase detecting means are provided. The means includes an envelope detection circuit that detects an envelope signal from a signal at the input terminal, an average calculation circuit that calculates a level average value of the envelope signals detected by the detection circuit, and an envelope detection circuit of the envelope detection circuit. A normalization circuit for normalizing the output envelope signal by the average value of the output level of the averaging circuit, and the phase detection means includes limiter means for limiting the amplitude of the signal for phase detection. Wireless receiver.