JPH0697696B2 - Non-volatile semiconductor memory device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory device having an insulated gate field effect transistor structure capable of electrically writing and erasing.

[Technical background of the invention and its problems]

As a non-volatile semiconductor memory element of one element / memory cell for electrically writing, a hot carrier in which a floating gate and a control gate are laminated on a channel region between a source and drain regions of an insulated gate field effect transistor structure. The so-called SAMOS memory of injection type is well known. In this SAMOS memory device, for example, in the case of n-channel, writing is performed by applying a positive voltage to the drain and the control gate to cause a channel current to flow and injecting electrons of the hot carriers generated near the drain region into the floating gate. Done. However, the conventional SAMOS memory could not electrically erase the written information.

2. Description of the Related Art As a non-volatile semiconductor memory element that is electrically written and electrically erased, there is one that uses an extremely thin gate insulating film and utilizes a tunneling phenomenon of electrons in the gate insulating film. However, in a nonvolatile semiconductor memory device utilizing such tunneling phenomenon, it is necessary to apply an extremely high voltage to the control gate at the time of writing and erasing. Therefore, there is a problem that a booster circuit must be provided inside the chip in order to configure the memory integrated circuit. Further, since a high voltage is applied to the gate insulating film, there is a problem in reliability such as deterioration of the gate insulating film.

[Object of the Invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of electrically writing and erasing without using a high voltage.

[Outline of Invention]

The present invention is based on an n-channel SAMOS memory device, and the first gate insulating film thickness under the floating gate is set to 100 Å or less. According to the experiments by the present inventors, when an n-channel SAMOS memory device using such a thin gate insulating film is applied with a channel current in a pentode operating region under a condition where the gate voltage is lower than the drain voltage, the channel region From this, it was confirmed that holes were injected into the floating gate. This is because an electric field that accelerates holes generated near the drain to the floating gate side acts between the drain region and the floating gate while the gate voltage is low. The experimental data is shown in FIG. This is not a SAMOS structure but a normal n-channel MOS structure, the gate oxide film thickness is changed, and the drain voltage is 6V and the gate voltage is 1.
The data is obtained by measuring the peak value of the hole current under the condition of 5 to 2.5 V. It can be seen that the hole current flowing in the gate is remarkably increased when the gate oxide film thickness is 100 Å or less. On the other hand, a SAMOS memory device using such a thin gate insulating film is
When the channel current is passed under the condition that the gate voltage is about the same as or slightly higher than the drain voltage, electrons are injected from the channel region into the floating gate, similar to the writing in the conventional SAMOS memory device. Therefore, holes or electrons can be selectively injected from the channel region to the floating gate by selecting the operating conditions. The experimental data is shown in FIG. The above is characteristically recognized in the case of the n channel.

The present invention is based on the above findings, the first gate insulating film is 100 Å
As an n-channel SAMOS memory element structure described below, writing is performed by applying a positive drain voltage and at the same time applying a positive writing voltage to the control gate to cause electrons in the hot carriers generated near the drain region to float in the floating gate. Erasing is performed by applying a positive drain voltage to the control gate, and at the same time, applying an erase voltage lower than the write voltage and higher than the threshold voltage of the element in the written state to the control gate in the vicinity of the drain region. It is characterized in that holes are injected into the floating gate of the generated hot carriers.

〔The invention's effect〕

According to the present invention, it is possible to obtain a non-volatile semiconductor memory device that can be electrically written and erased without using a high voltage. Therefore, according to the present invention, it is not necessary to provide a booster circuit in a chip when configuring a memory integrated circuit, and a high-reliability memory is realized because a high voltage is not used.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows a SAMOS memory device structure of one embodiment. Reference numeral 1 denotes a p-type Si substrate, on the surface of which an n ⁺ -type source region 2 and a drain region 3 are formed which are separated from each other. A floating gate 5 of a first-layer polycrystalline silicon film is formed on the substrate between the source and drain regions 2 and 3 as a first gate insulating film through a thermal oxide film 4 of about 100 Å or less. A control gate 7 made of a second-layer polycrystalline silicon film is further formed on the film 5 as a second gate insulating film with a thermal oxide film 6 of, for example, about 200Å interposed therebetween. The gate length is 1 μm and the gate width is 4 μm.

The operation of the memory device thus configured will be described below with reference to FIG.

FIG. 2A shows a state of carriers in the channel region at the time of writing information. For writing, for example, the drain voltage V _D = 6V, and the control gate 7 has a writing voltage V _GW = _7V.
Apply V. As a result, electrons of hot carriers generated near the drain of the channel region are injected into the floating gate 5 as in the conventional SAMOS memory device.

As a result, the threshold voltage of the device changes from about 0.2 V in the initial state to about 1.5 V as seen from the floating gate. This is the writing state.

FIG. 2B shows the movement of carriers in the channel region when erasing information. For erasing, drain voltage V _D = 6V,
Erase voltage V lower than write voltage is applied to control gate 7.
Perform by applying _GE . For example, when the area of the control gate 7 is about twice as large as that of the floating gate 5, the threshold value of the written state is
If it is set to 1.5V, V _GE = 3.4V is set so that a voltage of 1.7V, which is slightly higher than this, is applied to the floating gate 6. As a result, a channel current flows by pentode operation, holes among hot carriers generated near the drain are selectively injected into the floating gate 5, and information is erased by recombination with electrons in the floating gate 5. Done.

The information is read by setting the drain voltage V _D = 6V, applying the read voltage V _GR to the control gate 7, and detecting the presence or absence of the channel current. This read voltage
V _GR is a programming voltage V _GW and an erasing voltage V _GW so that a channel current does not flow in a device in which programming is performed and a channel current flows in a device in which programming is not performed, but neither electron injection nor hole injection occurs. Select the middle value of _GE . The intermediate value satisfying such a condition is slightly higher than 4V in the data of FIG. 4, for example.

As described above, according to the present embodiment, it is possible to obtain a nonvolatile semiconductor memory device that can be electrically erased as well as electrically written without using a high voltage. Therefore, when configuring a memory integrated circuit, it is not necessary to provide a booster circuit in the chip, and since high voltage is not used, reliability can be improved.

The present invention is not limited to the above-mentioned embodiment,
Various modifications can be implemented without departing from the spirit of the invention.

[Brief description of drawings]

FIG. 1 is a diagram showing the structure of a SAMOS memory device according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are schematic diagrams showing the movement of carriers in a channel during writing and erasing in this memory device. FIG. 3 is an experimental data showing the gate oxide film thickness dependence of the gate hole current in a MOS transistor, and FIG. 4 is an experimental data for explaining the principle of writing and erasing in the memory device of the present invention. Is. 1 ... p-type Si substrate, 2 ... n ⁺ type source region, 3 ... n ⁺ type drain region. 4 ... Thermal oxide film (first gate insulating film), 5 ... Floating gate, 6 ... Thermal oxide film (second gate insulating film), 7 ... Control gate.

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/792

Claims (1)

[Claims] 1. A p-type semiconductor layer of a substrate is formed with n-type source and drain regions separated from each other, and a floating gate is formed on the p-type semiconductor layer between the source and drain regions via a first gate insulating film. In the nonvolatile semiconductor memory device in which the control gate is formed on the floating gate via the second gate insulating film, when the thickness of the first gate insulating film is 100 Å or less and a positive drain voltage is applied At the same time, a positive write voltage is applied to the control gate to inject electrons of the hot carriers generated in the vicinity of the drain region into the floating gate to perform writing, and at the same time a positive drain voltage is applied. ,
A positive erasing voltage that is lower than the writing voltage and higher than the threshold voltage of the element in the written state is applied to the control gate, so that holes among the hot carriers generated near the drain region are converted into the floating gate. A non-volatile semiconductor memory device characterized in that erasing is performed by injecting into a semiconductor.