JPH0697437B2 - Bus switching method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access method for a local memory and an external memory of a firmware system, and more particularly to a bus used when a bus master that outputs addresses having different widths accesses both memories. Regarding switching method.

(Prior Art) Conventionally, a firmware system for accessing a local memory and an external common memory has widely adopted a method of dividing a memory space of a bus mask by a fixed address value of the local memory and the external common memory.

In this method, for address expansion of the bus master, it is common to prepare a register for address expansion corresponding to the bus master and match it with the address width of the system, but when the address width is small, a fixed value is output. It may be done.

In addition, a port for controlling access to external memory is prepared and a common memory at an arbitrary address is accessed by I / O access to access like a sequential file. The accessible logical space is divided into a local memory and an external memory by a certain address value, and when accessing the divided memory space for external memory access, a bank value can be set so that the address information is weighted and output. There is a method of designating an external memory space by adding a circuit to the interface with the system bus.

(Problems to be Solved by the Invention) However, in the conventional bus switching method, when the local memory and the external memory are divided by a fixed address value, the address space allocated to the internal memory when the external memory address is specified. The external memory with cannot exist (even if it exists, it cannot be accessed from the bus master inside the firmware because it is the space allocated to the local memory), and there is a waste of the external memory address space. Further, even if a register for address expansion is added to a bus master having a small address width, it is not possible to remove a useless portion of the external memory as long as the local memory and the external memory are divided by a fixed address value.

When external memory access is realized by controlling I / O prepared in firmware, I / O cannot be controlled. When a bus master is in firmware, the bus master cannot directly access external memory. .

Further, in advance, the local memory and the external memory are divided by a certain address value, and a circuit for setting a bank value that can add weight to the address information of the external memory when accessing the external memory space is added. When the external memory space is accessed by using the external memory, no unnecessary memory space is created in the external memory. However, when there is a bus master that outputs an address value smaller than the address value that divides the local memory and the external memory, there is a disadvantage that either the local memory or the external memory can be accessed.

An object of the present invention is to provide a bus switching system which solves the above-mentioned drawbacks.

(Means for Solving the Problems) In order to achieve the above object, the bus switching method according to the present invention is composed of a plurality of bus masters that output addresses having different widths, and firmware that has a local memory therein is provided. In the firmware system configured to access the external memory connected to the system bus via the local memory and the bus switching unit,
When a bus master which outputs an address not having the longest width among the bus masters in firmware, outputs address information, a predetermined value is added to the address bit lacking portion on the upper side of the address bus. Address comparing means for comparing the address information from the bus master with predetermined data, an address modification register storing an address information upper bit for arbitrarily setting the address of the external memory, and an upper bit of the address information. An upper address selection circuit for selecting either the contents of the address modification register or the upper bit of the address information from the bus master as a unit, and the address upper bit storage unit is connected to the output of the upper address selection circuit, and the address lower bit storage unit. Connects to the address bus from the bus master External memory bus buffer and a local memory bus buffer connected to the address bus from the bus master, and as a result of the comparison by the address comparing means, the bit pattern 1 or 2 with the bit on the upper side of the address designated. If not, the upper address selection circuit selects the address bus from the bus master, stores the address information on the address bus in the external memory bus buffer, accesses the external memory, and sets the upper bit of the address. Is a designated bit pattern 1, the upper address selection circuit selects the contents of the address modification register, and the external memory bus buffer stores address information obtained by adding a weight value to the address information on the address bus. Then, the external memory is accessed and the upper bit of the address is the specified bit When the over down 2 stores the address information on the address bus from the bus master to the local memory bus punishment Hua, is arranged to access the local memory.

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a bus switching system according to the present invention, and FIG. 2 is a diagram showing details of the bus switching circuit 4 of FIG.

The bus master 1 that outputs a 20-bit address outputs a 20-bit address from bits 0 to 19 to the 24-bit wide address bus 6, but the missing 4 bits are boosted up, and bits 20 to 23 are output. Is output as 1.

At this time, the comparison circuits 11 and 12 in the bus switching circuit compare the values from bits 19 to 23 of the address bus 6 with the comparison data 13 and 1.
Compare 4 respectively.

In this example, the comparator circuit 12 activates the external selection signal 15 at times other than "1111X" to store the address information on the address bus 6 in the external memory bus buffer 18 and direct it to the external memory address bus 7. Further, the comparison circuit 11 is “1111
When it is "1", the external selection signal 15 is activated and the address information on the address bus 6 is stored in the external memory bus buffer 8 and is directed to the external memory address bus 7. In this case, the address information of 24 bits is stored. Of the upper 5 bits, the upper address selection circuit is instructed to use the data of the address modification register 16. That is, for the upper 5 bits, the upper address selection circuit 17 selects the contents of the address modification register 16, External memory bus buffer
Store in the upper 5 bits of 18.

In this example, when the values of the bits 19 to 23 of the address bit 6 are "11111", the pattern 1 is used.

In the case of the bus master 2 capable of outputting 24-bit address information, the address data bits 23 to
If the 4 bits of 20 are not "1111", they are switched to the external bus 7 by the comparison circuit 12, and as the address information, the value output by the bus master 2 is passed to the external memory 5 with 24 bits.

For both the 20-bit output bus master 1 and the 24-bit output bus master 2, address information bits 23 to 19 are “11”.
In the case of 110 "(Pattern 2), the local memory bus buffer 19 becomes active and the local memory 3 is accessed because the comparators 11 and 12 do not switch the bus to the outside.

The contents of the address modification register 16 are written by the determined bus master. By this address modification, the address of the external memory 5 when accessing the external bus 7 can be arbitrarily set.

(Effect of the Invention) As described above, according to the present invention, when the non-longest bus master of the bus mounter in the firmware outputs the address information, the predetermined value is added to the address bit of the missing portion on the upper side. If the upper bit of the address bus is not the specified bit pattern 1 or 2, the external memory is addressed by the system bus (address information on the address bus from the bus master), and in the case of the specified bit pattern 1 separately. The external memory is accessed by an address to which a weight whose value can be set is added, and in the case of the designated bit pattern 2, the bus switching circuit is switched so as to access the local memory. Therefore, it is possible to freely access the local memory and the external memory even by bus masters having different address bus widths, without creating a wasteful address space in the external memory space. Also, since the bus master that can output the entire bit width of the external bus memory area can output the external memory address independently of the modified external address, there are few restrictions on the memory area that can be accessed by each bus master. Has the advantage that

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a bus switching system according to the present invention. FIG. 2 is a detailed diagram of the bus switching circuit of FIG. 1 ... Bus master (address 20 bit output) 2 ... Bus master (address 24 bit output) 3 ... Local memory, 4 ... Bus switching circuit 5 ... External memory, 6 ... Address bus 7 ... External memory Address bus 8 ... Local memory address bus 11 ... Address comparison circuit 1 12 ... Address comparison circuit 2 13 ... Address comparison data 1 14 ... Address comparison data 2 15 ... External selection signal 16 ... Address modification register 17 ... Upper address selection circuit 18 …… External memory bus buffer 19 …… Local memory bus buffer 20 …… Address comparison means

Claims (1)

[Claims] 1. An external memory comprising a plurality of bus masters each of which outputs an address having a different width and having a local memory therein, the external memory being connected to the system bus via the local memory and a bus switching unit. In the firmware system configured to access the address, when the bus master that outputs a non-longest width address among the bus masters inside the firmware outputs the address information, a predetermined value is set in the address bit lacking portion on the upper side of the address bus. In addition, the bus switching circuit stores address comparison means for comparing address information from the plurality of bus masters with predetermined data, and an address information upper bit for arbitrarily setting the address of the external memory. Address modification register and address information A high-order address selection circuit that selects one of the high-order bits of the address information from the bus master as the contents of the address modification register as a high-order bit section, and an address high-order bit storage part is connected to the high-order address selection circuit output, and the low-order address The storage portion includes an external memory bus buffer connected to the address bus from the bus master and a local memory bus buffer connected to the address bus from the bus master. If the bit is not the designated bit pattern 1 or 2, the upper address selection circuit selects the address bus from the bus master and stores the address information on the address bus in the external memory bus buffer, Access the memory and set the upper bit of the address In the case of the designated bit pattern 1, the upper address selection circuit selects the contents of the address modification register and stores the address information obtained by adding the weight value to the address information on the address bus in the external memory bus buffer. When the external memory is accessed and the bit on the upper address side is the specified bit pattern 2, the address information on the address bus from the bus master is stored in the local memory bus buffer and the local memory is accessed. Bus switching method characterized by being configured.