JPH0695562B2 - Multi-chip type semiconductor device and manufacturing method thereof - Google Patents
Multi-chip type semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0695562B2 JPH0695562B2 JP1039936A JP3993689A JPH0695562B2 JP H0695562 B2 JPH0695562 B2 JP H0695562B2 JP 1039936 A JP1039936 A JP 1039936A JP 3993689 A JP3993689 A JP 3993689A JP H0695562 B2 JPH0695562 B2 JP H0695562B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- chips
- semiconductor
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
- H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は、最も効率的な半導体チップの配列が可能なマ
ルチチップ型半導体装置とその製造方法に関する。The present invention relates to a multi-chip type semiconductor device capable of arranging semiconductor chips most efficiently and a manufacturing method thereof.
（ロ）従来の技術 以下に高出力型の半導体装置をパワーMOSFETを例にとり
説明する。(B) Conventional Technology A high-power semiconductor device will be described below taking a power MOSFET as an example.
第７図はSIP型リードフレームに載置した半導体装置を
示し、（１）はリードフレー（２）のタブ部、（３）は
外部接続用のリード、（４）はパワーMOSFETの素子形成
が終了したチップ、（５）はチップ（４）表面の電極パ
ッド、（６）はパッド（５）とリード（３）とを結ぶワ
イヤである。FIG. 7 shows a semiconductor device mounted on a SIP type lead frame. (1) is a tab portion of the lead frame ( 2 ), (3) is a lead for external connection, and (4) is a device formation of a power MOSFET. The completed chip, (5) is an electrode pad on the surface of the chip (4), and (6) is a wire connecting the pad (5) and the lead (3).
パワーMOSFET等のパワー系素子は、単位トランジスタを
電極で並列接続することにより所望の電流容量を実現す
るが、近年増々高耐圧化・高出力化が求められ、従って
前記単位トランジスタの数とチップサイズは増々増大傾
向にある。しかしながら、チップサイズを増大すること
はウェハー１枚当りの理論収率を低下させ、例えばチッ
プサイズを単純に1.5倍にすると歩留りは半分に落ちる
という様な現象が生じる。一方、チップサイズを変えず
に単位トランジスタの大きさを収縮することは、プロセ
ス技術的にみても大きな困難と労力を要し、前記単純に
チップサイズを増大させる手法よりも更に大きな歩留り
の低下を伴う。Power type devices such as power MOSFETs achieve desired current capacity by connecting unit transistors in parallel with electrodes, but in recent years, higher withstand voltage and higher output have been demanded. Therefore, the number of unit transistors and chip size are increased. Is increasing more and more. However, increasing the chip size lowers the theoretical yield per wafer, and for example, if the chip size is simply increased by 1.5 times, the yield will drop to half. On the other hand, shrinking the size of the unit transistor without changing the chip size requires a great deal of difficulty and labor from the viewpoint of process technology, and causes a larger yield loss than the method of simply increasing the chip size. Accompany.
そこで近年、ある基本サイズのチップ（４）を先行設計
し、これを複数個並列接続することにより前記高出力化
に対応する試みが本願発明者により成されている。（例
えば、特開昭62−2587） （ハ）発明が解決しようとする課題 しかしながら、従来のチップ（４）は単位トランジスタ
の平衡動作といった観点から縦と横の長さが1:1又はそ
の近傍の割合で作られることが多く、この様なチップ
（４）を並設するには、例えば２個の場合は第８図に示
す如く縦と横の長さが1:2のエリアを要し、４個の場合
は再び1:1（2:2）のエリアを要するといった具合に、そ
れを載置する為のチップエリア（７）の形状はチップ
（４）の数によって大きく異ってくる。Therefore, in recent years, the inventors of the present application have made an attempt to design a chip (4) of a certain basic size in advance and connect a plurality of the chips in parallel to cope with the high output. (For example, Japanese Patent Laid-Open No. 62-2587) (C) Problems to be Solved by the Invention However, the conventional chip (4) has a vertical and horizontal length of 1: 1 or in the vicinity thereof from the viewpoint of balanced operation of unit transistors. In many cases, such chips (4) are arranged side by side in the case of two chips, for example, as shown in FIG. The shape of the chip area (7) for mounting it greatly depends on the number of chips (4), such as when 4 pieces require 1: 1 (2: 2) area again. .
一方、チップ（４）を載置するリードフレーム（２）は
その用途に応じて規格化され、タブ部（１）のエリア
（８）の大きさが異る複数種類のリードフレーム（２）
が用意されている。この様なリードフレーム（２）に対
して、前記複数個のチップ（４）を搭載する為には、容
量に対して極端に大きなリードフレーム（２）を用いる
か、又はリードフレーム（２）自体を専用設計するとい
った具合に、リードフレーム（２）の最適な選択ができ
ない、又は１チップ搭載用のものと共用できない欠点が
あった。On the other hand, the chip (4) the placing leadframe (2) is normalized depending on the application, the tab portion (1) has multiple types size of the area (8) of the lead frame (2)
Is prepared. Against such a lead frame (2), wherein in order to mount a plurality of chips (4) are extremely or using a large lead frame (2) relative to the volume, or a lead frame (2) itself However, there is a drawback in that the lead frame ( 2 ) cannot be optimally selected or cannot be shared with the one for mounting one chip.
（ニ）課題を解決するための手段 本発明は上記従来の課題に鑑み成されたもので、チップ
（11）１個の縦と長さの比が、チップ（11）１個の形状
とチップ（11）を複数個並設する為に要するエリアの形
状とが相似形となるような比に選択し、該チップ（11）
を並列接続して１パッケージ化することにより、タブ面
積の効率的利用を可能ならしめた半導体装置を提供する
ものである。(D) Means for Solving the Problems The present invention has been made in view of the above-described conventional problems, and the ratio of the length to the length of one chip (11) is the shape of one chip (11) and the chip. The chip (11) is selected in such a ratio that the shape of the area required for arranging a plurality of (11) in parallel becomes a similar shape.
The present invention provides a semiconductor device in which the tab area can be efficiently used by connecting in parallel with each other to form one package.
（ホ）作 用 本発明によれば、チップ（11）１個の形状とチップ（1
1）複数個を載置する為のエリアの形状が相似形を成す
ので、多チップ（11）搭載時も事実上１チップと同様に
扱うことができ、従って規格化されたリードフレーム
（13）を共用することができる。また、タブ部（14）の
面積を効率利用できる。(E) Operation According to the present invention, the shape of one chip (11) and the chip (1
1) Since the shape of the area for mounting a plurality of chips is similar, it can be handled as if it were a single chip even when mounting multiple chips (11), and therefore standardized lead frame ( 13 ) Can be shared. Further, the area of the tab portion (14) can be efficiently used.
（ヘ）実施例 以下に本発明の一実施例を図面を参照しながら詳細に説
明する。(F) Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.
第１図は本発明の半導体装置を示す平面図で、（11）は
表面にパワーMOFET等の素子形成とアルミニウム材料に
よる電極パッド（12a）（12b）の形成が終了した半導体
チップ、（13）はチップ（11）を搭載する為のタブ部
（14）と外部接続用のリード（15）とを有するリードフ
レーム、（16）は電極パッド（12a）（12b）とリード
（15）とを電気接続する金（Au）等から成るワイヤで、
半導体装置はこの状態からチップ（11）を含む主要部を
樹脂モールドすることにより製造される。FIG. 1 is a plan view showing a semiconductor device of the present invention. (11) is a semiconductor chip on which elements such as power MOFETs and electrode pads (12a) (12b) made of an aluminum material have been formed on the surface, ( 13 ). Is a lead frame having a tab portion (14) for mounting the chip (11) and leads (15) for external connection, and (16) electrically connects the electrode pads (12a) (12b) and leads (15). A wire made of gold (Au) etc. to connect,
From this state, the semiconductor device is manufactured by resin-molding the main part including the chip (11).
リードフレーム（13）は搭載するチップ（11）の電流容
量等に鑑み且つ多品種のチップ（11）を搭載できるよう
にその大きさが規格化されたものであり、種々な大きさ
のリードフレーム（13）が従来より準備されている。一
方、前述した様に多品種ある半導体チップの大多数はウ
ェハー面積の効率的利用と単位トランジスタの平衡動作
等の要因により正方形又はそれに近い長方形で形成され
る。従って、リードフレーム（13）のタブ部（14）は前
記多品種の半導体チップに対応できるようにやや横長の
形状で規格化されている。The lead frame ( 13 ) is standardized in size so that various types of chips (11) can be mounted in consideration of the current capacity of the mounted chip (11) and the like. ( 13 ) has been prepared from the past. On the other hand, as described above, the majority of various types of semiconductor chips are formed in a square shape or a rectangular shape close to the square shape due to factors such as efficient use of the wafer area and balanced operation of unit transistors. Therefore, the tab portion (14) of the lead frame ( 13 ) is standardized in a slightly laterally long shape so as to be compatible with the various types of semiconductor chips.
上記リードフレーム（13）のタブ部（14）に対して、本
願のチップ（11）は縦と横の長さが大体 の比をとるようなサイズに設定してある。この様な比で
あれば、チップ（11）を単体で搭載する時も横の長さが
縦の長さの約1.4倍で済むので、似たような電流容量を
持つ他品種の正方形に近い半導体チップと十分にリード
フレーム（13）を共用でき、１サイズ上のリードフレー
ム（13）を使用する必要が無く且つタブ部（14）の面積
を効率利用できる。With respect to the tab portion (14) of the lead frame ( 13 ), the chip (11) of the present application has a vertical and horizontal length of about The size is set to take the ratio of. With such a ratio, the horizontal length is about 1.4 times the vertical length even when the chip (11) is mounted alone, so it is similar to other types of squares with similar current capacity. The lead frame ( 13 ) can be sufficiently shared with the semiconductor chip, it is not necessary to use the lead frame ( 13 ) of one size, and the area of the tab portion (14) can be efficiently used.
更に、上記本願のチップ（11）を２個搭載する時も、第
１図に示す如く長辺を互いに隣接する様に並設すること
により、チップ（11）２個分を搭載するのに要する領域
（エリア）の縦と横の比は√2:2＝1:√２となり、単体
実装時と比が変らない。即ち、パターンの設計変更をせ
ずに単純に２倍の電流容量を持つ半導体装置を構成でき
る。しかも、縦と横の長さの比がやはり大体1:√２であ
るので、規格化された多数のリードフレーム（13）の中
から最適寸法のタブ部（14）を持つリードフレーム（1
3）を選択することができ、専用設計する必要が無い。
このことは、やはり似たような電流容量を持つ他品種の
正方形に近い半導体チップとリードフレーム（13）を共
用できることを示し、１サイズ大きいリードフレーム
（13）を使用する必要が無くタブ部（14）の面積を効率
利用できることを示す。Further, even when two chips (11) of the present application are mounted, it is necessary to mount two chips (11) by arranging the long sides side by side as shown in FIG. The vertical and horizontal ratio of the area is √2: 2 = 1: √2, which is the same as when mounted as a single unit. That is, a semiconductor device having a double current capacity can be simply configured without changing the design of the pattern. Moreover, since the ratio of the vertical length to the horizontal length is approximately 1: √2, the lead frame ( 1 ) having the tab (14) with the optimum size is selected from the standardized lead frames ( 13 ).
3 ) can be selected, and there is no need to design exclusively.
This means that the lead frame ( 13 ) can be shared with other types of semiconductor chips close to a square, which have similar current capacity, and it is not necessary to use the lead frame ( 13 ) one size larger, and the tab portion ( It shows that the area of 14) can be used efficiently.
第２図は第１図と同じサイズのチップ（11）を４個搭載
した例を示し、長辺と長辺とが、短辺と短辺とが夫々隣
接するように上下左右に並べた例を示す。この例でも、
チップ（11）４個を並べるのに要する領域の縦と横の長
さは、 となり、チップ（11）単体と相似形を成す。従って、こ
の例でも規格化されたリードフレーム（13）群の中から
無駄の無い最適寸法のタブ部（14）を持つリードフ レ
ーム（13）を選択できる。FIG. 2 shows an example in which four chips (11) of the same size as those in FIG. 1 are mounted, and the long side and the long side are arranged vertically and horizontally so that the short side and the short side are adjacent to each other. Indicates. Also in this example,
The vertical and horizontal lengths of the area required to arrange four chips (11) are And is similar to the chip (11) itself. Therefore, also in this example, it is possible to select the lead frame ( 13 ) having the tab portion (14) of the optimum size without waste from the standardized lead frame ( 13 ) group.
第３図は第１図のものに対して半分の大きさを有するチ
ップ（11）を２個並べた例、第４図は第３図のものと同
じ大きさのチップ（11）を第１図のリードフレーム（1
3）と同じ規格のリードフレーム（13）に４個並べた
例、第５図は第２図と同じ規格のリードフレーム（13）
に、第２図のものに対して倍の大きさを持つチップ（1
1）を２個並べた例である。第５図に示す大きさのチッ
プ（11）は、第１図に示すリードフレーム（13）のタブ
部（14）にも単体で、且つ面積の無駄が無く搭載でき
る。FIG. 3 shows an example in which two chips (11) each having a size half that of FIG. 1 are arranged, and FIG. 4 shows a chip (11) of the same size as that of FIG. Illustrated leadframe (1
An example in which four pieces are arranged on a lead frame ( 13 ) of the same standard as 3), and Fig. 5 shows a lead frame ( 13 ) of the same standard as Fig. 2.
In addition, a chip (1
This is an example in which two 1) are arranged. The chip (11) having the size shown in FIG. 5 can be mounted alone on the tab portion (14) of the lead frame ( 13 ) shown in FIG. 1 without waste of area.
第６図は第２図のリードフレーム（13）と同じ規格のリ
ードフレーム（13）に対し、第３図のチップ（11）と同
じサイズのチップ（11）を６個並べた例である。この例
では、縦と横の長さの比が 程度となり、正方形の半導体ペレットを６個並べる（2:
3）よりはタブ部（14）面積を有効利用できる。FIG. 6 shows an example in which six chips (11) of the same size as the chip (11) of FIG. 3 are arranged on the lead frame ( 13 ) of the same standard as the lead frame ( 13 ) of FIG. In this example, the ratio of length to width is 6 square semiconductor pellets are arranged (2:
The area of the tab portion (14) can be effectively used rather than 3).
この様にしてタブ部（14）上に多数個のチップ（11）を
搭載した後、ゲート用の電極パッド（12a）とソース用
の電極パッド（12b）を夫々図面に示した通りの形状に
ワイヤ（16）でステッチボンドし、夫々の対応するリー
ド（15）にワイヤボンドする。After mounting a large number of chips (11) on the tab portion (14) in this way, the gate electrode pad (12a) and the source electrode pad (12b) are respectively formed into the shapes shown in the drawing. Stitch bond with wires (16) and wire bond to their respective leads (15).
上記本願発明の構成によれば、基本サイズのチップ（1
1）を単純に並列接続することにより、倍の電流容量を
持つ半導体装置を単純に製造できる。その時に、チップ
（11）単数個を載置するのに要する領域と、チップ（1
1）複数個を載置するのに要する領域とが相似形を成す
ので、複数個搭載時も、特異な形状とならず実質的に１
個の大きなチップとみなすことができ、その形状が大き
く変化しないので、規格化された複数のリードフレーム
（13）の中から最適な大きさのリードフレーム（13）を
選択できる。リードフレーム（13）の専用設計あるいは
チップ（11）形状の設計変更が全く不要になり、且つタ
ブ部（14）の面積を有効に活用できる。According to the above-described configuration of the present invention, the basic size chip (1
By simply connecting 1) in parallel, a semiconductor device having a double current capacity can be simply manufactured. At that time, the area required to mount a single chip (11) and the chip (1
1) Since the area required for mounting multiple pieces is similar, even when multiple pieces are mounted, there is no peculiar shape and practically 1
Since it can be regarded as one large chip and its shape does not change significantly, the lead frame ( 13 ) of the optimum size can be selected from the standardized lead frames ( 13 ). No special design of the lead frame ( 13 ) or design change of the chip (11) shape is required, and the area of the tab portion (14) can be effectively utilized.
（ト）発明の効果 以上に説明した如く本発明によれば複数個のチップ（1
1）を並設接続することで単純に整数倍の電流容量を持
つ半導体装置を、プロセス技術の複雑化及び歩留り低下
を伴うこと無く実現できる利点を有する。(G) Effect of the Invention As described above, according to the present invention, a plurality of chips (1
By connecting (1) in parallel, it is possible to simply realize a semiconductor device having an integral multiple current capacity without complicating the process technology and reducing the yield.
しかも、単数個時と複数個時とで相似形を成し、特異な
形状とはならないので、規格化された従来のリードフレ
ーム（13）群から最も適したリードフレーム（13）を選
択でき、タブ部（14）の面積を最大限有効に活用できる
と共に、リードフレーム（13）やチップ（11）の新規形
成が不要である利点を有する。Moreover, since the singular shape and the plural shape form similar shapes and do not form a peculiar shape, the most suitable lead frame ( 13 ) can be selected from the standardized conventional lead frame ( 13 ) group. This has the advantages that the area of the tab portion (14) can be utilized to the maximum extent and that new formation of the lead frame (13) and the chip (11) is unnecessary.
第１図乃至第６図は夫々本発明を説明する為の平面図、
第７図と第８図は従来例を説明する為の平面図である。1 to 6 are plan views for explaining the present invention,
7 and 8 are plan views for explaining a conventional example.
Claims (7)
並設し、且つ前記複数個の半導体チップの共通接続すべ
き複数の接続端子とリードとをワイヤで接続することに
より前記複数個の半導体チップを電気的に並列接続し、
全体を１パッケージ化したマルチチップ型半導体装置に
おいて、 前記半導体チップは短辺と長辺を持つ矩型形状を有する
と共に、前記複数個の半導体チップは前記半導体チップ
の矩型形状と相似形を成す矩形の領域を構成する様に並
設したことを特徴とするマルチチップ型半導体装置。1. A plurality of the same semiconductor chips are arranged side by side on a common die part, and a plurality of connection terminals of the plurality of semiconductor chips to be commonly connected are connected to a lead by a wire. Electrically connecting the chips in parallel,
In a multi-chip type semiconductor device in which the whole is packaged, the semiconductor chip has a rectangular shape having short sides and long sides, and the plurality of semiconductor chips have a similar shape to the rectangular shape of the semiconductor chip. A multi-chip type semiconductor device, which is arranged in parallel so as to form a rectangular region.
が 又はその近傍の比であることを特徴とする請求項第１項
に記載のマルチチップ型半導体装置。2. The ratio of the length of the short side to the length of the long side of the semiconductor chip is 2. The multi-chip semiconductor device according to claim 1, wherein the ratio is in the vicinity thereof.
数）個であることを特徴とする請求項第１項に記載のマ
ルチチップ型半導体装置。3. The multi-chip semiconductor device according to claim 1, wherein the number of the semiconductor chips is 2n (n is an integer).
且つ長辺と長辺とが隣接するように並設したことを特徴
とする請求項第３項に記載のマルチチップ型半導体装
置。4. The plurality of semiconductor chips is two,
4. The multi-chip type semiconductor device according to claim 3, wherein the long sides are arranged side by side so that the long sides are adjacent to each other.
と長辺とが、短辺と短辺とが夫々隣接するように上下左
右に並設したことを特徴とする請求項第３項に記載のマ
ルチチップ型半導体装置。5. The number of the semiconductor chips is four, and the long side and the long side are arranged side by side vertically and horizontally so that the short side and the short side are adjacent to each other. The multi-chip type semiconductor device according to the item.
並設し、且つ前記複数個の半導体チップの共通接続すべ
き複数の接続端子とリードとをワイヤで接続することに
より前記複数個の半導体チップを電気的に並列接続し、
全体を１パッケージ化するマルチチップ型半導体装置の
製造方法において、 前記半導体チップの短辺と長辺の長さの比を、前記複数
個の半導体チップを矩形の領域に納めた場合に、前記矩
形の領域の形状と前記半導体チップの形状とが互いに相
似となるような比に設定し、この比に従って前記半導体
チップのパターン設計を行うことを特徴とするマルチチ
ップ型半導体装置の製造方法。6. A plurality of the same semiconductor chips are arranged side by side on a common die portion, and a plurality of connection terminals to be commonly connected to the plurality of semiconductor chips are connected to a lead by a wire. Electrically connecting the chips in parallel,
In a method for manufacturing a multi-chip type semiconductor device in which the whole is packaged in one package, a ratio of a length of a short side of a semiconductor chip to a length of a long side of the semiconductor chip is set to a rectangle when the plurality of semiconductor chips are accommodated in a rectangular area. A method of manufacturing a multi-chip type semiconductor device, characterized in that the shape of the region and the shape of the semiconductor chip are set to be similar to each other, and the pattern of the semiconductor chip is designed according to this ratio.
れたことを特徴とする請求項第１項又は第６項に記載の
マルチチップ型半導体装置とその製造方法。7. The multi-chip type semiconductor device according to claim 1 or 6, and a method of manufacturing the same, wherein a vertical MOSFET is formed in the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1039936A JPH0695562B2 (en) | 1989-02-20 | 1989-02-20 | Multi-chip type semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1039936A JPH0695562B2 (en) | 1989-02-20 | 1989-02-20 | Multi-chip type semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02219257A JPH02219257A (en) | 1990-08-31 |
| JPH0695562B2 true JPH0695562B2 (en) | 1994-11-24 |
Family
ID=12566832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1039936A Expired - Fee Related JPH0695562B2 (en) | 1989-02-20 | 1989-02-20 | Multi-chip type semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0695562B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009141083A (en) * | 2007-12-05 | 2009-06-25 | Denso Corp | Semiconductor apparatus |
| JP2012191021A (en) * | 2011-03-11 | 2012-10-04 | Sanken Electric Co Ltd | Semiconductor module |
| JP2013197331A (en) * | 2012-03-21 | 2013-09-30 | Sumitomo Electric Ind Ltd | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6356950A (en) * | 1986-08-28 | 1988-03-11 | Fuji Electric Co Ltd | Composite integrated circuit device |
-
1989
- 1989-02-20 JP JP1039936A patent/JPH0695562B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02219257A (en) | 1990-08-31 |
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