JPH0563047B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, and particularly to the structure of a field effect transistor used in high frequency, high power applications.

[Conventional technology]

Conventionally, in this type of field effect transistor, the common source formation is common, and the multiple gate bonding pads of the field effect transistor chip are electrically connected to the input metallized portion of the transistor package using multiple gold wires, etc. connected,
Further, the plurality of drain bonding pads are similarly electrically connected to the output metallized portion by a plurality of gold wires, and the lengths of the plurality of gold wires are all formed to be equal.

[Problem that the invention seeks to solve]

In the conventional field effect transistor described above, in the case of high-frequency, high-power applications, multiple gate bonding pads or multiple drain bonding pads are connected to metallization on the input side within the transistor package by multiple thin metal wires. All are electrically connected to the output side metallized portion at equal lengths. However, in this case, the multiple thin metal wires have self-inductance and mutual inductance, and in a normal configuration in which multiple thin metal wires are arranged in parallel, the total inductance of the thin metal wires at both ends is greater than the total inductance of the thin metal wires at both ends. is smaller than that of the thin metal wire in the center, causing unbalance in inductance and making it impossible for input power or output power to be uniformly introduced into or led out from the field transistor chip, respectively.In high-frequency, high-output applications, power gain and power This caused a decrease in output.

In the case of the conventional field effect transistor mentioned above, the lengths of the thin metal wires that electrically connect the multiple drain bonding pads and gate bonding pads of the transistor chip are all the same, so they are connected at the center of the transistor chip. Since mutual inductance from both sides of the thin metal wire is added, the total inductance of the thin metal wire that connects the ends of the transistor chip becomes larger than the total inductance of the thin metal wire, resulting in non-uniform RF operation.In contrast, the present invention
By making the length of the thin metal wires shorter at the center of the transistor chip than at the ends, we can effectively equalize the total inductance of each thin metal wire, thereby achieving phase balance in RF operation. It has the original content of being able to measure high output and high gain.

[Means for solving problems]

In the field effect transistor of the present invention, the length of a plurality of thin metal wires that electrically connect a plurality of gate bonding pads and a transistor package, or the length of a plurality of thin metal wires that electrically connect a plurality of gate bonding pads and a transistor package; The length of the plurality of thin metal wires connected to the transistor chip is such that the length of the portion of the thin metal wire that connects the center of the transistor chip is shorter than that of the portion that connects the ends of the transistor chip. It has a structure in which the total inductance is effectively equal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a product plan view showing one embodiment of the present invention. Furthermore, FIG. 2 is a plan view of a conventional product. Field-effect transistors for high-frequency, high-output applications use a plurality of thin metal wires 4 to electrically connect the drain bonding pads 1 of a plurality of chips and the output-side metallized portion 3 of a package 2 in order to extract power output to the outside. It is connected to the. Furthermore, in order to supply power from the outside into the transistor chip 5, the gate bonding pads 6 of the plurality of chips and the input side metallized portion 7 of the package 2 are electrically connected using a plurality of thin metal wires 8 in the same manner as described above. It is connected.
In this case, among the plurality of thin metal wires 4 on the drain side arranged in parallel, the length of the thin metal wire that connects to the center of the transistor chip 5 connects the ends of the transistor chip 5. The thin metal wire 4 on each drain side is made shorter than the length of the thin metal wire.
The structure is such that the total inductance of the two elements is equalized and the RF power output can be uniformly extracted.

FIG. 3 is a plan view of Embodiment 2 of the present invention.
Embodiment 2 differs from Embodiment 1 in that the length of the thin metal wire that connects the center of the transistor chip is shorter than the length of the thin metal wire that connects the ends of the transistor chip, so that the overall inductance of each thin metal wire can be effectively reduced. By implementing a structure equal to , not only on the drain side but also on the gate side, we aim to make the phase of the RF operation more uniform.

〔Effect of the invention〕

As described above, the present invention provides a method for connecting the gate bonding pad of a transistor chip and the input metallized portion of the package, or the drain bonding pad of the transistor chip and the output metallized portion of the package to each other. By making the length of the thin metal wire that connects the center of the transistor chip thinner than the length of the thin metal wire that connects the ends of the transistor chip, the total inductance of each thin metal wire is made equal, thereby making the input power uniform. It is driven by the transistor chip, and the output power can be uniformly extracted from the transistor. Thereby, high output and high gain can be achieved in high frequency, high output applications.

[Brief explanation of the drawing]

1 is a plan view of a field effect transistor according to a first embodiment of the present invention, and FIG. 2 is a plan view of a field effect transistor having a conventional structure corresponding to FIG. Further, FIG. 3 is a plan view of a second embodiment of the present invention, which is an improved structure of the first embodiment. DESCRIPTION OF SYMBOLS 1...Drain bonding pad, 2...Transistor package, 3...Output side metallization part, 4...Drain side thin metal wire, 5...Transistor chip, 6...Gate bonding pad,
7...Input side metallized part, 8...Gate side thin metal wire.

Claims (1)

[Claims] 1. In a semiconductor device in which a plurality of electrodes on a transistor chip and a metallized portion provided in a semiconductor container are connected by a plurality of thin metal wires arranged in parallel,
A semiconductor device characterized in that a length of a metal thin wire existing in a central portion of the plurality of metal thin wires is shorter than a length of a metal thin wire existing at an end portion.