JPH0694801A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device, which can be tested certainly and with which clock supply is made simpl. CONSTITUTION:The input terminal D of a latch circuit 9 is connected with a parallel input terminal PI2 while the output terminal Q is connected with one of the input terminals of an XOR gate 7. A test clock TCK is fed to an enable end EN-bar. and the data of the input terminal D is taken in when 'L' is given to the enable end EN bar add also it is transmitted to the output terminal Q. When 'H' is given, on the other hand, the taken-in data is held and passed to the output, terminal Q. Even though the data given to the second input terminal becomes uncertain before the specified period goes out, it can be avoided within the period that the result from comparison becomes uncertain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a test auxiliary circuit for facilitating the test.

[0002]

2. Description of the Related Art FIG. 9 shows a data input / output scan register 3 which is connected in series to form a scan path.
It is a circuit diagram which shows the conventional structure of 2. Output terminal PO1,
Each of the input terminals PI2 is connected to a RAM (not shown), supplies data to the RAM, and reads data from the RAM.

In normal operation, the enable signal SCK1 is set to "L" and the enable signal PCK1 is set to "H". As a result, the data given to the input terminal PI1 is transmitted to the output terminal PO1 through the master latch 51, and R
Data is input to AM.

On the other hand, when the control signal TM is set to "L", the enable signal PCK2 also becomes "H". Therefore, by setting the enable signal SCK2 to "L", the output of the RAM read from the input terminal PI2. The data is transmitted to the output terminal PO2 via the slave latch 52. At this time, the test clock TCK may be set to either "H" or "L".

During the test operation, the enable signal PCK
1 and SCK2 are both set to "L" and input terminal P
The I1 and output terminal PO2 terminals are electrically separated from the RAM. The read data from the RAM is input to the first input terminal D1 of the slave latch 52 via the terminal PI2. On the other hand, at the output terminal Q of the master latch 51, the data obtained by inverting the expected value of the data PI2 from the RAM is set. Then, the true expected value further inverted by the inverter 61 and the data read from the RAM to the terminal PI2 are compared by the XOR circuit 71.

Since the control signal TM is set to "H" during the test operation, the enable signal PCK2 becomes "H" if they match as a result of the above comparison, and "L" if they do not match. become. As a result, from the RAM to the terminal P
The data read out to I2 passes through or is latched by the slave latch 52.

The result of this test is the enable signal SCK.
By applying a two-phase clock to SCK1 and SCK2, the scan path is sequentially shifted through the input terminal SI and the output terminal SO, and is read out to the outside.

The data stored in the RAM is sequentially read according to the address (ADRESS) sequentially updated by an address scan register (not shown). The address changes in accordance with shift clocks SCK1A and SCK2A that control the shift operation of the address scan register, and correspondingly read data (READ DATA) stored in the RAM is input terminal PI.
2 in sequence.

Since a pulse is given to the test clock TCK every time data is read, the data stored in the RAM is different from the expected value (fail data).
When is read, a pulse having the same phase as the pulse of the test clock TCK is generated in the enable signal PCK2. As a result, the fail data given to the parallel input terminal PI2 is given to the output terminal Q of the slave latch 52. To make the configuration simple, test clock TCK
Are also used by the shift clock SCK1A.

On the other hand, since expected value data (data opposite to the data given to the output terminal Q of the master latch 51) is set in advance at the output terminal Q of the slave latch 52, if fail data is read out, the node B is read. Data is inverted and can be detected at the parallel output terminal PO2.

FIG. 11 is a circuit diagram of another conventional data input / output scan register 42. When a scan path is constructed using this, the master latch 53 receives the output data of the RAM and the slave latch 54 inputs the data to the RAM.

In this case, the test result is the master latch 53.
Therefore, it is necessary to be careful when reading the test result by the shift operation. In order to read the test result nondestructively, it is necessary to add a clock to the enable signal SCK2, transfer the test result to the slave latch 54, and then perform the shift operation.

[0013]

In the conventional RAM test auxiliary circuit, there arises a problem due to using the clocks of the same phase for the shift clock SCK1A and the test clock TCK.

FIG. 10 is a timing chart for explaining the above problem. As shown in FIG. 10, when the update of the address (ADDRESS) is started at the rising edge of the shift clock SCK1A and the update of the address is completed, the RAM is updated.
The data (READDATA) output by is temporarily uncertain data, and then the stored data is output to the updated address.

That is, a certain delay occurs from the rising of the shift clock SCK1A to the time when the data stored corresponding to the new address is determined and read.

On the other hand, while the test clock TCK is "H", the expected value is compared with the read data of the RAM. Therefore, if the comparison of the data stored corresponding to the old address is not completed before the RAM outputs the uncertain data corresponding to the new address, that is, if the test clock TCK is not lowered, the test result Becomes uncertain and normal test cannot be performed.

Here, if a clock having the same phase as the shift clock SCK1A is used as the test clock TCK, the shift clock SCK1A falls between the start of the address update and the completion of the update, which is a very narrow clock. Must be However, it is difficult to transmit a clock having a narrow pulse width inside the semiconductor device.

Therefore, it is difficult to use a clock having the same phase as the shift clock SCK1A and the test clock TCK, and as a result, the shift clock SCK1A is used.
Since it is necessary to provide an independent clock to the test clock TCK, the clock supply becomes complicated.

The present invention has been made to solve the above problems, and the test result is uncertain even if a clock having a relatively wide pulse width and the same phase is used for the shift clock SCK1A and the test clock TCK. It is an object to provide a scan register that does not meet the requirement.

[0020]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit device having a scan path formed by connecting a plurality of scan registers in series.

In the first mode, the scan register is
A control terminal for receiving a control signal activated in a predetermined period, a first input terminal provided on the scan path,
Corresponding to the first input terminal and the second input terminal provided outside the scan path, and corresponding to the first output terminal and the second input terminal provided on the scan path, outside the scan path It has a second output terminal provided, an input end connected to the second input terminal, and an output end, and outputs data of the input end at the start of a predetermined period in a predetermined period based on the control signal. A first latch circuit that latches and outputs from the output terminal, and outputs the data of the input terminal as it is from the output terminal except for a predetermined period, and a first input connected to the output terminal of the first latch circuit. A second latch circuit having an end, a second input end operatively connected to the first input terminal, and an output end connected to the first and second output terminals;
It includes a comparison means for comparing the data at the output end of the first latch circuit and the data given to the second input end of the second latch circuit. Then, the second latch circuit latches the data at the start of the predetermined period at its first input end based on the comparison result of the comparison means and outputs it to its own output end.

In the second aspect, further, a scan register is connected to the third input terminal and the third output terminal, both of which are provided outside the scan path, and the third and first input terminals, respectively. A third latch circuit having first and second input terminals and an output terminal connected to the third output terminal; an input terminal connected to the output terminal of the third latch circuit;
A first inverter having an output end connected to the second input end of the second latch circuit, an input end connected to the output end of the second latch circuit, and an output end Two
And an inverter of. And the second output terminal is
It is connected to the first output terminal via the second inverter.

In the third aspect, the scan register is provided outside the scan path, a control terminal receiving a control signal activated in a predetermined period, a first input terminal provided on the scan path, and a scan terminal. A second input terminal corresponding to the first input terminal and provided on the scan path, a first output terminal provided on the scan path, and a second output terminal provided on the scan path and provided outside the scan path. It has an output terminal, an input terminal connected to the second input terminal, and an output terminal, and latches the data of the input terminal at the start of the predetermined period in the predetermined period based on the control signal and outputs the data from the output end. A first latch circuit that outputs and outputs the data of the input end as it is from the output end except for a predetermined period, a first input end connected to the output end of the first latch circuit, and a first input The second input connected to the terminal A second latch circuit having an end and an output end operatively connected to the first and second output terminals; data at the output end of the first latch circuit; Comparison means for comparing the data
including. Then, the second latch circuit latches the data at the start of the predetermined period at its first input end based on the comparison result of the comparing means and outputs it to its own output end.

In a fourth aspect thereof, a scan register is further provided at a third input terminal and a third output terminal both provided outside the scan path, an output end, and an output end of the second latch circuit. A first inverter having a connected input end; and a first input end connected to the third input terminal,
A third latch circuit having a second input terminal connected to the output terminal of the first inverter and an output terminal; an input terminal connected to the output terminal of the third latch circuit; And a second inverter having an output terminal connected to the output terminal. The second output terminal is connected to the input terminal of the first inverter.

[0025]

In the first and third aspects of the present invention, during the predetermined period when the comparison result of the comparison means is significant,
The output of the first latch circuit, which is one of the comparison targets, holds the data given to the second input terminal at the start of the predetermined period.

Further, in the second and fourth aspects of the present invention, a value opposite to the expected value is given to the output of the third latch circuit.

[0027]

【Example】

(1) First embodiment. 1 is a circuit diagram of a data input / output scan register 30 according to a first embodiment of the present invention. The configuration is such that the latch circuit 9 is added to the conventional data input / output scan register 32 shown in FIG. 9, but it is specifically configured as follows.

The data input / output scan register 30 is
Serial input terminal SI provided on the scan path,
And a serial output terminal SO. Further, it is provided with parallel input terminals PI1 and PI2 and parallel output terminals PO1 and PO2 provided outside the scan path.

The parallel input terminal PI1 is connected to the first input terminal D1 of the master latch 51, and the serial input terminal SI is connected to the second input terminal D2. Master latch 51
The enable signals PCK1 and SCK1 are applied to the first and second enable ends EN1 and EN2, respectively. A parallel output terminal PO1 is provided at the output terminal Q of the master latch 51.
Are connected.

The input terminal D of the latch circuit 9 is connected to the parallel input terminal PI2, and its output terminal Q (node C) is XO.
It is connected to one input terminal of the R gate 7. The test clock TCK is applied to the enable terminal EN bar.
The latch circuit 9 takes in the data of the input terminal D and transmits it to the output terminal Q when "L" is given to the enable terminal EN bar. When "H" is given, the fetched data is held and output to the output terminal Q.

The output terminal Q of the latch circuit 9 is connected to the first input terminal D1 of the slave latch 52 via the node C,
The second input terminal is connected to the other input terminal of the XOR gate 7 and the output terminal Q of the master latch 51 via the inverter 61. The output terminal Q of the slave latch 52 is connected to the parallel output terminal PO2 and the serial output terminal SO via the inverter 62. The enable signals PCK2 and SCK2 are applied to the first and second enable ends EN1 and EN2 of the slave latch 52, respectively.

The enable signal PCK2 is an output of the NAND gate 82, and the control signal TM is applied to one input terminal of the NAND gate 82. The output of the NAND gate 81 is applied to the other input terminal of the NAND gate 82, and the output of the XOR gate 7 and the test clock TCK are applied to the NAND gate 81.

In both the master latch 51 and the slave latch 52, when "H" is applied to the first enable end EN1, the data of the input terminal D1 is taken in and transmitted to the output terminal Q. Also, the second enable end EN2
When "H" is applied to, the data of the input terminal D2 is taken in and is transmitted to the output terminal Q. Then, when "L" is given to both the first enable end EN1 and the second enable end EN2, the fetched data is held and output to the output terminal Q. Note that the normal enable terminal EN1 and the enable terminal EN2 are not used at the same time to give "H".

A plurality of such data input / output scan registers 30 are connected in series to form a scan path (a kind of shift register), function as normal flip-flops during normal operation, and RA during test.
Contributes to the testing of M and logic circuits.

FIG. 2 is a block diagram showing how the data input / output scan register 30 is provided so as to contribute to the test of the RAM 1. Here, an address scan register 2 for giving an address of the RAM 1 when the RAM 1 is tested is also provided.

The scan registers 2 and 30 surround the RAM 1 and separate the RAM 1 from other logic circuits on the semiconductor integrated circuit device during the test operation and the shift operation. A plurality of address scan registers 2 are also connected in series to form a scan path.

During the shift operation, test data such as an address of RAM 1 to be provided to RAM 1 and an expected value are stored in scan registers 2 and 30 by the shift function of the scan path. Then, during the test operation, the read data corresponding to each address from the RAM 1 is compared with the expected value. The test result (comparison result) of the RAM 1 is stored in the data input / output scan register 30 and is output to the outside by the shift function of the scan path.

FIG. 3 is a circuit diagram showing an example of the configuration of the address scan register 2 in order to explain the shift function of the scan path. The address scan register 2 has a serial input terminal SI and a serial output terminal SO provided on the scan path. In addition, a parallel input terminal PI1 and a parallel output terminal PO1 provided outside the scan path are provided.

The parallel input terminal PI1 is connected to the first input terminal D1 of the latch circuit 5, and the serial input terminal SI is connected to the second input terminal D2. The enable signal PCK1 and the shift clock SCK1A are applied to the first and second enable ends EN1 and EN2 of the latch circuit 5, respectively. The parallel output terminal PO1 is connected to the output terminal Q (node A) of the latch circuit 5.

The latch circuit 5 performs the same operation as the master latch 51 based on the logic signals given to the first and second enable ends EN1 and EN2.

The input terminal D of the latch circuit 4 is an inverter 63.
Is connected to the node A of the latch circuit 5 via. The output terminal Q of the latch circuit 4 is connected to the serial output terminal SO via the inverter 64. The shift clock SCK2A is applied to the enable end EN of the latch circuit 4.

The latch circuit 4 takes in the data of the input terminal D and transmits it to the output terminal Q when "H" is applied to the enable terminal EN. Also, enable terminal E
When "L" is given to N, the fetched data is held and output to the output terminal Q.

In the normal operation of the address scan register 2, the shift clock SCK1A becomes "L",
The enable signal PCK1 is set to "H". As a result, the RAM 1 and the logic are connected via the latch circuit 5. That is, the address of RAM1 is transmitted from the parallel input terminal PI1 to the parallel output terminal PO1. At this time, the shift clock SCK2A may be set to either "H" or "L".

On the other hand, during the shift operation and the test operation, the enable signal PCK1 is set to "L" and the RAM1
And logic are separated. RA during shift operation
Input of data for the test of M1 and reading of the test result of the test of RAM1 are performed. These are performed by the shift operation in the scan path.

The shift operation will be described by taking the address scan register 2 as an example. FIG. 4 is a timing chart showing the shift operation in the scan path. The shift clocks SCK1A and SCK2A have a first phase and a second phase, respectively.
The phase clock signals are applied. The data at the serial input terminal SI of each address scan register 2 is taken into the node A by the shift clock SCK1A. The data at the node A is inverted by the inverter 63, receives the shift clock SCK2A, and is transferred to the node B (the output terminal Q of the latch circuit 4). Further inverter 6
4, the inverted data of the node B is set to the serial output terminal SO.

As described above, the two-phase shift clock SC
A 1-bit shift operation from the serial input terminal SI to the serial output terminal SO is performed by K1A and SCK2A. Since the data appearing at the serial output terminal SO of the address scan register 2 of a certain stage is given to the serial input terminal SI of the address scan register 2 of the next stage, the data is sequentially transferred in the scan path. .

Such a shift operation is similarly performed in the data input / output scan register 30. The output of the gate 81 becomes "H" by setting the test clock TCK to "L", and the output of the gate 82 becomes "L" by setting the control signal TM to "H". The enable end EN1 of is always "L". Data is sequentially transferred via the serial input terminal SI and the serial output terminal SO by applying the clocks in phase with the shift clocks SCK1A and SCK2A to the enable signals SCK1 and SCK2, respectively.

In this way, the shift operation is performed by the two-phase clock, and the test data is set and the test result is read.

Next, the case of testing the RAM 1 will be described. FIG. 5 shows the scan register 3 for data input / output.
FIG. 6 is a timing diagram when the RAM 1 is tested when 0 is used. The enable signal PCK1 is set to "L",
RAM1 and logic are separated.

A two-phase clock is applied to the shift clocks SCK1A and SCK2A to the address scan register 2 to update the address to be tested. However, unlike the case of the shift operation, the enable signals SCK1 and SCK are applied to the data input / output scan register 30.
No two-phase clock is applied to CK2, and both are set to "L". As a result, the data given to each data input / output scan register 30 by the shift operation is held.

In this way, the master latch 51 has RA
The inverted data of the expected read value from M1 is held. Then, the true expected value further inverted by the inverter 61 and the data held by the latch circuit 9 become the XOR circuit 7
Compared by.

In many cases, when testing RAM1,
All stored data corresponding to the address is preset to "L" (or "H"). Therefore, the expected read value of the RAM 1 is set to "L" and the master latch 51 holds "H". RAM1
If the data read from is "H", it becomes fail data.

By the rise of the shift clock SCK1A, the address updated from the parallel output terminal PO1 of the address scan register 2 is newly added to the RAM.
Given to 1. As described in the conventional technique, the data read from the RAM 1 is applied to the parallel input terminal PI2 of the data input / output scan register 30 with a delay thereafter.

Here, since the test clock TCK is also used as the shift clock SCK1A, the latch circuit 9 is brought into the holding state when the address update is started. When the test clock TCK is "L", the data of the parallel input terminal PI2 is taken in by the latch circuit 9 and transmitted to the node C. Therefore, what is held by the latch circuit 9 is the data (read data of the RAM1) of the parallel input terminal PI2 at the time when the test clock TCK changes from “L” to “H”.

Therefore, the parallel input terminal PI when the test clock TCK changes from "L" to "H"
The data of 2 is compared with the expected read value. That is, even if the data of the parallel input terminal PI2 is changed with a delay after that, the uncertain data is not held, and even if the pulse width of the shift clock SCK1A is wide, this is also used as the test clock TCK to perform a normal test. Can be done.

The output of the latch circuit 9 is the test clock TC.
K is held during the period of "H". On the other hand, during this period, the gate 81 is open (during comparison operation), and XOR
The output of the gate 7 is inverted and given to the gate 82. Further, when the output of the RAM1 is tested, the control signal TM is set to "H" so that the gate 82 operates as an inverter.

Therefore, the output of the XOR gate 7 is the slave latch 52 while the test clock TCK is "H".
Is applied to the first enable end EN1 of. In other words, when the fail data (the inverted data of the expected read value) is read, the enable signal SCK2 having a pulse in phase with TCK is generated.

Since the enable signal SCK2 is generated in this manner, R supplied to the parallel input terminal PI2 is
The read data of the AM1 is taken into the slave latch 52 when it is the fail data, and the read data of the node B
Appear in.

On the other hand, the slave latch 52 holds the expected value data (“L”, which is the opposite data to the data held in the master latch 51) in advance by the shift operation. Therefore, the fail data is parallel output terminal PO
At 2, the data is detected as being inverted from "L" to "H".

After the above test is completed for a plurality of addresses, the shift operation is performed again at the timing shown in FIG. 4 and the test result is read.

A pulse is generated in the test clock TCK for each of a plurality of updated addresses, but in many cases, as described, all the data stored in the RAM 1 is expected to be "L". If there is fail data, it is detected regardless of the number.

The parallel input terminal PO1 is connected to the node A.
Are connected, and data "H" is sequentially written at the tested addresses. As a result, RA
Following the test in which the expected value of M1 is "L", RA
It becomes easy to perform a test in which the expected value of M1 is "H".

(2) Second embodiment. FIG. 6 shows the second aspect of the present invention.
FIG. 6 is a circuit diagram of a data input / output scan register 40 according to the embodiment. The configuration is such that the latch circuit 9 is added to the conventional data input / output scan register 42 shown in FIG. The specific operation is similar to that of the first embodiment, and the same effect as that of the first embodiment can be obtained.

However, the data input / output scan register 4
When 0 is used, the test result is held in the master latch 53, so it is necessary to be careful in reading the test result by the shift operation. In order to read the test result nondestructively, first, a clock is added to the enable signal SCK2 to transfer the test result to the slave latch 54,
It is necessary to perform the shift operation at the timing shown in FIG.

(3) Third embodiment. In the first and second embodiments, the case where the present invention is applied to the data input / output scan registers 30 and 40 separately requiring the parallel output terminal PO2 has been described. In such a configuration, the test clock TCK is set to "L" during normal operation,
The latch circuit 9 is used in the enabled state. However, in some cases, a data input / output scan register having a configuration in which the parallel output terminal PO2 is directly connected to the parallel input terminal PI2 may be used. The present invention can be applied to this case as well.

FIG. 7 is a circuit diagram of the data input / output scan register 31 corresponding to the first embodiment in which the slave latch 52 holds the test result. Parallel output terminal P
O2 is not connected to node B, and parallel input terminal PI
Connected to 2. In such a configuration, the test clock TCK may be set to "H" even during normal operation.

FIG. 8 is a circuit diagram of the data input / output scan register 41 corresponding to the second embodiment in which the test result is held in the master latch 53. Parallel output terminal PO
2 is not connected to the node A, and the parallel input terminal PI2
It is connected to the. In such a configuration, like the data input / output scan register 31, the test clock TCK may be set to "H" during normal operation.

[0068]

As described above, according to the present invention, even if the data applied to the second input terminal is delayed by a certain delay time from the start of the predetermined period, it becomes uncertain. The data at the start of the predetermined period is held in the predetermined period. Therefore, even if the data given to the second input terminal becomes uncertain before the end of the predetermined period, it is possible to avoid that the comparison result becomes uncertain in the predetermined period.

Therefore, even if the pulse width of the shift clock for controlling the shift operation of the first latch circuit is longer than the delay time, the clock having the same phase as this can be used as the control signal and the clock can be supplied. It will be easy.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram of a scan path system for explaining the first embodiment of the present invention.

FIG. 3 is a circuit diagram of an address scan register for explaining the first embodiment of the present invention.

FIG. 4 is a timing chart at the time of a shift operation, which explains the first embodiment of the present invention.

FIG. 5 is a timing chart at the time of a test operation for explaining the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a third embodiment of the present invention.

FIG. 9 is a circuit diagram showing a conventional technique.

FIG. 10 is a timing diagram at the time of a test operation showing a conventional technique.

FIG. 11 is a circuit diagram showing a conventional technique.

[Explanation of symbols]

1 RAM 7 XOR circuit 9 Latch circuit 30, 31, 40, 41 Data input / output scan register 51, 53 Master latch 52, 54 Slave latch 61, 62 Inverter circuit

[Procedure amendment]

[Submission date] January 11, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 10

[Correction method] Change

[Correction content]

[Figure 10]

Claims (4)

[Claims] 1. A semiconductor integrated circuit device having a scan path configured by connecting a plurality of scan registers in series, wherein the scan register includes a control terminal that receives a control signal that is activated in a predetermined period, A first input terminal provided on the scan path, a second input terminal provided outside the scan path, and a first input terminal provided on the scan path corresponding to the first input terminal. Output terminal, a second output terminal corresponding to the second input terminal and provided outside the scan path, an input end connected to the second input terminal, and an output end. Latching the data at the input end at the start of the predetermined period based on the control signal and outputting the data from the output end, and the data at the input end except the predetermined period. Output from the output terminal as it is, a first input terminal connected to the output terminal of the first latch circuit, and a second input terminal operatively connected to the first input terminal. A second latch circuit having an input terminal of the first latch circuit and an output terminal connected to the first and second output terminals, data at the output terminal of the first latch circuit, and the second latch circuit. Comparing means for comparing the data supplied to the second input terminal of the circuit, the second latch circuit, based on a comparison result of the comparing means, the first input terminal of the second latch circuit. The semiconductor integrated circuit device which latches the data at the start of the predetermined period in, and outputs the data to the output terminal of itself. 2. The scan register includes a third input terminal and a third output terminal both of which are provided outside the scan path, and a first input terminal connected to the third and first input terminals, respectively.
A third latch circuit having a second input terminal and an output terminal connected to the third output terminal; an input terminal connected to the output terminal of the third latch circuit; A first inverter having an output end connected to the second input end of a second latch circuit; an input end connected to the output end of the second latch circuit;
The semiconductor integrated circuit according to claim 1, further comprising: a second inverter having an output terminal, wherein the second output terminal is connected to the first output terminal via the second inverter. Circuit device. 3. A semiconductor integrated circuit device having a scan path configured by connecting a plurality of scan registers in series, wherein the scan register has a control terminal for receiving a control signal activated in a predetermined period, A first input terminal provided on the scan path, a second input terminal provided outside the scan path, and a first input terminal provided on the scan path corresponding to the first input terminal. Output terminal, a second output terminal corresponding to the second input terminal and provided outside the scan path, an input end connected to the second input terminal, and an output end. Latching the data at the input end at the start of the predetermined period based on the control signal and outputting the data from the output end, and the data at the input end except the predetermined period. A first input terminal connected to the output terminal of the first latch circuit, and a second input terminal connected to the first input terminal A second latch circuit having an output end operatively connected to the first and second output terminals, data at the output end of the first latch circuit, and the first output The second latch circuit starts the predetermined period at the first input terminal of the second latch circuit based on a comparison result of the comparison means. A semiconductor integrated circuit device for latching time data and outputting it to the output terminal of itself. 4. The scan register is connected to a third input terminal and a third output terminal both provided outside the scan path, an output terminal, and the output terminal of the second latch circuit. A first input terminal having a first input terminal connected to the third input terminal, a second input terminal connected to the output terminal of the first inverter, A second latch circuit having an output terminal, an input terminal connected to the output terminal of the third latch circuit, and an output terminal connected to the first output terminal The semiconductor integrated circuit device according to claim 3, further comprising an inverter, wherein the second output terminal is connected to an input terminal of the first inverter.