JPH0693482B2 - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPH0693482B2
JPH0693482B2 JP8437984A JP8437984A JPH0693482B2 JP H0693482 B2 JPH0693482 B2 JP H0693482B2 JP 8437984 A JP8437984 A JP 8437984A JP 8437984 A JP8437984 A JP 8437984A JP H0693482 B2 JPH0693482 B2 JP H0693482B2
Authority
JP
Japan
Prior art keywords
mounting portion
resin
element mounting
collector
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP8437984A
Other languages
Japanese (ja)
Other versions
JPS60226154A (en
Inventor
三聖雄 加藤
健一 立野
Original Assignee
松下電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電子工業株式会社 filed Critical 松下電子工業株式会社
Priority to JP8437984A priority Critical patent/JPH0693482B2/en
Publication of JPS60226154A publication Critical patent/JPS60226154A/en
Publication of JPH0693482B2 publication Critical patent/JPH0693482B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、回路基板等への高密度実装を可能にする樹脂
封止型半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device that enables high-density mounting on a circuit board or the like.

従来例の構成とその問題点 パワートランジスタは、回路基板あるいは放熱板へ絶縁
板を介して密着させ、トランジスタ素子内部で発生した
熱を速やかに外部へ放熱させる必要がある。
Configuration of Conventional Example and Problems Thereof It is necessary for the power transistor to be in close contact with the circuit board or the heat radiating plate via the insulating plate so that the heat generated inside the transistor element can be quickly radiated to the outside.

第1図(a)は、従来の代表的な樹脂封止型半導体装置
を示す平面図、第1図(b)は第1図(a)のA−A′
断面図である。
FIG. 1 (a) is a plan view showing a conventional typical resin-sealed semiconductor device, and FIG. 1 (b) is an AA ′ line in FIG. 1 (a).
FIG.

リードフレーム1の一部には、放熱板を兼ねる厚い素子
載置部2が形成されており、その一方の側に取付け用の
ビス(図示せず)を挿入するための孔3が形成されてい
る。素子載置部2の一端には、2本の細条4,4が一体に
形成されている。一方、素子載置部2の他端の中央には
コレクタ用外部リード5が一体に形成されている。コレ
クタ用外部リード5の両側には、ベース用外部リード6
およびエミッタ用外部リード7が隣接して配置されてい
る。なお、コレクタ用,ベース用,エミッタ用外部リー
ド5,6,7は、リードフレーム1の一部として形成されて
おり、リードフレームの状態では各外部リード5,6,7の
右端が、第1図(a)の右側の図示しない部分で相互に
一体に連結されている。トランジスタ素子8は、支持基
板9を介して素子載置部2の表面に接着されている。ト
ランジスタ素子8のベース電極とベース用外部リード6
は金属細線10で接続され、トランジスタ素子8のエミッ
タ電極とエミッタ用外部リード7は金属細線11で接続さ
れる。
A thick element mounting portion 2 also serving as a heat sink is formed in a part of the lead frame 1, and a hole 3 for inserting a mounting screw (not shown) is formed on one side thereof. There is. Two strips 4, 4 are integrally formed at one end of the element mounting portion 2. On the other hand, a collector external lead 5 is integrally formed at the center of the other end of the element mounting portion 2. On both sides of the collector external lead 5, the base external lead 6 is provided.
And the external lead 7 for emitter is arranged adjacently. The collector, base, and emitter external leads 5, 6, 7 are formed as a part of the lead frame 1. In the lead frame state, the right end of each external lead 5, 6, 7 is the first The right portion of FIG. (A) is integrally connected to each other at a portion not shown. The transistor element 8 is bonded to the surface of the element mounting portion 2 via the support substrate 9. Base electrode of transistor element 8 and base external lead 6
Are connected by a thin metal wire 10, and the emitter electrode of the transistor element 8 and the external lead 7 for an emitter are connected by a thin metal wire 11.

以上のような組立てが完了した後、細条4,4とコレクタ
用外部リード5を利用して素子載置部2を金型(図示せ
ず)内の中央付近に浮かせるように支持し、この状態
で、第1図(a),(b)に破線で示す樹脂封止域12内
を樹脂で封止する。
After the above-mentioned assembly is completed, the element mounting portion 2 is supported by using the strips 4 and 4 and the external leads 5 for the collector so as to float in the vicinity of the center of the die (not shown). In this state, the inside of the resin sealing area 12 shown by the broken lines in FIGS. 1A and 1B is sealed with resin.

その後、樹脂封止域12からはみ出た細条4,4の先端を切
断し、さらにコレクタ用,ベース用,エミッタ用の外部
リード5,6,7の右端を切断し、相互に切離すことによっ
て、樹脂封止型半導体装置が完成する。
After that, the tips of the strips 4 and 4 protruding from the resin sealing region 12 are cut, and further, the right ends of the external leads 5, 6 and 7 for the collector, the base and the emitter are cut and separated from each other. The resin-sealed semiconductor device is completed.

このような樹脂封止型半導体装置は、孔3に挿入サレタ
ビス(図示せず)を締付けることにより回路基板(図示
せず)に取付けられる。その結果、素子載置部2の下面
が回路基板に密着し、トランジスタ素子8の内部で発生
した熱が、素子載置部2および封止樹脂を介して岐路基
板に伝えられ、良好な放熱効果が得られる。
Such a resin-encapsulated semiconductor device is attached to a circuit board (not shown) by tightening an insert sale screw (not shown) in the hole 3. As a result, the lower surface of the element mounting portion 2 comes into close contact with the circuit board, and the heat generated inside the transistor element 8 is transferred to the branch substrate via the element mounting portion 2 and the sealing resin, and a good heat dissipation effect is obtained. Is obtained.

ところが、従来の樹脂封止型半導体装置においては、回
路基板などへの取付けの際に、ビス止めの作業が必要で
ある。そのため実装時の作業性は必ずしもよくない。特
に、回路基板などへの部品の実装密度が高くなると、ビ
ス止めの作業が著しく困難になる。
However, in the conventional resin-encapsulated semiconductor device, a screwing operation is required when it is attached to a circuit board or the like. Therefore, workability at the time of mounting is not always good. In particular, when the mounting density of components on a circuit board or the like becomes high, the work of screw fixing becomes extremely difficult.

また、コレクタ用,ベース用,エミッタ用の各外部リー
ド5,6,7が、素子載置部2の一方の側(第1図(a),
(b)では右側)に配置されている。このため、回路基
板などへの実装時に、隣接して実装される他の部品等と
の位置関係から、取付方向が制約されたり、多くの無駄
な空間を必要とすることが多く、結果的に実装密度が低
下するという問題がある。
Also, the external leads 5, 6, 7 for the collector, the base, and the emitter are connected to one side of the element mounting portion 2 (see FIG. 1 (a),
It is arranged on the right side in (b). Therefore, when mounted on a circuit board or the like, the mounting direction is often restricted or a large amount of wasted space is required due to the positional relationship with other components that are mounted adjacent to each other. There is a problem that the packaging density is reduced.

発明の目的 本発明は、外部リードを回路基板などの取付基板に接続
するだけで、素子載置部を取付基板に密着させることが
でき、しかもコレクタ用外部リードの接続方向に自由度
をもたせることによって実装密度を高くすることのでき
る樹脂封止型半導体装置を提供するものである。
An object of the present invention is to make it possible to bring the element mounting portion into close contact with the mounting board by simply connecting the external leads to the mounting board such as a circuit board, and also to provide a degree of freedom in the connecting direction of the collector external lead. The present invention provides a resin-encapsulated semiconductor device capable of increasing the mounting density.

発明の構成 本発明の樹脂封止型半導体装置は、平面矩形の素子載置
部の上面に半導体素子を載置し、前記素子載置部の対向
2辺部両側面の前記上面に接する各位置から、それぞ
れ、成形樹脂の外方に引き出された前記素子載置部の厚
みより薄い外部リードを有し、かつ、前記成形樹脂が、
前記素子載置部の上面側よりも、下面側において薄く形
成され、前記両側面から引き出される前記外部リードを
前記成形樹脂の外で前記素子載置部の下面側に折り曲
げ、前記外部リードの先端部下面を前記成形樹脂の下面
とほぼ同一面になしたものであり、これによって、回路
基板への高密度実装が可能になると共に、前記素子載置
部からの放熱機能が、前記成形樹脂層の回路基板面への
密着性向上によって、一段と助長される。
Configuration of the Invention In the resin-encapsulated semiconductor device of the present invention, a semiconductor element is mounted on the upper surface of a flat rectangular element mounting portion, and each position in contact with the upper surface of the two opposite side surfaces of the element mounting portion. From, respectively, having an outer lead that is thinner than the thickness of the element mounting portion pulled out of the molding resin, and, the molding resin,
The outer leads, which are formed thinner on the lower surface side than on the upper surface side of the element mounting portion and are drawn from the both side surfaces, are bent to the lower surface side of the element mounting portion outside the molding resin, and the tips of the outer leads are formed. The lower surface of the part is substantially flush with the lower surface of the molding resin, which enables high-density mounting on the circuit board, and the function of radiating heat from the element mounting part is the molding resin layer. It is further promoted by improving the adhesion of the to the circuit board surface.

実施例の説明 以下、本発明の第1の実施例を第2図とともに説明す
る。
Description of Embodiments A first embodiment of the present invention will be described below with reference to FIG.

第2図(a)は本発明の第1の実施例における樹脂封止
型半導体装置の平面図、第2図(b)は第2図(a)の
B−B′断面図である。
2 (a) is a plan view of the resin-sealed semiconductor device according to the first embodiment of the present invention, and FIG. 2 (b) is a sectional view taken along the line BB 'of FIG. 2 (a).

第2図(a),(b)において、リードフレーム13の一
部には、放熱板を兼ねる厚い矩形の素子載置部14が形成
されており、その一端に第1のコレクタ用外部リード15
が一体に形成されている。第1のコレクタ用外部リード
15の幅Wは、素子載置部14の幅Lの0.4倍以上に設定さ
れている。一方、素子載置部14の他端には第2のコレク
タ用外部リード16が一体に形成されている。第2のコレ
クタ用外部リード16の幅は、第1のコレクタ用外部リー
ド15の幅より狭い。なお、第2図(b)から明らかなよ
うに、第1,第2のコレクタ用外部リード15,16は、いず
れも素子載置部14より薄い。第2のコレクタ用外部リー
ド16の両側には、ベース用外部リード17およびエミッタ
用外部リード18が隣接して配置されている。なお、各外
部リード16.17,18は、リードフレーム13の一部として形
成されており、リードフレームの状態では、各外部リー
ド16,17,18の右端が、第2図(a)の右側の図示しない
部分で相互に連結されている。トランジスタ素子19は、
支持基板20を介して素子載置部14の表面に装着されてい
る。トランジスタ素子19のベース電極とベース用外部リ
ード17は金属細線21で接続され、トランジスタ素子19の
エミッタ電極とエミッタ用外部リード18は金属細線22で
接続される。
In FIGS. 2A and 2B, a thick rectangular element mounting portion 14 which also serves as a heat sink is formed on a part of the lead frame 13, and one end of the first collector external lead 15 is formed on the element mounting portion 14.
Are integrally formed. External lead for first collector
The width W of 15 is set to 0.4 times or more the width L of the element mounting portion 14. On the other hand, a second collector external lead 16 is integrally formed at the other end of the element mounting portion 14. The width of the second outer collector lead 16 is smaller than the width of the first outer collector lead 15. As is apparent from FIG. 2B, the first and second collector external leads 15 and 16 are thinner than the element mounting portion 14. A base external lead 17 and an emitter external lead 18 are arranged adjacent to each other on both sides of the second collector external lead 16. The external leads 16.17, 18 are formed as a part of the lead frame 13, and in the state of the lead frame, the right ends of the external leads 16, 17, 18 are shown on the right side of FIG. 2 (a). Not connected to each other. The transistor element 19 is
It is mounted on the surface of the element mounting portion 14 via the support substrate 20. The base electrode of the transistor element 19 and the base external lead 17 are connected by a metal thin wire 21, and the emitter electrode of the transistor element 19 and the emitter external lead 18 are connected by a metal thin wire 22.

以上のような組立てが完了した後、第1,第2のコレクタ
用外部リード15,16を利用して素子載置部14を金型(図
示せず)内の中央付近に浮かせるように支持し、この状
態で、第2図(a),(b)に破線で示す樹脂封止域23
内を樹脂で封止する。
After the above-mentioned assembly is completed, the element mounting portion 14 is supported by the first and second external leads 15 and 16 for the collector so as to float in the vicinity of the center of the mold (not shown). In this state, the resin sealing area 23 shown by the broken line in FIGS.
The inside is sealed with resin.

その後、樹脂封止域23から突出した外部リード15,16,1
7,18の先端をリードフレームの枠体(図示せず)から切
り離し、更に各外部リード15,16,17,18の先端付近に第
2図(b)のような折曲げ加工を施す。この状態では、
各外部リード15,16の先端部の下面と樹脂封止域23の下
面とがほぼ同一面となる。
After that, the external leads 15, 16, 1 protruding from the resin sealing area 23
The tips of 7, 18 are separated from the frame body (not shown) of the lead frame, and the outer leads 15, 16, 17, 18 are bent near the tips as shown in FIG. 2 (b). In this state,
The lower surfaces of the tip portions of the outer leads 15 and 16 and the lower surface of the resin sealing area 23 are substantially flush with each other.

このような樹脂封止型半導体装置を回路基板へ装着する
際には、外部リード15,16,17,18の先端部下面を回路基
板の銅箔に半田等を用いて接続すればよい。このように
すれば、各外部リード15,16,17,18と回路基板の所定の
接続点とが電気的に接続される。また樹脂封止域23の下
面と回路基板とが密着するため、トランジスタ素子19の
内部で発生した熱も、素子載置部14、封止樹脂および回
路基板を介して放熱される。しかも、第1のコレクタ用
外部リード15と、それ以外の外部リード16,17,18とが、
素子載置部14の両側に振り分けて配置されているため、
外部リード15,16,17,18の先端が回路基板に接続された
状態では、封止樹脂の下面全域が回路基板表面に密着す
る。このため、従来のビス止めに比べて決して遜色のな
い良好な放熱効果が得られる。もちろん、封止樹脂によ
り、半導体装置の内部部品と回路基板との絶縁が保たれ
る。さらに、第1,第2のコレクタ用外部リード15,16
が、素子載置部2の両側から引き出されているため、実
装時の実装方向の自由度も大きくなる。すなわち、回路
基板に十分なスペースがあり、コレクタ接続用に2つの
接続点を設けることができるときは、2つの接続点に対
して第1,第2のコレクタ用外部リード15,16をそれぞれ
接続すればよい。一方、回路基板に十分なスペースがな
く、隣接する他の部品との位置関係から、素子載置部14
のいずれか一方の側にしか接続点が設けられないとき
は、第1,第2のコレクタ用外部リード15,16のうちのい
ずれか一方のみを用いてコレクタの接続を行えばよい。
この場合でも、二方向のうちのいずれかを選ぶことがで
きるから、装着方向の自由度はかなり大きくなる。
When mounting such a resin-encapsulated semiconductor device on a circuit board, the lower surfaces of the tips of the external leads 15, 16, 17, 18 may be connected to the copper foil of the circuit board using solder or the like. With this configuration, each external lead 15, 16, 17, 18 is electrically connected to a predetermined connection point on the circuit board. Further, since the lower surface of the resin sealing area 23 and the circuit board are in close contact with each other, heat generated inside the transistor element 19 is also radiated through the element mounting portion 14, the sealing resin and the circuit board. Moreover, the first external lead 15 for collector and the other external leads 16, 17, 18 are
Since it is arranged separately on both sides of the element mounting portion 14,
When the tips of the external leads 15, 16, 17, 18 are connected to the circuit board, the entire lower surface of the sealing resin is in close contact with the surface of the circuit board. Therefore, a good heat dissipation effect comparable to that of the conventional screw stopper can be obtained. Of course, the sealing resin maintains the insulation between the internal components of the semiconductor device and the circuit board. Furthermore, external leads 15 and 16 for the first and second collectors
However, since it is pulled out from both sides of the element mounting portion 2, the degree of freedom in the mounting direction at the time of mounting also becomes large. That is, when there is sufficient space on the circuit board and two connection points can be provided for collector connection, the first and second collector external leads 15 and 16 are connected to the two connection points, respectively. do it. On the other hand, there is not enough space on the circuit board, and due to the positional relationship with other adjacent components, the element mounting portion 14
If the connection point is provided only on one of the two sides, the collector may be connected using only one of the first and second collector external leads 15 and 16.
Even in this case, one of the two directions can be selected, so that the degree of freedom in the mounting direction becomes considerably large.

第3図は本発明の第2の実施例を示すものであり、第2
のコレクタ用外部リード16の先端を切断したものであ
る。すなわち、樹脂封止時に素子載置部14を金型中央に
浮かせた状態で支持するために第1,第2のコレクタ用外
部リード15,16を用いることは第1の実施例と同様であ
るが、樹脂封止後のリードフレームからの切断時に第2
のコレクタ用外部リード16を短く切断したものである。
FIG. 3 shows a second embodiment of the present invention.
The tip of the external lead 16 for the collector is cut. That is, it is similar to the first embodiment that the first and second collector external leads 15 and 16 are used to support the element mounting portion 14 in a state of being floated in the center of the mold during resin sealing. However, when cutting from the lead frame after resin sealing,
The external lead 16 for collector of is cut short.

この場合、第2のコレクタ用外部リード16は電気的な接
続には寄与しないが、回路基板への実装時にあらかじめ
コレクタ用の接続点が固定できる場合には、その接続点
に対して第1のコレクタ用外部リード15を接続すればよ
い。この場合でも、素子載置部14の一方の側が第1のコ
レクタ用外部リード15で回路基板に接続され、他方の側
がベース用外部リード17,エミッタ用外部リード18で回
路基板に接続される。このため、封止樹脂の下面全域が
回路基板表面に密着し、良好な放熱効果が得られること
は変わりがない。
In this case, the second collector external lead 16 does not contribute to electrical connection, but if the collector connection point can be fixed in advance when mounted on the circuit board, the first external collector lead 16 can be connected to the first connection point. The collector external lead 15 may be connected. Also in this case, one side of the element mounting portion 14 is connected to the circuit board by the first collector external lead 15 and the other side is connected to the circuit board by the base external lead 17 and the emitter external lead 18. Therefore, the entire lower surface of the sealing resin is in close contact with the surface of the circuit board, and a good heat dissipation effect can be obtained.

第4図は、第2図(a)に示す素子載置部14の幅Lと第
1のコレクタ用外部リード15の幅Wの比(W/L)と、外
部リード15,16,17,18の先端を回路基板へ半田で接続し
た場合に得られる熱抵抗との関係を示した図である。第
4図から明らかなように、第1のコレクタ用外部リード
15の幅Wと素子載置部14の幅Lの比(W/L)が0.4以上で
あれば、熱抵抗が安定した状態となる。
FIG. 4 shows the ratio (W / L) of the width L of the element mounting portion 14 and the width W of the first collector external lead 15 shown in FIG. 2 (a) to the external leads 15, 16, 17, It is a figure showing the relation with the thermal resistance obtained when the tip of 18 is connected to a circuit board by soldering. As is clear from FIG. 4, the first external lead for the collector
If the ratio (W / L) of the width W of 15 to the width L of the element mounting portion 14 is 0.4 or more, the thermal resistance becomes stable.

発明の効果 本発明によれば、回路基板等への実装密度を高めること
ができ、良好な放熱効果が得られる樹脂封止型半導体装
置が実現できる。
EFFECTS OF THE INVENTION According to the present invention, it is possible to realize a resin-encapsulated semiconductor device that can increase the mounting density on a circuit board or the like and can obtain a good heat dissipation effect.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)は従来の樹脂封止型半導体装置の平面図、
第1図(b)は第1図(a)のA−A′断面図、第2図
(a)は本発明の第1の実施例における樹脂封止型半導
体装置の平面図、第2図(b)は第2図(a)のB−
B′断面図、第3図は本発明の第2の実施例における樹
脂封止型半導体装置の平面図、第4図は素子載置部、第
1のコレクタ用外部リードの幅の寸法比と熱抵抗の関係
を示す特性図である。 13……リードフレーム、14……素子載置部、15……第1
のコレクタ用外部リード、16……第2のコレクタ用外部
リード、17……ベース用外部リード、18……エミッタ用
外部リード、19……トランジスタ素子、20……支持基
板、21,22……金属細線、23……樹脂封止域。
FIG. 1A is a plan view of a conventional resin-encapsulated semiconductor device,
1 (b) is a sectional view taken along the line AA 'in FIG. 1 (a), and FIG. 2 (a) is a plan view of a resin-sealed semiconductor device according to the first embodiment of the present invention. (B) is B- in FIG. 2 (a)
B'sectional view, FIG. 3 is a plan view of the resin-sealed semiconductor device in the second embodiment of the present invention, and FIG. 4 is a width ratio of the element mounting portion and the first external lead for collector. It is a characteristic view which shows the relationship of thermal resistance. 13 ... Lead frame, 14 ... Element mounting part, 15 ... First
External collector lead, 16 …… second collector external lead, 17 …… base external lead, 18 …… emitter external lead, 19 …… transistor element, 20 …… support substrate, 21,22 …… Thin metal wire, 23 ... Resin sealing area.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭54−151172(JP,A) 実開 昭49−10463(JP,U) 実開 昭53−143562(JP,U) 実公 昭45−15928(JP,Y1) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-54-151172 (JP, A) Actually open 49-10463 (JP, U) Actually open 53-143562 (JP, U) Actual public 45- 15928 (JP, Y1)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】平面矩形の素子載置部の上面に半導体素子
を載置し、前記素子載置部の対向2辺部両側面の前記上
面に接する各位置から、それぞれ、成形樹脂の外方に引
き出された前記素子載置部の厚みより薄い外部リードを
有し、かつ、前記成形樹脂が、前記素子載置部の上面側
よりも、下面側において薄く形成され、前記両側面から
引き出される前記外部リードを前記成形樹脂の外で前記
素子載置部の下面側に折り曲げ、前記外部リードの先端
部下面を前記成形樹脂の下面とほぼ同一面になした樹脂
封止型半導体装置。
1. A semiconductor element is mounted on the upper surface of a flat rectangular element mounting portion, and the outer side of the molding resin is respectively placed from respective positions in contact with the upper surface on opposite two side portions of the element mounting portion. An external lead that is thinner than the thickness of the element mounting portion that has been pulled out, and the molding resin is formed thinner on the lower surface side than on the upper surface side of the element mounting portion, and is pulled out from both side surfaces. A resin-encapsulated semiconductor device in which the outer lead is bent outside the molding resin toward the lower surface side of the element mounting portion, and the lower end surface of the outer lead is substantially flush with the lower surface of the molding resin.
JP8437984A 1984-04-25 1984-04-25 Resin-sealed semiconductor device Expired - Lifetime JPH0693482B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8437984A JPH0693482B2 (en) 1984-04-25 1984-04-25 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8437984A JPH0693482B2 (en) 1984-04-25 1984-04-25 Resin-sealed semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP7711594A Division JP2512289B2 (en) 1994-04-15 1994-04-15 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPS60226154A JPS60226154A (en) 1985-11-11
JPH0693482B2 true JPH0693482B2 (en) 1994-11-16

Family

ID=13828906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8437984A Expired - Lifetime JPH0693482B2 (en) 1984-04-25 1984-04-25 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH0693482B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0777248B2 (en) * 1988-11-09 1995-08-16 富士電機株式会社 Resin-sealed semiconductor device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4910463U (en) * 1972-04-28 1974-01-29
JPS5415172A (en) * 1977-07-07 1979-02-03 Fujitsu Ltd Way of fixing electronic parts

Also Published As

Publication number Publication date
JPS60226154A (en) 1985-11-11

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