JPH0693195B2 - Music signal generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a musical tone signal generator, and in particular, generates each order component corresponding to a fundamental wave (fundamental tone) and its harmonics (harmonics) that compose a musical tone, The present invention relates to a harmonic synthesis type musical tone signal generator which generates a musical tone signal by weighting each of these components with a corresponding amplitude coefficient and then synthesizing them.

[Background technology and its problems]

This type of harmonic synthesis type musical tone signal generator appropriately sets an amplitude coefficient (hereinafter, referred to as a harmonic coefficient) for controlling the amplitude of each fundamental component and each order component of the harmonic (hereinafter referred to as a harmonic component). It is extremely excellent in that it can generate tone signals of various tones simply by setting it.

By the way, it has been conventionally proposed to generate a tone signal whose tone color changes with time like a natural musical instrument sound by changing the harmonic coefficient for each of the above harmonic components over time. Has been done. For example,
It is disclosed in Japanese Patent Publication No. 58-20039.

However, in this conventional technique, in order to change each harmonic coefficient with the passage of time, an envelope memory (attack / date memory) is provided for each harmonic component. The same number of envelope memories as the number of components is required, and it is necessary to prepare a group of a plurality of envelope memories for each mode of timbre change over time. Therefore, a very large capacity memory is prepared as a whole. However, there is an inconvenience that the cost becomes very high as the configuration becomes large.

[Object of the Invention]

The present invention has been made in consideration of the above points, and generates a tone signal whose tone color changes with time at a low cost with a simple configuration by significantly reducing the memory capacity as compared with the prior art. An attempt is made to propose a musical tone signal generator of the harmonic synthesis system which is designed to be obtained.

[Outline of Invention]

In the harmonic synthesis type musical tone signal generator, in order to generate a musical tone signal whose tone color changes with time, it is necessary to change each harmonic coefficient as time passes, as described above. According to the present invention, harmonic coefficients that change with time are formed as follows.

That is, first, as shown in FIG. 2 in which the amplitude value of a tone signal to be generated is standardized (the amplitude envelope is removed to make the amplitude value constant), a plurality of frames from the tone signal generation to the end are generated. Divide into That is, since the musical tone waveform MW of this musical tone signal changes with time, the amplitude ratio of the harmonic components of each order contained in this musical tone waveform MW also changes with the passage of time.
In this case, since there is no extreme change in the tone color for a relatively short time, the time points t ₁ , t ₂ ... t between the predetermined period t _{0 to} t _N of the entire period from the generation to the end of the tone signal. Divide by _N-1 to form N frames F1, F2 ... FN. Since there is almost no change in timbre after time t _N, the final frame F (N + 1) corresponding to this is provided.

Here, the relative amplitude levels of the respective harmonic components constituting the tone waveform at the times t ₀ , t ₁ , t _2, ... T _N in FIG. 2 are as shown in FIGS. 3 (A) to (D), respectively. It should take any value. At the start time t ₀ of the first frame F1 in FIG. 2, a set of first- to W-th order (W is, for example, 64) harmonic coefficients having a spectrum distribution curve as shown in FIG. 3 (A). Generate data Q1. Further, at the starting time t ₁ of the second frame F2, generating a primary ~W following set of harmonic coefficient data Q2 having a spectral distribution curve as shown in FIG. 3 (B). Hereinafter, generating harmonics coefficient data Q3 at time t ₂ ~t _N in the same manner (FIG. 3 (C)) ~Q (N + 1) ( FIG. 3 (D)).

Then, each harmonic coefficient data generated during the time _{t 0 ~t 1, t 1 ~t} 2 ...... t N-1 ~t N from each of the data Q1
From Q2, Q2 to Q3 ... QN to Q (N + 1).

Although harmonic coefficient data Q1 when point t ₀ of the first invention produced as harmonic coefficient data time t ₀ after reads the coefficient data of the difference stored in the interpolation coefficient memory,
Using the coefficient data of this difference, time points t ₀ to t ₁ , t _{1 to} t ₂ ...... t
Between the _N-1 ~t _N to the interpolation operation connexion occur.

That is, as shown in FIG. 4, for example, the interpolation coefficient memory stores the difference between the first harmonic coefficient data of adjacent frames.
Q2-Q1 (Fig. 4 (A)), Q3-Q2 (Fig. 4 (B)) ...
The coefficient data of the difference determined based on Q (N + 1) -QN (Fig. 4 (C)) is stored, and the coefficient data of this difference is stored at the time
Read at t ₀ , t ₁ , t ₂ ... t _N respectively. The first, gradually in due connexion each frame to interpolation calculation repeatedly a predetermined number of times (i.e. K _1, K ₂ ...... K _N) by using an arithmetic circuit in the second ...... N-th frame F1, F2 ...... FN Is obtained, and this interpolation data is added to the harmonic coefficient data Q1 at time t ₀ to form harmonic coefficient data.

By doing so, the harmonic coefficient data smoothly changes from the coefficient value at the start of the frame to the coefficient value at the start of the next frame in fine steps every time interpolation calculation is performed in each frame. I will go.

As the difference coefficient data stored in the interpolation coefficient memory, the following is specifically used as an example. The first is, as shown in FIG. 5, the harmonic coefficient data Q1 to QN to be generated at the start times t _{0 to} t _N−1 of the _first to Nth frames F1 to FN and the adjacent harmonic coefficient data Q1 to QN. 2 (N + 1) th harmonic coefficient data Q2 to be generated at the beginning t ₁ ~t _N frame
To Q (N + 1) are stored in the interpolation coefficient memory as difference coefficient data, which is a value obtained by dividing the number of interpolation calculations K _{1 to} K _N in each frame.

The interpolation calculation in this case is executed as follows, for example. That is, for example, the Mth-order harmonic coefficient data will be described. The value L ₁ at the start time t ₀ of the first frame F ₁
If the value L ₂ at time t ₁ (FIG. 3 (A)) changes to the value L ₂ (FIG. 3 (B)), the difference coefficient data stored in the interpolation coefficient memory is the difference L ₂ −L ₁ ( The value obtained by dividing (A) in FIG. 4 by the number of interpolations K ₁ in the first frame F1 is (L ₂ −L ₁ ) / K ₁ and is from time t _{0 to} t ₁ (during the first frame F1). from the harmonic coefficient data value L ₁ each time the interpolation operation is repeated in
It changes to L ₂ by (L ₂ −L ₁ ) / K _{1 and} reaches the value L ₂ at time t ₁ .

Similarly, in the interpolation coefficient memory, the values L ₃ and L ₂ (FIGS. 3 (C) and (B)) for the second frame F2 at the times t _{1 to} t ₂ are stored.
The difference (L ₃ -L ₂₎ stored as (FIG. 4 (B)) the split ivy value interpolation number K ₂ in the second frame _{F2 (L 3 -L 2) /} K 2 is the coefficient of the difference data, ......... WariTsuta at t _N-1 ~t value for the N-th frame FN of _N L _{N + 1} and L _N of the difference (L _{N + 1} -L _N) times the interpolation in the N-th frame NF K _N Value (L _{N + 1} −L _N ) /
K _N is stored as difference coefficient data.

Thus, the harmonic coefficient data, in the second frame F2, consists values of L ₂ at the time t ₁ to the difference (L ₃ -L ₂₎ / K ₂ increments the changed value L ₃ at time t _2, the ... ... Difference (L _{N + 1} −L _N ) from the value L _N at time t _N−1 in the Nth frame FN
/ K _N, and it changes continuously and sequentially so that the value becomes L _{N + 1} at time t _N.

In the case of the second aspect of the invention, the difference Q2-Q between the first harmonic coefficient data Q1 to Q (N + 1) of the above-described sequentially adjacent frames is provided.
1, Q3−Q2, ... Q (N + 1) −QN are directly stored in the interpolation coefficient memory as difference coefficient data. In this case, the arithmetic circuit multiplies the read coefficient data of the difference by the weighting coefficient that changes sequentially each time the interpolation calculation is repeated in each frame, and obtains the interpolation data that changes with time in each frame. obtain. Then, the data representing the multiplication result at the end of each frame is temporarily stored for each degree, and the temporarily stored data, the multiplication result, and the basic coefficient data are added for each degree, and Obtain the amplitude coefficient for each order.

As the difference coefficient data stored in the interpolation coefficient memory, the following data can be used instead of the above-mentioned data.

That is, predetermined harmonic coefficient data (for example, the above-mentioned harmonic coefficient data Q1) is used as basic coefficient data, and this basic coefficient data and the harmonic coefficient data Q1, Q2, ... Q (which should be generated at the beginning of each frame). N + 1) and the data relating to the difference are stored in the interpolation coefficient memory as difference coefficient data. In this case, the difference coefficient data stored in the interpolation coefficient memory may be the difference value between the first harmonic coefficient data Q1 to Q (N + 1) in each frame and the basic coefficient data, or the error May be divided by the number of interpolations in each frame (K ₁ , K ₂ ... K _N ). In the former case, the arithmetic circuit multiplies the coefficient data of the read difference by the weighting coefficient which changes sequentially each time the interpolation calculation is repeated in each frame, and changes with the passage of time in each frame. Harmonic coefficient data is formed by obtaining interpolation data and adding this interpolation data to the basic coefficient data. Further, in the latter case, the arithmetic circuit obtains the interpolation data which changes with the passage of time in each frame by repeatedly accumulating the read difference coefficient data for each frame according to the number of interpolations. ,
This is added to the basic coefficient data to form harmonic coefficient data.

In this way, the data required to generate the harmonic coefficients of each order that change with time are:
Only one set (1st to Wth) of harmonic coefficient data or a predetermined set of basic coefficient data at the start of the tone signal generation and one set of difference data used for interpolation calculation in each frame are sufficient. Since the respective values forming the difference data have sufficiently small values, the memory capacity as a whole can be sufficiently reduced.

The method of dividing the frame may be the same for each order (this is the case in the above description), or may be different for each order.

〔Example〕

First Embodiment FIG. 1 shows an embodiment in which the musical tone signal generator according to the present invention is applied to a single-tone electronic musical instrument. In this embodiment, the amplitude value X ₀ (qR) of the sequential sampling points qR of the musical tone signal (tone waveform) corresponding to the key pressed on the keyboard is changed to the following at regular time intervals (sampling time) t _x : It is calculated according to the equation (1).

Here, q is a variable that increases by 1, 2, ... For each time interval t _x , n represents the order of each harmonic component including the fundamental wave, and n = 1 represents the fundamental wave (fundamental tone), n = 2 represents the second harmonic (second overtone), ... N = W represents the Wth harmonic (Wth overtone). In this embodiment, W = 64. Further, R represents a numerical value (hereinafter referred to as a frequency number) corresponding to the fundamental frequency (pitch) of the musical sound, A (t) represents an envelope function for setting the amplitude envelope of the musical sound, and C _n represents the nth harmonic. Represents the harmonic coefficient for the wave component.

In FIG. 1, reference numeral 1 is a key switch circuit, in which key data KD corresponding to a depressed key is given to a frequency number memory 2, and a frequency number R having a numerical value corresponding to a pitch of the depressed key is read out. It is then transmitted to the accumulator 3. The accumulator 3 accumulates the frequency number R every time the calculation section timing signal t _x is given to its clock terminal CK, and the accumulated data qR (q = 1, 2, ...) It is sent to the harmonic component generating circuit 4 as designated phase data.

5 is a clock oscillator whose clock signal t _c is 64
It is given to the order counter 6 having a modular structure, and the calculation section timing signal t _x is transmitted from the carrier output terminal thereof. Thus, as shown in FIG. 6A, the calculation interval timing signal t _x is generated every time 64 clock pulse signals t _c are generated.
(FIG. 6 (B)) is obtained, whereby one cycle T _tx of the calculation section timing signal t _x is divided into 64 by the clock signal t _c in correspondence with each harmonic component of the 1st to 64th order. It is designed to form a time slot.

The harmonic component generation circuit 4 calculates the harmonic signal components of the 1st to 64th harmonics in each of the time slots set by the clock signal t _{c from} among the above equations (1). The sinusoidal waveform data S1 represented by is generated and given to the harmonic amplitude multiplication circuit 11. The harmonic component generation circuit 4
For example, those disclosed in the above-mentioned Japanese Patent Publication No. 58-20039 and Japanese Patent Laid-Open No. 55-43552 can be applied.

The harmonic amplitude multiplication circuit 11 is supplied with the harmonic coefficient data S2 corresponding to the harmonic coefficient C _n of the above equation (1) from the harmonic coefficient generation circuit 7, and the sine waveform data S1 and the harmonic coefficient data S2 are given. The multiplication output data S3 obtained by multiplying by and is given to the tone signal output circuit 8.

The tone signal output circuit 8 forms a tone signal by adding and synthesizing the data S3 based on the clock signal t _c and the calculation section timing signal t _x, and at the same time based on the key-on signal KON obtained from the key switch circuit 1. A musical tone signal S4 represented by the above-mentioned equation (1) is output with an amplitude envelope added, and this is converted into a musical tone in the sound system 9. As the tone signal output circuit 8, for example, Japanese Patent Laid-Open No. 54-
The one disclosed in 140523 or JP-A-55-45056 can be applied.

In the case of this embodiment, when the respective key switches are depressed, the key switch circuit 1 generates a key-on signal KON which becomes logic "1" until the key is released, as shown in FIG. 7 (A). A differentiation circuit that receives the calculation interval timing signal t _x as a trigger signal based on the rise of this key-on signal KON
In 10, the key-on pulse signal KONP (FIG. 7 (B)) having the period T _tx of the calculation section timing signal t _x is transmitted.

The harmonic coefficient generating circuit 7 includes a basic coefficient memory 21 for storing the basic coefficient data described above with reference to FIG. 3 (A) and the interpolation difference data (Q2 described above with reference to FIGS. 4 (A) to (C) and FIG. _{-Q1) / K 1, (Q3} -Q2) / K 2 ...... [Q (N-
1) -QN] / K _N is included in the interpolation difference coefficient memory 22. Each of the memories 21 and 22 stores the above-mentioned data corresponding to each timbre that can be generated, and basic coefficient data RD and interpolation corresponding to the timbre selected by the timbre selection signal TC of the timbre selection circuit 23. The difference coefficient data DD can be read out.

The basic coefficient memory 21 receives the order data n representing the count content of the order counter 6 as an address signal, sequentially reads the basic coefficient data RD of the 1st to 64th order according to the order data n, and adds the adder circuit 25 of the arithmetic circuit 24. As a first addition input signal.

The interpolation difference coefficient memory 22 receives the order data n of the order counter 6 and the frame designation data FNO generated in the frame data generation circuit 31 as an address signal, and the order data n of the frame designated by the frame designation data FNO. Accordingly, the 1st to 64th interpolation difference coefficient data DD are sequentially read.

The frame data generation circuit 31 has a repetition number counter 32 that counts the number of interpolation calculations, and is a counter that counts according to a carry signal CA generated in the accumulator 3. Here, when the cumulative calculation force of the accumulator 3 exceeds the maximum value (that is, all "0").
Or when all "1" is reached), the carrier signal CA is generated. The accumulator 3 accumulates the frequency number data R so that the maximum value is reached every time one cycle of the musical tone waveform elapses. Thus, the repetition number counter 32 has one cycle of the musical tone waveform. The counting operation is performed one by one every time a minute has elapsed. As a result, the count content of the repeat count counter 32 represents the number of tone waveforms in each frame, that is, the repeat count in the calculation circuit 24.
Sent as CV.

The repeat count data CV of the repeat count counter 32 is supplied to the comparison circuit 33 and compared with the repeat count data K obtained at the output terminal of the repeat count specifying circuit 34. As a result, when a match is obtained, the match detection signal EQ sent from the comparison circuit 33 is given to the count input terminal of the frame counter 37 through the gate circuit 36, and the repetition number counter is passed through the delay circuit 38 and the OR circuit 39. It is adapted to be applied to 32 reset input terminals R. The key-on pulse signal KONP is input to the repetition number counter 32 through the OR circuit 39, whereby the repetition number counter 32 is reset.

The repeat number designating circuit 34 is, as described above with reference to FIGS. 2 and 5, the first, second ... Nth frame F1, F2.
Predetermined number of iterations for FN K ₁ , K ₂ …… K _N
Is stored for each timbre, and the stored data is read out by the timbre selection signal TC and the frame number data FNO coming from the frame counter 37, and sent out as the repeat count designation data K. Therefore, when the number of repetitions designated by the number-of-repetitions designation data K from the number-of-repetitions designation circuit 34 and the number of repetitions count data CV of the number-of-repetitions counter 32 match for each frame, the comparison circuit 33 ( That is, at the end of each frame), the coincidence detection output EQ is generated and the repetition number counter 32
Is reset, and the frame counter 37 is caused to count through the gate circuit 36.

The frame counter 37 displays the key-on pulse signal KONP.
Is supplied as a reset signal, and the contents of the count after resetting are transmitted as frame designation data FNO.

The frame designation data FNO of the frame counter 37 is given to the final frame detection circuit 40. Final frame detection circuit
40 outputs the final frame detection output FD which rises to logic “1” when the frame designation data FNO reaches (N + 1),
This is given to the enable terminal of the gate circuit 36 via the inverter 41 as an inverted output ▲ ▼. As a result, when the final frame FN ends, the gate circuit 36 is closed to stop the counting operation of the frame counter 37 and prevent the frame designation data FNO from changing.

The interpolation difference coefficient memory 22 sequentially reads a set of (1st to 64th) interpolation difference coefficient data DD corresponding to the frame designated by the frame designation data FNO using the order data n as an address signal, It is given to the adding circuit 44 of the accumulator 43 through the circuit 42. Here, the interpolation difference coefficient data DD sent from the interpolation difference coefficient memory 22 can take a positive or negative sign, and the adder circuit 43 performs an adding operation including this sign.

The addition output S11 of the adding circuit 44 is given to the shift register 46 having a 64-stage configuration through the gate circuit 45. The shift register 46 shifts in response to the clock signal t _c to sequentially capture interpolated difference coefficient data DD for each of the 1 st to 64 th harmonics, and sequentially fetch the interpolated difference coefficient data DD. When 64 pieces of data are fetched, the feedback signal is fed back from the output terminal to the addition circuit 44 as the other addition input.

A control signal S12 is applied from the AND circuit 47 to the enable terminal of the gate circuit 42. AND circuit 47 is an inverter 41
Under the condition that the inverted output ▲ of is a logic "1" (in other words, it is not in the final frame), at the timing when the carrier signal CA of the accumulator 3 rises, the differentiation circuit 48 (timing signal t _x becomes The gate circuit is controlled by a control signal S12 which rises by a differential output S13 which becomes a logic "1" during a calculation section T _{tx from} the time when one period of the musical tone waveform elapses. 1st to 64th order interpolation difference coefficient data to the accumulator 43 through 42
Give DD.

As a result, the adder circuit 44, for each of the 1st to 64th orders,
Output added one cycle before stored in shift register 46
The interpolation difference coefficient data DD coming through the gate circuit 42 is sequentially added to S11. In this way, the accumulator 43 sequentially accumulates the interpolation difference coefficient data DD of each order sent from the interpolation difference coefficient memory 22 for each cycle T _{tx of the} calculation section timing signal t _x .

This accumulated data is taken out from the output terminal of the gate circuit 45,
The difference accumulation coefficient data DS is given to the adder circuit 25.
The adding circuit 25 adds the accumulated difference coefficient data DS to the basic coefficient data RD, and sends the addition result to the harmonic amplitude multiplying circuit 11 as the harmonic coefficient data S2 of the harmonic coefficient generating circuit 7.

Here, the gate circuit 45 controls the control signal S1 of the gate control circuit 49.
4 is received via the inverter 50. The gate circuit 45 receives the repeat count data CV of the repeat counter 32 and the frame specifying data FNO of the frame counter 37, and the frame specifying data FNO is "1" (first frame F1.
Is specified), and the repeat count data CV
Is "0" (meaning that a new frame has started)
When, the closing control is performed. Thus, by closing the gate circuit 45 for one cycle of the first tone waveform of the first frame F1, the addition accumulation circuit 25 is prevented from being supplied with the difference accumulation coefficient data DS, and each shift register 46 Clear the data stored in the stage.

In the above configuration, when the key is operated, the differentiating circuit 10
The repetition number counter 32 and the frame counter 37 are reset by the key-on pulse signal KONP obtained through. As a result, the frame designation data FNO becomes the state of designating the first frame F1, and the repeat count data CV becomes zero.

On the other hand, when the frequency number R corresponding to the depressed key is given to the accumulator 3, the sine waveform data S1 of each harmonic component of the 1st to 64th harmonics at the pitch corresponding to this frequency number R The components are sequentially generated from the component generation circuit 4 and sent to the harmonic amplitude multiplication circuit 11.

In addition, the clock signal sent from the clock oscillation circuit 5
The order data n transmitted by the counting operation of the order counter 6 based on t _c is given as an address signal to the basic coefficient memory 21 and the interpolation difference coefficient memory 22, and is applied to each of the 1st to 64th harmonics. Basic coefficient data consisting of harmonic coefficient data Q1 (Fig. 3 (A)) at the start of sound generation
RD is sequentially read from the basic coefficient memory 21 and given to the adder circuit 25, and at the same time, the first-order to 64th bits for the first frame F1
Interpolation difference data for each of the following harmonics (Fig. 4 (A))
The interpolated difference coefficient data DD of is sequentially given to the accumulator 43.

At this time, in the accumulator 43 of the harmonic coefficient generating circuit 7, the gate control circuit 49 causes the repeat count data CV
Is 0 and the frame designation data FN0 is 1, and the gate circuit 45 is controlled to the closed state via the inverter 50. Therefore, the accumulator 43 is the difference accumulation coefficient data.
Controlled so that DS is not sent.

In this way, when the key is pressed, the basic coefficient data RD of the basic coefficient memory 21 is sent to the adding circuit 25 of the arithmetic circuit 24.
Is supplied to the harmonic amplitude multiplication circuit 6 as the harmonic coefficient data S2.

In this state, the order counter 6 generates a calculation interval timing signal t _x each time it counts 64 clock signals t _c of the clock oscillation circuit 5, and the accumulator 3 is based on this timing signal t _x and the accumulator 3 outputs the sampling position of the tone waveform. Is sequentially supplied to the harmonic component generating circuit 4. The harmonic component generating circuit 4 sequentially generates the sine waveform data S1 of the first harmonic component to the 64th harmonic component in a time division manner in each of the 1st to 64th time slots formed by the clock signal t _c . And supplies it to the harmonic amplitude multiplication circuit 11.

On the other hand, from the basic coefficient memory 21, the 1st to 64th order harmonic coefficient data Q1 (FIG. 3 (A)) are sequentially read according to the clock signal t _c, and the harmonic coefficient data S2 is added through the adder circuit 25. Is supplied to the harmonic amplitude multiplication circuit 11 as described above, and from the harmonic amplitude multiplication circuit 11 to the sampling point amplitude values of the 1st to 64th harmonic components of the first period of the tone waveform, A multiplication data output S3 obtained by multiplying each of the second to 64th harmonic coefficient data is obtained.

Eventually, when the accumulator 3 completes the accumulation of one cycle of the tone waveform and sends out the carrier signal CA, the repetition number counter
32 counts and repeat count data CV becomes 0
Change from 1 to 1. At this time, the gate control circuit 49 responds to drop the output to the logic "0", thereby controlling the gate circuit 45 to the open state. Therefore, the interpolation difference coefficient memory
The interpolation difference coefficient data DD of 22 is the gate circuit 42 and the addition circuit 4
4. The difference accumulation coefficient data DS is transmitted through the gate circuit 45. At this time, since the content of the frame designation data FNO for the interpolation difference coefficient memory 22 is 1, the 1st to 64th order interpolation difference data (Q2-Q1) / K ₁ corresponding to the first frame F1 from the interpolation difference coefficient memory 22. Are sequentially read.

Therefore, the adder circuit 25 of the arithmetic circuit 24 has the basic coefficient memory 21
Since the basic coefficient data RD and the cumulative difference coefficient data DS are given, the addition result is sent to the harmonic amplitude multiplication circuit 11 as the harmonic coefficient data S2. At the same time, the harmonic component generating circuit 4 outputs the sine waveform data S1 for each of the first to 64th harmonic components in the second cycle,
The harmonic amplitude multiplication circuit 11 calculates the harmonic coefficient data Q1 (Q2-Q1) / K ₁ minute from the harmonic coefficient data Q1 (FIG. 3 (A)) for each harmonic component in the second cycle. Q2 (3rd
The harmonic coefficient data S2 having the spectrum distribution curve changed so as to approach FIG.

For example, as for the Mth-order harmonic coefficient, as shown in FIG. 8, the content of the harmonic coefficient data S2 changes from L ₁ to (L ₂ −L ₁ ) at the time t ₀₁ when the tone waveform of the first cycle ends. / K Increase by ₁ minute.

Similarly, every time one cycle of the tone waveform is completed,
When the carrier signal CA is given from the accumulator 3 to the repetition number counter 32, the value of the repetition number count data CV increases by one, but the frame counter
Since the frame designation data FNO of 37 does not change, the interpolation difference coefficient memory 22 continues to send the interpolation difference coefficient data of the first frame.

However, when the carrier signal CA is generated, the gate circuit 42 is controlled to be opened by the output of the AND circuit 47 only for one period T _tx of the calculation section timing signal t _x each time.
From interpolation difference coefficient memory 22 to accumulator 43 primary to 64
The interpolation difference data DD for each of the following orders will be input only once. At this time, the accumulator 43, every time the data DD is input, adds the data sequentially sent from the shift register 45 to each time slot and sends it as the difference accumulation coefficient data DS, at the same time,
The shift register 46, the adder circuit 44, the gate circuit 45, and the shift register 46 are cyclically stored.

Thus, the accumulator 43 accumulates the interpolation difference coefficient data DD read from the interpolation difference coefficient memory 22 each time one cycle of the tone waveform is completed.

As a result, in the first frame F1, for example, as shown in FIG.
According to the accumulation operation of, the content of the difference accumulation coefficient data DS is the interpolation difference data (L ₂ −L ₁ ) / K _{1 of 1 at} each time point t ₀₂ , t _03, ... When one cycle of the tone waveform ends. It will go up step by step.

The differential accumulation coefficient data DS rising in this way is added to the basic coefficient data RD in the adder circuit 25 and transmitted as harmonic coefficient data S2. As a result, the timbre of the musical tones generated in the sound system 9 changes continuously in practical use.

Eventually, the count content of the repeat count counter 32 is specified by the repeat count designating circuit 34 as the repeat count K (K ₁ ).
If it matches with, the comparison circuit 33 outputs a match detection output EQ. At this time, the coincidence detection output EQ changes the content of the frame designation data FNO from 1 to 2 by counting the frame counter 37 through the gate circuit 36. Thus, the harmonic coefficient generating circuit 7 finishes the coefficient generating operation of the first frame and enters the next second frame.

At the same time, the coincidence detection output EQ is delayed by one calculation section T _tx in the delay circuit 38, and then the OR circuit 39 resets the repetition number counter 32 to reset the content of the repetition number count data CV to zero.

Here, the interpolation difference coefficient memory 22 stores the frame designation data FN
Since O has changed to 2, the interpolation difference coefficient set as the interpolation difference coefficient data DD corresponding to the second frame F2. Is controlled to read. Also at this time, since the carry signal CA is given from the accumulator 3, the gate circuit 42 is opened for one cycle T _tx of the calculation interval timing signal t _x , and the new interpolation difference coefficient data DD is stored in the accumulator 43.
Entered in. Therefore, when the accumulator 43 enters the second frame F2, the accumulator 43 is in a state of further accumulating the interpolation difference coefficient data DD2 to the accumulation result in the first frame.

Therefore, the harmonic coefficient data S2, for example the M-order harmonic coefficient, as shown in FIG. 8, each time the one period of the sound waveform from NyuTsuta time t ₁ to the second frame ends, the interpolation differential coefficient data _{(L 3 -L 2) / K} 2 will be only going to change. In the case of FIG. 4 (B), the difference data L ₃ −L ₂
Has a negative polarity, the difference accumulation coefficient data DS is decreased by one step from the accumulation result of the first frame by the interpolation difference coefficient data DD.

In such an operation, since the content of the repeat number designating data K of the repeat number designating circuit 34 is switched to the value K ₂ for the second frame, the repeat number count data CV of the repeat number counter 32 is set to this value K 2. Continue until ₂ is matched. Therefore, the harmonic coefficient data S2 of each order for the second frame F2 output from the harmonic coefficient generating circuit 7
Values of the musical tones generated from the sound system 9 are different from those of the first frame F1 by the step values different from those of the first frame F1. Can be changed in any way.

Hereinafter, the same operation is repeated for the third frame F3 ... Nth frame FN, and when the Nth frame NF ends at time t _N in FIG. 2, the contents of the frame designation data FNO of the frame counter 37 ( N + 1), and the final frame detection circuit 40 detects this. This detection output FD closes the gate circuit 36, so that the frame counter 37 can no longer perform the count operation and the content of the frame designation data FNO is fixed.

At this time, the interpolation difference coefficient memory 22 stores the interpolation difference coefficient data.
Numerical data 0 is output as DD. Therefore, the accumulator 43 does not substantially perform a new accumulation operation, and consequently, in the (N + 1) th frame, the accumulation result in the final cycle of the Nth frame is stored and held as it is.

Therefore, for example, for the M-th order harmonic coefficient, as shown in FIG. 8, the result of accumulating the interpolated difference data (L _N −L _N−1 ) / K _N at the end in the Nth frame FN is obtained by the accumulator 43 The value L _N to be maintained is maintained even in the (N + 1) th frame F (N + 1) after the time t _N.

As a result, the tone color of the tone generated from the sound system 9 is maintained in the same tone color until the key is released.

As described above, according to the configuration of FIG. 1, since the amplitude of each harmonic component included in the musical tone signal can be changed for each frame, the amplitude can be continuously changed within the same frame. It is possible to generate from the sound system 9 a musical tone that is similar to the musical tone of a musical instrument.
Therefore, the basic coefficient memory 21 needs to store only one set of the fundamental harmonic coefficient data Q1 (1st to 64th) of the 1st to 64th order, and the other stored data is each frame. Since it is only necessary to store a set of interpolation difference data having a small change width in the interpolation difference coefficient memory 22, it is possible to easily reduce the memory capacity of the harmonic coefficient generating circuit 7 as a whole.

Second Embodiment FIG. 9 shows another embodiment of the present invention, in which the number of frames and the number of repetitions in each frame can be set for each order. Thus, regarding the order in which the change of the harmonic coefficient is complicated, the period from the generation of the tone signal to the end thereof is divided into a number of frames, and the length of each frame is shortened. On the other hand, regarding the order in which the change of the harmonic coefficient changes relatively monotonically, the length of each frame is increased by dividing it into a small number of frames.

In the case of this embodiment, the change in the harmonic coefficient is made by selecting the number of repetitions K _{1 to} K _N described above with reference to FIG. 5 to different values as needed for each order, and thus interpolating difference data in each frame are mutually different. Set so that they are different.

In FIG. 9 in which parts corresponding to those in FIG. 1 are designated by the same reference numerals, the repetition number counter 32 has a shift register 55 of 64 stages. The shift register 55 shifts according to the clock signal t _c, and delays the input data by the time T _{tx corresponding to} one cycle of the calculation interval timing signal t _x and outputs it. The output of the shift register 55 is added to the “+1” addition input S15 in the adder circuit 56, and the addition result is returned to the input terminal of the shift register 55 through the gate circuit 57. As a result, every time the shift register 55 outputs the 1st to 64th repeat count data to the input end of the shift register 55, data obtained by adding "+1" to the data is obtained. The input data to the shift register 55 is given to the comparison circuit 33 as the repeat count data CV. "+
The 1 ”addition input S15 is obtained as a signal which is generated by differentiating the carrier signal CA in the differentiating circuit 60 during one period T _tx of the timing signal t _x .

On the other hand, the repeat count designating circuit 34 stores repeat count designating data corresponding to the first to 64th harmonics in advance,
This data can be designated and read by the order data n of the order counter 6.

Therefore, the comparison circuit 33 compares the repeat count data CV with the repeat count designation data K at each time slot corresponding to each of the first to 64th harmonics.

Therefore, the coincidence detection output EQ is obtained from the comparison circuit 33 for each time slot corresponding to each order, and this is the time T _tx for one cycle of the calculation section timing signal t _{x in} the delay circuit 37.
After being delayed by only, it is given to the inverter 59 via the OR circuit 58, and its output is given to the enable terminal of the gate circuit 57. As a result, at the time slot where the coincidence detection output EQ is obtained, the gate circuit 57 is closed to reset the data of the order corresponding to the time slot of the shift register 55 to 0.

In addition to this, the enable terminal of the gate circuit 57 is supplied with the inverted key-on pulse signal KONP through the OR circuit 58 and the inverter 59, and when any key is operated by this, one cycle of the calculation interval timing signal t _x . Interval T _tx
During this period, the gate circuit 57 is closed to reset all stages of the shift register 55 to 0.

On the other hand, the frame counter 37 has a shift register 61, a “+1” addition circuit 62,
It has a gate circuit 63, and the coincidence detection output EQ of the comparison circuit 33 is given through the gate circuit 36 as the “+1” addition input of the addition circuit 62. The key-on pulse signal KONP is inverted and given to the enable terminal of the gate circuit 63 by the inverter 64, and when any key is operated, the gate circuit 63 is supplied for one cycle T _tx of the calculation interval timing signal t _x. By performing the closing operation, all the 1st to 64th order frame designation data FNO of the shift register 61 are reset to 0. After that, every time the coincidence detection output EQ is obtained in the comparison circuit 33, an addition circuit
Numerical data "+1" is added to the data obtained at the output terminal of the shift register 61.

Here, since the comparison circuit 33 sends out the coincidence detection output EQ for each time slot corresponding to the 1st to 64th order,
Frame designation data FN from the 1st to the 64th of the shift register 61
The contents of O are changed independently for each order. Therefore, the interpolation difference coefficient data DD read from the interpolation difference coefficient memory 22 also relates to different frames for each order.

Further, the final frame detection circuit 40 receives the order data n of the order counter 6 and detects the data representing the final frame stored in advance for each order and the frame designation data FNO at the time slot corresponding to each order. To do. As a result, when the final frame detection signal FD is obtained in the time slot of the order that reaches the final frame of the frame designation data FNO, the gate circuit 36 is closed only during the time slot to close the time slot. Corresponding degree frame designation data FN
Control so that the "+1" addition operation for O cannot be executed.

In the above configuration, when any key is operated,
The gate circuit 57 of the repeat counter 32 is closed and the gate circuit 63 of the frame counter 37 is closed by the key-on pulse signal KONP generated at this time. Therefore, the repeat counter 32 is the accumulator 3
Each time the carrier signal CA is generated from the differential circuit 60, the data of the time slot corresponding to each order of the shift register 55 is given by the "+1" input S15 given for one period T _tx of the calculation interval timing signal t _x. The addition operation is repeated with respect to the
The content of becomes larger by one for each period of the musical tone waveform.

On the other hand, when the gate circuit 63 of the frame counter 37 is closed by the key-on pulse signal KONP, the contents of each stage of the shift register 61 are cleared to zero. Therefore, the frame counter 37 sends the frame designation data FNO for each order having the first frame F1 as the content to the repetition number designation circuit 34.

At this time, the repeat count designating circuit 34 sends the repeat count designating data K read according to the order data n designated for each time slot to the comparing circuit 33. Thus, the comparison circuit 33 detects whether or not the number of repetitions set for the first frame F1 for each order in each time slot and the content of the number-of-repetitions counter 32 match. Eventually, when the coincidence detection output EQ is obtained at any of the time slots, this is given to the adder circuit 62 of the frame counter 37 as "+1" addition data, and the content of the shift register 61 corresponding to the order of the time slot is set to a numerical value. Add 1

At the same time, the coincidence detection output EQ of the time slot is given to the gate circuit 57 through the delay circuit 38, the OR circuit 58, and the inverter 59, thereby clearing the contents of the register 55 corresponding to the order of the time slot to zero. Therefore, the repeat counter 32 starts a new counting operation for the order.

Similarly, when the coincidence detection signal EQ is obtained for each time slot corresponding to each order, the content of the register 61 of the frame counter 37 is incremented by 1 and the repetition number counter 32 repeats for the order of the time slot. Clear the count data to 0 and start a new count. As a result, the content of the frame designation data FNO is incremented by 1 for each order, the second frame F2 is designated to the repeat count designating circuit 34, and the repeat count of each order in the second frame F2 is repeated. counter
Start counting at 32.

This operation is repeated thereafter, and when one of the frame designating data FNO of each order finally becomes the final frame, the final frame detection circuit 40 detects this and closes the gate circuit 36 by the final frame detection signal FD. And let
The gate circuit 42 of the arithmetic circuit 24 is closed. As a result, the frame counter 37 controls so that the order is not incremented by 1 thereafter. At the same time, the accumulator 43 is controlled not to perform new accumulation in the same manner, so that the difference accumulation coefficient data of the same value can be obtained thereafter.
Send DS.

This operation is performed by the frame designation data FNO corresponding to each order.
Is performed for each relevant order each time the content reaches the final frame, thus ending the generation of the harmonic coefficient data S2 for all the 1st to 64th orders.

As described above, according to the configuration of FIG. 9, it is possible to arbitrarily set the number of repetitions of each frame for each of the 1st to 64th orders, and the number of frames is also independent of each other. Since it can be set to, the change of the tone color from the time of the generation of the musical sound generated in the sound system 9 to the end thereof can be brought closer to the sound of the natural musical instrument.

Incidentally, in natural musical instruments, higher-order harmonic components tend to change more rapidly, and the amplitude of higher-order harmonic components tends to be larger when a musical sound rises. However, according to the configuration of FIG. It is possible to easily realize the phenomenon in which the timbre changes based on the change in the harmonic component for each order in each frame.

Third Embodiment FIG. 10 shows a third embodiment. In the embodiment shown in FIGS. 1 and 9, the interpolation difference coefficient obtained by dividing the difference between the harmonic coefficients of adjacent frames by the number of repetitions in the frame is stored in the interpolation difference coefficient memory 22 for each order. In the case of FIG. 10, instead of this, a difference coefficient memory 67 for directly storing the difference between the harmonic coefficients in adjacent frames for each order is provided.

The difference coefficient data DF1 read from the difference coefficient memory 67 is given to the multiplication circuit 70 through the gate circuit 69 which receives the final frame detection signal FD at the enable terminal through the inverter 68. The multiplication circuit 70 multiplies the data DF1 by the multiplication coefficient data MC given from the multiplication coefficient generation circuit 71, and gives the multiplication result to the addition circuit 72 as a first addition input.

The repeat count data CV changes from 0 to K CV / K at each end of one cycle of the tone waveform in each frame.
(K-1) Since it increases in increments, the multiplication coefficient data MC
(MC = CV / (K-1) accordingly increases from 0 to 1. The difference coefficient data MSX obtained at the output end of the multiplication circuit 70 is changed from 0 to 0 for each frame. It will change to the difference coefficient data DF1.

On the other hand, the basic coefficient data RD of the basic coefficient memory 21 is added as the second addition input through the gate circuit 73 to the addition circuit 72.
Given to. A key-on pulse signal KONP is given to the enable terminal of the gate circuit 73, which causes the gate circuit 73 to open for the time T _tx of one cycle of the first timing signal t _x after any key is operated. The basic coefficient data RD is given to the adding circuit 72 as a second addition input.

The addition output of the adding circuit 72 is sent to the harmonic amplitude multiplying circuit 11 as the harmonic coefficient data S2, and this harmonic coefficient data S2 is given to the A input terminal of the selector 74. Selector 74
The selection output of is input to the shift register 75 having a 64-stage configuration. The shift register 75 shifts according to the clock signal t _c , and thus the data of each order sequentially arriving at the input end of the shift register 75 is one cycle T _{tx of the} timing signal t _x.
It is delayed by an amount, and is given as the storage data MR to the adder circuit 72 through the gate circuit 76 as the third addition input and also to the B input terminal of the selector 74.

The coincidence detection signal EQ and the key-on pulse signal KONP are given to the selector 74 as the A input selection signal through the OR circuit 77, and the output of the OR circuit 77 is inverted by the inverter 78 as the B input selection signal.

Thus, when one of the keys is operated, the selector 74 selects the harmonic coefficient data S2 (basic coefficient data RD) and fetches it in the shift register 75, and then the shift register 75.
The output of the above is cyclically stored by feeding back to the input end of the shift register 75 through the selector 74, and the harmonic coefficient data S2 is again stored by the coincidence detection signal EQ generated at the end of each frame. Is taken into the shift register 75 through the selector 74, and then this data is cyclically stored until the next coincidence detection signal EQ is obtained.

A key-on pulse signal is applied to the enable terminal of the gate circuit 76.
KONP is given through the inverter 79, and the gate circuit 76 is closed only when the key-on pulse signal KONP arrives.

In the configuration of FIG. 10, when any key is operated and a key-on pulse KONP is generated, the gate circuit 73 is opened and the basic coefficient data RD of the basic coefficient memory 21 is added to the addition circuit 72 for each time slot (each order). Entered in. At this time, the gate circuit 76 is controlled to be closed by the key-on pulse signal KONP, and the output of the shift register 75 is not given to the adding circuit 72. On the other hand, the difference coefficient data DF1 of the difference coefficient memory 67 is multiplied by the multiplication coefficient data MC in the multiplication circuit 70 through the gate circuit 69 and weighted, and is given to the addition circuit 72 as difference coefficient data MSX. However, since the value of the repeat count data CV is 0 at the initial stage, the difference coefficient data MSX also becomes 0, and the adder circuit 72 sends the basic coefficient data RD as it is as the harmonic coefficient data S2. In this state, the selector 74 selects the data at the B input end, that is, the data MR at the output end of the shift register 75, and feeds it back to the input of the shift register 75, and thus the shift register 75 enters a state in which the basic coefficient data RD is cyclically stored. .

In this initial stage, the selector 74 selects the A input by the key-on pulse signal KONP, so that the harmonic coefficient data S2 is sequentially taken into the shift register 75 through the selector 74.

Eventually, when the rising section of the key-on pulse signal KONP passes, the gate circuit 73 is closed and the basic coefficient data RD is not input to the adder circuit 72, and at the same time, the gate circuit 76 is opened via the inverter 79. The data MR of the shift register 75 is input to the adder circuit 72 through the gate circuit 76. As a result, the harmonic coefficient data S2 consisting of the 1st to 64th harmonic coefficients determined based on the basic coefficient data RD
Is sent.

Here, the data MR input from the shift register 75 to the adder circuit 72 is the data one calculation section T _tx before, that is, the basic coefficient data RD, and the adder circuit 72 adds the differential coefficient data MSX to this basic coefficient data RD. It becomes a state. in this case,
Since the repeat count counter 32 counts, the repeat count data CV changes from 0 to 1. Therefore, the value of the multiplication coefficient data MC changes to 1 / (K-1), and this difference coefficient data MSX Is increased by one step. This difference coefficient data MSX is stored data MR (MR = RD)
Thus, the harmonic coefficient data S2 is changed by the change of the difference coefficient data MSX.

After that, the multiplication coefficient data MC increases by one step as the repetition count data CV increases by one each time one cycle of the musical tone waveform elapses. Therefore, the difference coefficient data MSX responds to this. Then change by 1 / (K-1). Therefore, the harmonic coefficient data S2 is the basic coefficient data RD.
Value (FIG. 3 (A)) approaches the first value (FIG. 3 (B)) of the second frame F2.

Eventually, when a musical tone waveform is generated for the number K ₁ of repetitions of the first frame F1 and the coincidence detection signal EQ is obtained in the comparison circuit 33, the selector 74 selects the A input by the coincidence detection signal EQ. The last harmonic coefficient data S2 of one frame F1 is taken into the shift register 75. On the other hand, when the frame designation data FNO is increased by 1, the difference coefficient memory 67 outputs new difference coefficient data DF1 for the second frame F2. Therefore, the arithmetic circuit 24 adds the difference coefficient data MSX obtained based on the change of the multiplication coefficient data MC to the last harmonic coefficient data S2 of the first frame F1 in the second frame F2 to obtain the higher harmonic wave. The coefficient data S2 will be transmitted.

In the same manner, the arithmetic circuit 24 executes the arithmetic operations for the third ... Nth frame F3 ... FN, and thus, FIGS.
It is possible to obtain harmonic coefficient data that continuously changes based on the interpolation calculation described above with reference to the drawings, and thereby it is possible to form a musical tone exhibiting a tone color change close to that of a natural musical instrument.

Note that, in FIG. 10, the case where the multiplication coefficient data MC is obtained based on the arithmetic expression of CV / (K-1) as the multiplication coefficient generating circuit 71 is described, but this arithmetic expression is changed as necessary. be able to.

Further, when forming the multiplication coefficient data MC in the multiplication coefficient generation circuit 71, the multiplication coefficient data is stored in the multiplication coefficient memory forming the lookup table, and this is stored by the repetition number count data CV and the repetition number designation data K. It may be read.

Fourth Embodiment The arithmetic circuit 24 having the configuration shown in FIG. 11 can be applied. In this case, the difference coefficient memory 81 uses the first to Nth frames F1.
The difference data between the harmonic coefficient in FN to FN and a predetermined basic coefficient are stored in advance in association with the first to Nth frames. Then, according to the frame designation data FNO, 1
When one frame is designated, the difference coefficient data DF2 of the frame and the difference coefficient data DF3 of the frame number which is larger by 1 than the frame number of the frame are read at the same time. The first difference coefficient data DF2 is first added to the direct addition circuit 82.
Given as the addition input of.

On the other hand, the first and second difference coefficient data DF2 and D
F3 is subtracted in the subtraction circuit 83, and the subtraction output is multiplied by the multiplication coefficient data MC generated in the multiplication coefficient generation circuit 85. The multiplication coefficient generation circuit 85 may have the same configuration as the multiplication coefficient generation circuit 71 described above with reference to FIG. Therefore, the difference coefficient data DF is output to the output terminal of the multiplication circuit 84.
By multiplying the subtraction value of 3 and DF2 by the multiplication coefficient CV / (K-1), the interpolating difference data DSY which changes by one step each time the repetition count data CV changes is obtained, and this is the gate circuit 86. Is given as a second addition input to the addition circuit 82 through.

Since the final frame detection signal FD is inverted by the inverter 87 and applied to the gate circuit 86 as an enable signal, the differential interpolation data DSY is not applied to the addition circuit 82 when the final frame is detected. There is.

The adder circuit 82 receives the basic coefficient data RD of the basic coefficient memory 21 as a third addition input, and outputs the addition output as harmonic coefficient data S2.

In the configuration of FIG. 11, the arithmetic operation circuit 83 determines, for each frame, the difference coefficient data DF2 of the frame and the succeeding frame.
By obtaining the difference data DF3-DF2 of DF3 and DF3, the range of the difference coefficient to be changed during the frame is obtained,
By multiplying this change range by the multiplication coefficient data MC that changes by one step according to the repeat count data CV, the difference interpolation data DSY indicating the change amount from the difference coefficient data DF2 to the difference coefficient data DF3 is obtained. Will be obtained.

This changing interpolated difference data DSY is added to the difference coefficient data DF2 and the basic coefficient data RD in the adder circuit 82, so that the resulting harmonic coefficient data S2 in the frame is from the first value of the frame to the next value. Will have a content that varies continuously with the first value of the frame based on the repetition factor K.

Also in this case, the gate circuit 86 is closed by the final frame detection signal FD, so that after the final frame has elapsed, the difference coefficient data DF about the final frame.
The harmonic coefficient data S2 determined by the sum of 2 and the basic coefficient data RD will be continuously output.

As described above, also with the configuration of FIG. 11, it is possible to obtain the harmonic coefficient data S2 of each order that changes at a different rate of change for each frame. In this way, the basic coefficient memory 21 and the difference coefficient memory 81 need only be provided as the means for storing the coefficient data. In particular, as the data of the difference coefficient memory 81, it is sufficient to store the data of a sufficiently small value. It is possible to reduce the memory capacity.

In FIG. 11, if the output data of the subtraction circuit 83 is stored in the memory 81 for each frame in advance, the subtraction circuit 83 becomes unnecessary.

Fifth Embodiment FIG. 12 shows another embodiment of the arithmetic circuit 24. First
In FIG. 12, the memory has the same basic coefficient memory 21 and interpolation difference coefficient memory 22 as in the case of the embodiment of FIG. 1, and the interpolation difference coefficient data DD is the same as in the case of FIG.
It is given as a first addition input to the addition circuit 91 through 42.

Further, the basic coefficient data RD of the basic coefficient memory 21 is given to the adder circuit 91 as a second addition input through the gate circuit 92.

In the case of this embodiment, the harmonic coefficient data S2 obtained at the addition output end of the addition circuit 91 is a shift register having a 64-stage configuration.
While being input to 93, its output is given to the adding circuit 91 as a third addition input through the gate circuit 94.

The gate circuit 92 is opened by the key-on pulse signal KONP and supplies the basic coefficient data RD to the adder circuit 91 for one calculation period T _tx . The key-on pulse signal KONP is inverted and given to the gate circuit 94 by the inverter 95. As a result, the gate circuit 94 is opened in a section other than the rising section of the key-on pulse KONP, and the data of the shift register 93 is given to the adding circuit 91.

In the configuration of FIG. 12, when any key is operated, the key-on pulse signal KONP causes the basic coefficient memory 21
The basic coefficient data RD is input to the adder circuit 91, which is output as the harmonic coefficient data S2 and is sequentially input to the shift register 93. Eventually key-on pulse KONP
When the voltage rises, the gate circuit 92 is controlled to be closed and the gate circuit 94 is controlled to be opened, whereby the data stored in the shift register 93, that is, the basic coefficient data RD, is given to the addition circuit 91. At this time, the adder circuit 91 sends the data coming from the shift register 93 as the harmonic coefficient data S2, and takes it in the shift register 93 again.
This operation is repeated for one cycle of the tone waveform, and after one cycle, the accumulator 3 carries the carrier signal CA.
Will be maintained until.

Eventually, when the carrier signal CA arrives at the differentiating circuit 48, 1
The gate circuit 42 is controlled to be opened by the AND circuit 47 during the calculation section T _tx . Therefore, the difference coefficient data DD of the first frame F1 read from the interpolation difference memory 22 is the gate circuit.
It is given to the adder circuit 91 via 42, added with the basic coefficient data RD stored in the shift register 93, and sent out as the harmonic coefficient data S2.
Will be sequentially captured. Eventually, when one calculation interval T _tx passes,
The gate circuit 42 is controlled to be closed, and the data taken into the shift register 93 is circularly stored through the loop of the gate circuit 94, the adder circuit 91, and the shift register 93.

Hereinafter, the gate circuit 42 is controlled by the carrier signal CA that arrives every time one period of the tone waveform of the first frame F1 passes.
The interpolation difference memory 22 supplies the interpolation difference coefficient data DD to the adder circuit 91 every time it is controlled to open, and this is added to the data stored in the shift register 93. As a result, the content of the harmonic coefficient data S2 changes by the interpolation difference coefficient data DD of the interpolation difference memory 22.

Eventually, when the coincidence detection signal EQ is obtained from the comparison circuit 33 with the end of the first frame F1 and the frame counter 36 performs the counting operation (FIG. 1), the interpolation difference coefficient output from the interpolation difference memory 22. The data DD is switched to the value stored for the second frame F2, and the formation operation of the harmonic coefficient data S2 for the second frame F2 is performed based on this data.

Similarly, every time the frame counter 37 counts and the frame designation data FNO changes, the interpolation difference coefficient data DD sent from the interpolation difference coefficient memory 22 is changed and the harmonic coefficient data for a new frame is changed. S2
When the last frame is reached, the final frame detection circuit 39 detects this and the gate circuit 42 is controlled to be closed. Therefore, the content of the harmonic coefficient data S2 obtained at the output end of the adder circuit 91 is only the data stored in the shift register 93, and thus the harmonic coefficient data calculated for the final frame thereafter.
S2 is continuously output.

Therefore, even with the configuration of FIG. 12, the harmonic coefficient data S2 for each order can be continuously changed for each frame in the same manner as in the above-described embodiments. Need only store one set of basic harmonic coefficient data and one set of interpolation difference coefficient data for each frame. Especially, since the value of the interpolation difference coefficient data is small, the total memory capacity is small. Can be converted.

Modifications The same effects as in the above case can be obtained even if the following modifications are added to the above-described embodiment.

(1) In the above embodiment, the case where the present invention is applied to the single-tone electronic musical instrument is described, but it may be applied to the multi-tone electronic musical instrument. In this case, the various circuits described above may be arranged in parallel for a plurality of sounds and configured to perform simultaneous processing,
Alternatively, a plurality of sounds may be processed in a time division manner.

(2) In the case of the above-described embodiment, the corresponding time slot is provided assuming that there are harmonic components for all orders, but a tone signal having only some higher order harmonic components is generated. The present invention can also be applied to cases.
In this case, for example, the technique disclosed in JP-A-54-140523 may be used.

(3) In the above embodiment, the frequency number R is used to generate and combine harmonics of each order, but other harmonic combining methods may be used. For example, instead of a frequency number, note counters corresponding to keys are counted by a counter to generate data corresponding to the cumulative force qR, and harmonic components to be combined are generated based on this data. May be.

(4) In the above-mentioned embodiment, the frequencies of the respective harmonic components are set in an integral multiple relationship to generate a harmonic musical tone, but instead of this, it is disclosed in, for example, Japanese Patent Publication No. 53-40527. As described above, the anharmonic musical sound may be generated by setting the frequency of the desired harmonic component so as to deviate from the integral multiple relationship (set to the non-integer multiple relationship).

(5) In the above-described embodiment, the switching of each frame is performed in units of the tone waveform period, so that the time of each frame is changed according to the pitch of the key pressed. However, the present invention is not limited to this, and for example, a timer circuit may be provided to control the frame switching in units of time regardless of the tone waveform period. In this case, for example, in the frame data generating circuit 31, a predetermined clock signal may be applied to the gate circuit 36.

(6) In each of the above-described embodiments, the shift register 46 is used to store the difference accumulation coefficient in the accumulator 43 (FIGS. 1 and 9), and the repeat count data is stored in the repeat count counter 32. For this purpose, the shift register 55 is used (FIG. 9), the frame counter 37 uses the shift register 61 for storing the frame number (FIG. 9), and the arithmetic circuit 24 shifts for storing the harmonic coefficient data S2. Registers 75 (Fig. 10) and 93 (Fig.
Although FIG. 12) is used, RAM or other storage means may be used instead of these shift registers.

(7) In the above-described configuration, dedicated hardware is provided to execute operations such as addition, accumulation, multiplication, etc. and control of these operations, but processing is performed by a micro computer or the like. You may do it.

(8) In the above-described embodiment, the case where the musical tone waveform formation calculation by harmonic synthesis is executed in real time has been described. However, the musical tone waveform formation (harmonic synthesis) calculation result is once written in the memory, and then the musical tone frequency is changed. Correspondingly, the memory may be read out and the processing may be performed in a non-real-time system in which the musical tone waveform formation calculation is executed a plurality of times in order to change the tone color during one sound generation. As the configuration of this non-real time system, the configuration disclosed in Japanese Patent Laid-Open No. 48-76520 can be used.

(9) In the above-described embodiment, the generation calculation of each harmonic coefficient is performed in synchronization with the generation timing of each harmonic component. Instead of this, the calculation calculation of each harmonic coefficient is performed, for example, in Japanese Patent Publication No. Sho. As shown in Japanese Patent Laid-Open No. 58-3238, it may be performed at a low speed timing that is asynchronous with the timing of generation of each harmonic component.

(10) In the above embodiment, in the arithmetic circuit 24,
Although the interpolation calculation of the harmonic coefficient is performed for each cycle of the tone waveform, the invention is not limited to this, and the interpolation calculation may be performed once for a plurality of cycles, for example, two cycles or four cycles.
The same effect as the above case can be obtained.

(11) In the basic coefficient memory 21, the interpolation difference coefficient memory 22 (FIG. 1, FIG. 9 and FIG. 12) and the difference coefficient memories 67 (FIG. 10) and 81 (FIG. 11) of the above embodiment. The data to be stored is not limited to PCM data, but DPCM, ADPCM, DM, AD
Data of various waveform coding methods such as M and APCM may be used.

(12) In the above embodiment, the case where the repetition number designating circuit 34 is provided in the frame data generating circuit 31 so that the repetition number can be set for each frame has been described. It may be fixed to a constant value common to all frames. In this case, in the frame data generation circuit 31, the carrier signal CA may be divided and added to the gate circuit 36.

(13) In the above embodiment, the harmonic synthesis operation is performed in a time-division manner, but the present invention is not limited to this.
As shown in Japanese Patent Publication No. 53-42104, generation of each harmonic component and generation of each harmonic coefficient may be performed in parallel for each order.

(14) In the above embodiment, the harmonic component generation circuit 4
As described above, the case where a sine wave is generated has been described, but the present invention is not limited to this, and other waveforms such as a rectangular wave and a triangular wave may be generated to perform harmonic synthesis.

(15) In the above-described embodiment, the present invention is applied to the case where a musical tone having a pitch corresponding to the operated key is generated, but the present invention is not limited to this and is also applied to the case where a rhythm sound is generated. You can

(16) In the above-mentioned embodiment, in addition to the effect of changing the timbre from the time the musical sound is generated until it disappears,
In addition, for example, when adding timbre changes such as key scaling, touch response, and controls, an arithmetic circuit
In 24, a multiplier is provided on the output side of the accumulated difference data, and after the accumulated accumulated data is given a predetermined weight according to the key scaling or the touch response by this multiplier,
It may be configured to be added to the fundamental harmonic coefficient. By doing so, it is possible to easily generate a timbre change regarding the effect to be added as needed without deteriorating the image of the original sound mainly determined by the fundamental harmonic coefficient.

(17) In the case of the embodiment shown in FIG. 10, the coefficient data of the difference corresponding to the difference between the amplitude coefficient to be generated at the beginning of the frame and the basic coefficient data is calculated for each frame as the interpolation coefficient storage means. Although each of the frames is stored for each frame and the corresponding coefficient data of the difference is read out in accordance with the output of the frame designating means, instead of this, each frame is processed in the same manner as described above with reference to FIG. The coefficient data of the difference corresponding to the difference between the amplitude coefficient to be generated at the beginning of the frame and the amplitude coefficient to be generated at the beginning of the next frame is stored for each order, and the calculating means is The coefficient data of this difference is multiplied by a weighting coefficient that changes with time in each frame for each order, and at the end of each frame. The data representing the multiplication result is temporarily stored for each degree, and the temporarily stored data,
The multiplication result and the basic coefficient data are added for each degree to obtain the amplitude coefficient for each degree. Even in this case, the same effect as in the case of FIG. 10 can be obtained.

〔The invention's effect〕

As described above, according to the present invention, in the harmonic synthesis type musical tone signal generator, the amplitude level of each order component constituting the musical tone can be independently changed with time, so that the timbre changes with time. It is possible to generate a high quality musical sound that changes in a complicated manner.

Further, in order to obtain the amplitude coefficient of each order that sequentially changes with the passage of time for setting the amplitude level of each order component, “a set of basic coefficient data (representing the initial value of the amplitude coefficient of each order”) And "difference coefficient data (corresponding to the difference in amplitude coefficient between adjacent frames for each order in the case of the first invention, and the amplitude coefficient to be generated in each frame for each order in the case of the second invention) Since it suffices to store "(corresponding to the difference from the basic coefficient)", the memory capacity can be remarkably reduced as compared with the conventional one.

Furthermore, since the amplitude coefficient of each order that changes over time is calculated based on the above basic coefficient data, the timbre can be changed over time without spoiling the image of the basic timbre based on this basic coefficient data. Can be subtly changed.

Particularly, in the first aspect, since the frame division is set for each order, the amplitude coefficient of each order can be changed with time at a speed corresponding to the order, and the tone color of the musical sound can be changed with time in a complicated manner. be able to.

Further, in the second aspect of the invention, since the data regarding the difference between the amplitude coefficient to be generated and the basic coefficient is stored for each frame, the tone color is changed to the basic tone color (corresponding to the basic coefficient) in each frame. The difference may be obtained according to how much the tone color is changed, and the correspondence between the tone color of each frame and the data regarding the difference to be stored is easy to understand and the data setting becomes easy. When it is desired to change the timbre of only a certain frame, only the difference coefficient data regarding the frame needs to be changed, and thus the timbre of the frame can be easily changed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment when the tone signal generator according to the present invention is used in a single-tone electronic musical instrument, FIG. 2 is a signal waveform diagram showing a tone waveform to be generated, and FIG. Curve diagram showing the spectral distribution curve of the power harmonic coefficient,
FIG. 4 is a curve diagram showing the spectrum distribution curve of the difference data to be calculated, FIG. 5 is a table showing the relationship between the number of repetitions and the interpolation difference coefficient in each frame of FIG. 2, and FIG. 6 is a clock signal t _c . FIG. 7 is a signal waveform diagram showing the relationship with the calculation interval timing signal t _x , FIG. 7 is a signal waveform diagram showing the relationship between the key-on signal KON and the key-on pulse signal KONP, and FIG.
Waveform diagrams showing an example of the harmonic coefficients generated in the harmonic coefficient generating circuit 7 of FIG. 9, FIG. 10, FIG. 11, FIG.
Each of the drawings is a block diagram showing a second embodiment, a third embodiment, a fourth embodiment and a fifth embodiment of the tone signal generator according to the present invention. 4 ... Harmonic component generation circuit, 7 ... Harmonic coefficient generation circuit, 21 ... Basic coefficient memory, 22 ... Interpolation difference coefficient memory, 24 ... Arithmetic circuit, 31 ... Frame data generation circuit,
67, 81 ... Difference coefficient memory.

Claims (7)

[Claims] 1. A method in which each order component corresponding to a fundamental wave and its harmonics constituting a musical tone is weighted by an amplitude coefficient which sequentially changes with the passage of time and then they are synthesized. In a musical tone signal generator for generating a musical tone signal, (a) the musical tone signal to be generated is divided into a plurality of frames independently for each degree, and each frame for each degree is generated from the start of the musical tone signal generation. Frame designating means for sequentially designating as time passes, (b) basic coefficient storing means for storing basic coefficient data representing the initial value of the amplitude coefficient for each order, and (c) the basic coefficient data for each frame. The difference coefficient data corresponding to the difference between the amplitude coefficient to be generated at the beginning of a frame and the amplitude coefficient to be generated at the beginning of the next frame is stored for each order, Interpolation coefficient storage means for reading the corresponding coefficient data of the difference in accordance with the output of the frame designation means, and (d) from the basic coefficient storage means each time the frame designation means sequentially designates each frame. Arithmetic means for arithmetically outputting an amplitude coefficient at each time point of the designated frame based on the read basic coefficient data and the difference coefficient data read from the interpolation coefficient storage means. Music signal generator. 2. The interpolation coefficient storage means stores, as coefficient data of the difference, a value obtained by dividing the difference for each frame by the number of repetitions of the interpolation calculation in the frame, and the calculation means stores the difference data. The musical tone according to claim 1, wherein coefficient data is accumulated for each degree, and the accumulated result is added to the basic coefficient data for each degree to obtain an amplitude coefficient for each degree. Signal generator. 3. The interpolation coefficient storage means stores the difference for each frame as coefficient data of the difference, and the arithmetic means changes with time in each frame with respect to the coefficient data of the difference. The weighting coefficient is multiplied for each degree, and data representing the multiplication result at the end of each frame is temporarily stored for each degree.
The amplitude coefficient for each degree is obtained by adding the temporarily stored data, the multiplication result, and the basic coefficient data for each degree.
The musical tone signal generator described in the paragraph. 4. A weight component is added to each order component corresponding to a fundamental wave and its harmonics constituting a musical tone by an amplitude coefficient that sequentially changes with the passage of time, and then they are synthesized. In a musical tone signal generator for generating a musical tone signal, (a) frame designating means for dividing the musical tone signal to be generated into a plurality of frames and sequentially designating each frame according to the passage of time from the start of the musical tone signal generation. (B) basic coefficient storage means for storing basic coefficient data representing a predetermined value for each order, and (c) for each of the frames, the amplitude coefficient and the basic coefficient data to be generated at the beginning of the frame. Interpolation coefficient storage means for storing difference coefficient data corresponding to the difference for each degree and reading out the corresponding difference coefficient data according to the output of the frame designating means. (D) Based on the basic coefficient data read from the basic coefficient storage means and the difference coefficient data read from the interpolation coefficient storage means each time the frame designating means sequentially designates each frame. A musical sound signal generating device comprising: a calculating unit that calculates and outputs an amplitude coefficient at each time point of the designated frame. 5. The interpolation coefficient storage means stores the difference for each frame as coefficient data of the difference, and simultaneously calculates the difference coefficient data of the frame designated by the frame designating means and the next frame. The data is read out and output as first and second difference coefficient data, and the arithmetic means subtracts the first and second difference coefficient data, and a time elapses in each frame with respect to the subtraction result. A weighting coefficient that changes with is multiplied, and the multiplication result, the first difference coefficient data, and the basic coefficient data are added for each order to obtain an amplitude coefficient for each order. The musical sound signal generating device according to claim 4. 6. The musical tone signal generating apparatus according to claim 5, wherein the arithmetic means generates the weighting coefficient that sequentially changes from “0” to “1” in decimal in each frame. . 7. The frame division is performed independently for each degree, and the frame designation means designates the frame for each degree.
7. The tone signal generator according to any one of items 1 to 6.