JPH0691447B2 - Integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an integrated circuit, and more particularly to an integrated circuit having an output current limiting circuit of an output MOS transistor.

[Conventional technology]

Circuits that limit the output current when the load abnormally shorts in the integrated circuit have been performed in the bipolar integrated circuit, but in that case, the output bipolar transistor always has a base-emitter voltage drop of about 0.7V, so output to the load. When a large current is required as the current, heat generation of the transistor has been a problem.

Recently, it has been attempted to use a vertical MOS transistor as an output transistor of an integrated circuit.

In this case, by increasing the gate voltage by combining the vertical MOS transistor and the charge pump, the on-resistance of the output MOS transistor can be suppressed low, so that the heat generation of the integrated circuit can be reduced.

Generally, when a MOS transistor is used as an output transistor, the current is limited by clamping the gate-source voltage of the output transistor constant.

FIG. 4 is a circuit diagram of an example of a conventional integrated circuit, and FIG.
FIG. 6 is a waveform diagram of an output current for explaining the operation of the circuit in the figure.

As shown in FIG. 4, the integrated circuit 1 _b has a gate drive circuit 2 having a charge pump and supplying a gate voltage V _G to the node N, and a gate G connected to the node N and a drain having a drain voltage V _D. Output MOS whose receiving source is connected to the output terminal T _O
Transistor Q _O and, gate output of the MOS transistor to Q ₁ for current limiting gate G ₁ is the drain receives a drain voltage V _D is the source connected to the node N is connected to the output terminal T _O via the normal-series diode SD It has _a bypass circuit _3a .

First, the input switch SW ₁ is closed to supply the high level “H” input voltage V ₁ to the input terminal T _1, and the gate voltage V _G output from the gate drive circuit 2 is raised to the drain power supply voltage V _DD or higher. Turns on the output MOS transistor Q _O.

Here, when the output terminal T _O is in the same state as when the output switch SW _O was closed by grounding in advance due to some abnormality, input the input voltage V ₁ to the “H” level at time t _1. When the switch SW ₁ is closed, the gate voltage V _G exceeds the sum of the threshold voltage V _T of the MOS transistor Q ₁ for current limiting and the forward voltage nV _F of the n forward series diodes SD for current limiting. Transistor Q ₁ turns on and gate / output bypass current i ₁
To clamp the gate-source voltage of the output MOS transistor Q _O to (V _T + nV _F ) to limit the output current i _O as shown in FIG.

Here, the number of diode stages n is selected so as to satisfy the equation (1) so that the output MOS transistor Q _O can be turned on.

n> V _T / V _F (1) For example, when the threshold voltage V _T of the output transistor Q _O is about 2 V, n may be selected as 3.

[Problems to be Solved by the Invention]

In the conventional integrated circuit described above, the output current is well limited when the input voltage becomes "H" level when the output terminal of the current limiting circuit is grounded in advance, but the input voltage is "H" level. When the output terminal is grounded due to some abnormality in the state, there is a drawback that a large output current at a transition time flows at the time of rising and destroys the integrated circuit.

The cause is the parasitic inductances L ₁ and L _O of the power supply side wiring and the load side wiring.

FIGS. 6 (a) and 6 (b) are waveform diagrams of the signal voltage and the output current of each part for explaining the problems of the circuit of FIG.

When the output MOS transistor Q _O is in the ON state, its on-resistance is very small and the output terminal T _O
When grounded by the output switch SW _{O at} t _O , most of the power supply voltage V _DD is applied to the inductance L ₁ of the power supply side wiring and the inductance L _O of the output side wiring.

However, the gate / output bypass circuit _3a is an MO for current control.
Voltage between the gate G ₁ and the output terminal T _O of the S transistor Q ₁ is (V
_Since it does not operate unless it becomes more than _T + nV _F ), a large current as shown in B transiently flows during the number + μsec when the power supply voltage is recovered.

Generally, the wiring inductance is about 1 μH when the wiring diameter is 1 mm and the length is 1 m, and when the ON resistance of the output transistor Q _O is about 0.1 Ω, the output current i _O becomes the original current limit value. It may take several + to several hundreds of microseconds to stabilize.

An object of the present invention is to provide an integrated circuit having an output current limiting circuit that operates stably even at the rising time.

[Means for Solving the Problems]

The integrated circuit of the present invention includes a gate drive circuit that receives an input voltage and supplies a gate voltage to a node N, and a gate having the contact N.
Output MO that is connected to and the drain (source) is connected to one power supply and the source (drain) supplies the output voltage to the output terminal.
An S transistor, a first MOS transistor having a gate connected to the one power source and a drain (source) connected to the contact N, and one end connected to the source (drain) of the transistor and the other end connected to the output terminal. In the integrated circuit having a gate and an output bypass circuit including a constant voltage element, the input terminal receives the output voltage and outputs a gate pulse having a predetermined time width, and the gate receives the gate pulse. A gate-ground bypass circuit having a second MOS transistor having a drain (source) connected to the contact N and a source (drain) connected to a ground potential point is added.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment of the present invention.

The integrated circuit 1 has a pulse generation circuit that receives the input voltage V ₁ and the output voltage V _O to generate a gate pulse voltage V _A , a gate that receives the pulse voltage V _A , a drain that is connected to the node N, and a source that is grounded. except it yl point obtained by adding a gate grounding bypass circuit 3 _b having a MOS transistor Q ₂ for the second current limit is the same as conventional integrated circuits 1 _b.

Here, the pulse generation circuit includes a level detection circuit 4 for an inverter I that inputs an output voltage V _O , a CR time constant circuit 5 that differentiates the detected voltage V _L , and a differential voltage V _t that is input to one of the other and the other. _A two-gate input circuit of an AND circuit AND which inputs the input voltage V ₁ and outputs an AND voltage V _A.

FIGS. 2A and 2B are waveform diagrams of the signal voltage and the output current of each part for explaining the operation of the circuit of FIG.

First, when the load is grounded due to some abnormality, the output switch SW _O corresponds to the ON state.

Therefore, as described in the operation of the conventional circuit in FIG. 5, when the input switch SW ₁ is turned on at time t ₁ , the input voltage V ₁
Becomes "H" level, but the gate-source voltage of the output MOS transistor Q _O is suppressed to (V _T + nV _F ), so that the output current i _O is limited to a predetermined value.

Next, as shown in FIG. 2, when the input voltage V _O is "H" level and the output MOS transistor Q _O is turned on, the time t _O
When the switch SW _O is turned on and the output terminal T _O is grounded, the output voltage V _O rises, so the level detection circuit 4
Output becomes H, and the differential voltage V _t of the time constant circuit 5 of the CR differentiating circuit becomes “H” level only during the time of τ = C · R.
It is input to the D circuit AND and the current limiting MOS transistor Q ₂ is τ
It is turned on for a second to instantly reduce the gate voltage V _G of the output transistor Q _O.

The gate voltage V _A of the current limiting MOS transistor Q ₂ can be reduced by the amount of the voltage drop due to the inductance L ₁ of the wiring on the power supply side, but since the source terminal is connected to ground, the gate-source voltage is applied sufficiently high. Cage, transistor
The on-resistance of Q ₂ becomes low and the gate voltage V _G of the gate G can be lowered.

As a result, as shown in A of FIG. 2 (b), the output switch
It is possible to suppress the transient large current immediately after SW _O turns on t _o .

The time constant τ of the time constant circuit 5 is a product of the drain-gate capacitance C _GD of the output MOS transistor Q _O and the on-resistance R _{ON of} the second current limiting MOS transistor Q ₂ τ = C _GD · R _ON Choose to.

If τ is shorter than this, the current limiting effect is small, and if τ is longer than this, the current limiting effect becomes too effective and the output transistor Q _O is completely turned off.

Therefore, the value of τ is selected in the range of about 0.5 to 2 times τ _O.

FIG. 3 is a circuit diagram of the second embodiment of the present invention.

In this embodiment, the level detection circuit _4a is the inverter I of FIG.
It has an inverter that uses a comparator COMP and a reference power supply E _R instead of.

When a normal CMOS inverter is used, the threshold voltage depends on the power supply voltage, but in the present embodiment, the threshold voltage can be kept constant. Therefore, as shown in FIG. It is possible to improve the power supply voltage dependency at the first peak point A of the value.

〔The invention's effect〕

As described above, according to the present invention, by adding a gate / ground bypass circuit driven by a pulse generation circuit for inputting an input voltage and an output voltage to a conventional current limiting circuit, parasitic inductance of wiring from the input and output terminals is added. This has the effect of preventing the influence of a voltage drop due to and preventing a large transient current in the grounded state of the load end connected to the output terminal.

[Brief description of drawings]

FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIG. 2 (a).
And (b) are waveform diagrams of signal voltage and output current of each part for explaining the operation of the circuit of FIG. 1, FIG. 3 is a circuit diagram of the second embodiment of the present invention, and FIG. A circuit diagram of an example of an integrated circuit, FIG. 5 is a waveform diagram of an output current for explaining the operation of the circuit of FIG. 4, and FIGS. 6 (a) and 6 (b) show problems of the circuit of FIG. It is a waveform diagram of the signal voltage and output current of each part for explaining. 1, 1 _a ... Integrated circuit, 2 ... Gate drive circuit, 3 _a ... Gate / output bypass circuit, 3 _b ... Gate / ground bypass circuit,
4 ... Level detection circuit, 5 ... Time constant circuit, AND ... AND circuit,
E _R ... reference source, N ... node, G ... output gate, G _1, G ₂ ... first to the second gate, Q _1, Q ₂ ... MOS transistor, Q _O ... output MOS transistor, SD ... forward series diode , T ₁ ... input terminal, T _O ... output terminal, V _R ... reference voltage, i _O ... output current,
i ₁ , i ₂ ... Bypass current, V _A ... AND voltage, V _D ... Drain voltage, V ₁ ... Input voltage, V _G ... Gate voltage, V _L ... Level detection voltage, V _O ... Output voltage.

Claims (1)

[Claims] 1. A gate drive circuit for receiving an input voltage to supply a gate voltage to a contact N, a gate connected to the contact N, a drain connected to one power source, and a source connected to an output terminal. An output MOS transistor for supplying an output voltage, a first MOS transistor having a gate connected to the one power source and a drain (source) connected to the contact N, and one end of the source (drain) of the first MOS transistor In an integrated circuit having a gate / output bypass circuit connected to the output terminal and having the other end connected to the output terminal, an input circuit receives the output voltage and outputs a pulse pulse having a predetermined time width. A second MOS transistor whose gate receives the gate pulse and whose drain (source) is connected to the contact N and whose source (drain) is connected to a ground potential point Integrated circuit characterized in that by adding a gate grounding bypass circuit having a capacitor.