JPH06216735A - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPH06216735A JPH06216735A JP364493A JP364493A JPH06216735A JP H06216735 A JPH06216735 A JP H06216735A JP 364493 A JP364493 A JP 364493A JP 364493 A JP364493 A JP 364493A JP H06216735 A JPH06216735 A JP H06216735A
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- current
- output circuit
- limiting element
- current limiting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はサーマルヘッドドライバ
ーなど電子装置の出力回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit of an electronic device such as a thermal head driver.
【０００２】[0002]
【従来の技術】図７はサーマルヘッドドライバーなどの
出力回路の従来例を示す回路図である。図７において、
出力回路はそのドレインが出力端子Ｏにそのソースが接
地端子にそれぞれ接続された出力段のＮ ＭＯＳＦＥＴ
１と電圧端子Ｖ1 と接地端子間にその主端子が直列に接
続されたＰ ＭＯＳＦＥＴ３と Ｎ ＭＯＳＦＥＴ４と
からなる前段のインバータとで構成され、このＰ ＭＯ
ＳＦＥＴ３とＮ ＭＯＳＦＥＴ４の主端子の接続点は出
力段のＮ ＭＯＳＦＥＴ１のゲートに接続され、これら
のゲートはそれぞれ入力端子Ｉに接続される。2. Description of the Related Art FIG. 7 is a circuit diagram showing a conventional example of an output circuit such as a thermal head driver. In FIG.
The output circuit is an N-MOSFET of the output stage whose drain is connected to the output terminal O and whose source is connected to the ground terminal.
1 and a voltage terminal V 1 and a ground terminal, the main terminal of which is connected in series to a front-stage inverter composed of a P MOSFET 3 and an N MOSFET 4.
The connection point between the main terminals of the SFET 3 and the N MOSFET 4 is connected to the gate of the N MOSFET 1 of the output stage, and these gates are connected to the input terminal I, respectively.
【０００３】この出力回路の動作は次の通りである。入
力端子Ｉに「Ｈ」の信号を入力するとＰ ＭＯＳＦＥＴ
３はオン，Ｎ ＭＯＳＦＥＴ４はオフとなり、出力段の
ＮＭＯＳＦＥＴ１はそのゲートに電源端子Ｖ1 からＰ
ＭＯＳＦＥＴ３を通してゲート電流が入力されてオンす
る。また、入力端子に「Ｌ」の信号を入力するとＰＭＯ
ＳＦＥＴ３はオフ，Ｎ ＭＯＳＦＥＴ４はオンとなり、
出力段のＮ ＭＯＳＦＥＴ１はそのゲートが接地されて
オフする。The operation of this output circuit is as follows. When inputting "H" signal to input terminal I, P MOSFET
3 is on, N MOSFET 4 is off, and the output stage NMOSFET 1 has its gate connected to the power terminals V 1 to P
The gate current is input through the MOSFET 3 and turned on. Also, if an "L" signal is input to the input terminal, the PMO
SFET3 is off, N MOSFET4 is on,
The N-MOSFET 1 in the output stage is turned off because its gate is grounded.
【０００４】このようにして入力端子Ｉに「Ｈ」あるい
は「Ｌ」の信号を入力することにより、出力端子Ｏと接
地端子間にオンあるいはオフの信号が出力される。By inputting the "H" or "L" signal to the input terminal I in this manner, an ON or OFF signal is output between the output terminal O and the ground terminal.
【０００５】[0005]
【発明が解決しようとする課題】前述の出力回路におい
ては、出力段のＮ ＭＯＳＦＥＴのターンオフあるいは
ターンオン時間が短かいとスイッチング時に回路にノイ
ズ電圧が発生しやすくなり、このノイズ電圧が高いと素
子を破壊する事故を生じることがある。この対策として
前段のインバータのＮ ＭＯＳＦＥＴあるいはＰ ＭＯ
ＳＦＥＴのゲート長を長くしてゲート容量を増大し、前
段のインバータのタンーオフあるいはターンオン時間を
延長して出力段のＮ ＭＯＳＦＥＴのターンオフあるい
はターンオン時間を延長しノイズ電圧を低減することが
行われるが、この場合、ターンオフあるいはターンオン
時間を０．８μＳから１．０μＳに延長するのに、例え
ばこの出力回路を半導体集積回路として形成した場合半
導体チップの面積を約１０％増大する必要がある。この
ように半導体チップの面積が増大することはコスト上昇
要因となり、特に各表示ドットごとに出力回路が設けら
れるサーマルヘッドドライバーなど出力回路の個数が多
いとき特に問題となる。In the above-mentioned output circuit, if the turn-off or turn-on time of the N MOSFET in the output stage is short, a noise voltage is apt to occur in the circuit during switching. This may cause an accident of destruction. As a countermeasure, N MOSFET or P MO of the inverter in the previous stage
The gate length of the SFET is increased to increase the gate capacitance, and the turn-off or turn-on time of the inverter in the previous stage is extended to extend the turn-off or turn-on time of the N MOSFET in the output stage to reduce the noise voltage. In this case, in order to extend the turn-off or turn-on time from 0.8 μS to 1.0 μS, it is necessary to increase the area of the semiconductor chip by about 10% when this output circuit is formed as a semiconductor integrated circuit. Such an increase in the area of the semiconductor chip causes a cost increase, and is especially a problem when the number of output circuits such as a thermal head driver in which an output circuit is provided for each display dot is large.
【０００６】本発明の目的は出力回路が形成されている
半導体チップの面積をそれ程大きくすることなく出力段
のＭＯＳＦＥＴのターンオンあるいはターンオフ時間を
延長することにある。An object of the present invention is to extend the turn-on or turn-off time of the output stage MOSFET without increasing the area of the semiconductor chip on which the output circuit is formed.
【０００７】[0007]
【課題を解決するための手段】前述の目的を達成するた
めに、本発明は出力段の一極性チャンネルのＭＯＳＦＥ
Ｔと、電源端子と接地端子間に直列に接続され、かつそ
られのゲートが互に接続された他極性チャンネルおよび
一極性チャンネルの第１および第２のＭＯＳＦＥＴとか
らなる前段のインバータとで構成された出力回路におい
て、前記第２のＭＯＳＦＥＴと接地端子の間に限流要素
（以下第１の限流要素と称する）を設けるようにする。
あるいは前記第１のＭＯＳＦＥＴと電源端子の間に限流
要素（以下第２の限流要素と称する）を設けるようにす
る。更にあるいは前記第２のＭＯＳＦＥＴと接地端子の
間および前記第１のＭＯＳＦＥＴと電源端子との間にそ
れぞれ第１および第２の限流要素を設けるようにする。
そして前記第１の限流要素はそのゲートにスレッシュ電
圧より僅かに高い電圧が印加される一極性チャンネルの
ＭＯＳＦＥＴからなり、前記第２の限流要素はそのゲー
トにスレッシュ電圧より僅かに高い電圧が印加される他
極性チャンネルのＭＯＳＦＥＴからなるようにする。あ
るいは前記第１の限流要素は電流ミラー回路に構成され
て所定の電流値の電流を通電する一極性チャンネルのＭ
ＯＳＦＥＴからなり、前記第２の限流要素は電流ミラー
回路に構成されて所定の電流値の電流を通電する他極性
チャンネルのＭＯＳＦＥＴからなるようにする。In order to achieve the above-mentioned object, the present invention provides a unipolar channel MOSFE of the output stage.
T, and a front-stage inverter composed of a first polarity MOSFET and a second polarity MOSFET of a unipolar channel connected in series between a power supply terminal and a ground terminal and having their gates connected to each other. In this output circuit, a current limiting element (hereinafter referred to as a first current limiting element) is provided between the second MOSFET and the ground terminal.
Alternatively, a current limiting element (hereinafter referred to as a second current limiting element) is provided between the first MOSFET and the power supply terminal. Further alternatively, first and second current limiting elements are provided between the second MOSFET and the ground terminal and between the first MOSFET and the power supply terminal, respectively.
The first current limiting element is composed of a unipolar channel MOSFET in which a voltage slightly higher than the threshold voltage is applied to its gate, and the second current limiting element has a voltage slightly higher than the threshold voltage in its gate. It is composed of MOSFETs of the other polarity channel to be applied. Alternatively, the first current limiting element is configured as a current mirror circuit, and M of a unipolar channel that conducts a current of a predetermined current value.
The second current limiting element is composed of an OSFET, and the second current limiting element is composed of a MOSFET of another polarity channel which is configured as a current mirror circuit and carries a current of a predetermined current value.
【０００８】[0008]
【作用】本発明は出力段の一極性チャンネルのＭＯＳＦ
ＥＴと、電源端子と接地端子間に直列に接続され、かつ
そられのゲートが互に接続された他極性チャンネルおよ
び一極性チャンネルの第１および第２のＭＯＳＦＥＴと
からなる前段のインバータとで構成された出力回路にお
いて、前記第２のＭＯＳＦＥＴと接地端子の間に限流要
素（以下第１の限流要素と称する）を設け、この第１の
限流要素はそのゲートにスレッシュ電圧より僅かに高い
電圧が印加される一極性チャンネルのＭＯＳＦＥＴから
なるようにした。この場合このＭＯＳＦＥＴは抵抗とし
て作用するので、出力段のＭＯＳＦＥＴのゲート容量に
蓄積された電荷はこの抵抗を通して放電し、このゲート
容量とこの抵抗の抵抗値とで定まる時定数に対応して出
力段のＭＯＳＦＥＴのターンオフ時間は延長される。あ
るいはこの第１の限流要素は電流ミラー回路に構成され
て所定の電流値の電流を通電する一極性チャンネルのＭ
ＯＳＦＥＴからなるようにした。この場合出力段のＭＯ
ＳＦＥＴのゲート容量に蓄積された電荷は前記の所定の
電流値の電流によって放電されるので、このゲート容量
とこの電流の電流値とで定まる時定数に対応して出力段
のＭＯＳＦＥＴのターンオフ時間は延長される。あるい
は前記第１のＭＯＳＦＥＴと電源端子の間に限流要素
（以下第２の限流要素と称する）を設け、この第２の限
流要素はそのゲートにスレッシュ電圧より僅かに高い電
圧が印加される他極性チャンネルのＭＯＳＦＥＴとから
なるようにした。この場合このＭＯＳＦＥＴは抵抗とし
て作用するので、出力段のＭＯＳＦＥＴのゲート容量に
蓄積された電荷はこの抵抗を通して放電し、このゲート
容量とこの抵抗の抵抗値とで定まる時定数に対応して出
力段のＭＯＳＦＥＴのターンオフ時間は延長される。あ
るいはこの第２の限流要素は電流ミラー回路に構成され
て所定の電流値の電流を通電する他極性チャンネルのＭ
ＯＳＦＥＴからなるようにした。この場合出力段のＭＯ
ＳＦＥＴのゲート容量に蓄積された電荷は前記の所定の
電流値の電流によって放電されるので、このゲート容量
とこの電流の電流値とで定まる時定数に対応して出力段
のＭＯＳＦＥＴのターンオフ時間は延長される。あるい
は前記第２のＭＯＳＦＥＴと接地端子の間および前記第
１のＭＯＳＦＥＴと電源端子との間にそれぞれ第１およ
び第２の限流要素を設けるようにした。これら第１およ
び第２の限流要素は前述と同様であり、出力段のＭＯＳ
ＦＥＴのターンオフ時間およびターンオン時間がそれぞ
れ延長される。The present invention is a unipolar channel MOSF of the output stage.
ET and a front-stage inverter composed of a first polarity MOSFET and a second polarity MOSFET of one polarity channel connected in series between a power supply terminal and a ground terminal and having their gates connected to each other In the output circuit described above, a current limiting element (hereinafter referred to as a first current limiting element) is provided between the second MOSFET and the ground terminal, and the first current limiting element has a gate at a voltage slightly lower than a threshold voltage. It is composed of a unipolar channel MOSFET to which a high voltage is applied. In this case, since this MOSFET acts as a resistor, the electric charge accumulated in the gate capacitance of the MOSFET in the output stage is discharged through this resistor, and the output stage corresponding to the time constant determined by this gate capacitance and the resistance value of this resistor. The MOSFET turn-off time is extended. Alternatively, the first current limiting element is configured as a current mirror circuit, and M of a unipolar channel that conducts a current of a predetermined current value.
It is composed of OSFET. In this case, the output stage MO
Since the electric charge accumulated in the gate capacitance of the SFET is discharged by the current of the above-mentioned predetermined current value, the turn-off time of the MOSFET of the output stage is corresponding to the time constant determined by this gate capacitance and the current value of this current. Be extended. Alternatively, a current limiting element (hereinafter referred to as a second current limiting element) is provided between the first MOSFET and the power supply terminal, and a voltage slightly higher than the threshold voltage is applied to the gate of the second current limiting element. And a MOSFET of another polarity channel. In this case, since this MOSFET acts as a resistor, the charge accumulated in the gate capacitance of the MOSFET in the output stage is discharged through this resistor, and the output stage is corresponding to the time constant determined by this gate capacitance and the resistance value of this resistor. The MOSFET turn-off time is extended. Alternatively, the second current limiting element is configured as a current mirror circuit and M of another polarity channel that conducts a current of a predetermined current value.
It is composed of OSFET. In this case, the output stage MO
Since the electric charge accumulated in the gate capacitance of the SFET is discharged by the current of the above-mentioned predetermined current value, the turn-off time of the MOSFET in the output stage is corresponding to the time constant determined by this gate capacitance and the current value of this current. Be extended. Alternatively, first and second current limiting elements are provided between the second MOSFET and the ground terminal and between the first MOSFET and the power supply terminal, respectively. These first and second current limiting elements are the same as those described above, and the output stage MOS is
The FET turn-off time and turn-on time are each extended.
【０００９】[0009]
【実施例】図１は本発明の出力回路の一実施例を示す回
路図である。図１に示す本発明の出力回路は図７に示す
従来の出力回路において、前段のインバータのＮ ＭＯ
ＳＦＥＴ４と接地端子との間に、そのドレインがＮ Ｍ
ＯＳＦＥＴ４のソースにそのソースが接地端子にそれぞ
れ接続されるＮ ＭＯＳＦＥＴ６を設け、このＮＭＯＳ
ＦＥＴ６のゲートには電源端子Ｖ2 の電圧ｖ2 が抵抗７
および８によって分圧されて入力される。1 is a circuit diagram showing an embodiment of an output circuit of the present invention. The output circuit of the present invention shown in FIG. 1 is the same as the conventional output circuit shown in FIG.
Between the SFET4 and the ground terminal, its drain is NM
The source of the OSFET 4 is provided with an N MOSFET 6 whose source is connected to the ground terminal, respectively.
The voltage v 2 of the power supply terminal V 2 is applied to the resistor 7 at the gate of the FET 6.
And divided by 8 and input.
【００１０】この出力回路の動作は次の通りである。ま
ず、抵抗７および８の抵抗値を調整してＮ ＭＯＳＦＥ
Ｔ６のゲートに入力される電圧をこのＮ ＭＯＳＦＥＴ
６のスレッシュ電圧１．１Ｖより僅かに高い１．２Ｖと
するとこのＮ ＭＯＳＦＥＴ６のドレイン・ソース間抵
抗は、例えば２００ＫΩ程度となる。この状態で入力端
子Ｉに「Ｌ」の信号が入力された場合を考えると、前段
のインバータのＰ ＭＯＳＦＥＴ３はオフ，Ｎ ＭＯＳ
ＦＥＴ４はオンとなり、出力段のＮ ＭＯＳＦＥＴ１の
ゲートはＮ ＭＯＳＦＥＴ６のドレイン・ソースを通し
て接地される。これにより、出力段のＮ ＭＯＳＦＥＴ
１のゲート容量に蓄積された電荷はこのＮ ＭＯＳＦＥ
Ｔ６のドレイン・ソース間の抵抗、この例では２００Ｋ
Ωの抵抗を通して放電するので、このゲート容量とＮ
ＭＯＳＦＥＴ６のドレイン・ソース間の抵抗値とで定ま
る時定数に対応して、出力段のＮ ＭＯＳＦＥＴ１のタ
ーンオフ時間は、例えば０．８μＳから２．８μＳに延
長される。The operation of this output circuit is as follows. First, the resistance values of the resistors 7 and 8 are adjusted to adjust the N MOSFE.
The voltage input to the gate of T6
When the threshold voltage of 6 is 1.2 V, which is slightly higher than the threshold voltage of 1.1 V, the resistance between the drain and the source of this N MOSFET 6 is, for example, about 200 KΩ. Considering the case where an "L" signal is input to the input terminal I in this state, the P MOSFET 3 of the inverter in the previous stage is off, and the N MOS is on.
The FET 4 is turned on, and the gate of the N MOSFET 1 in the output stage is grounded through the drain / source of the N MOSFET 6. As a result, the N MOSFET of the output stage
The charge accumulated in the gate capacitance of 1 is this N MOSFE
T6 drain-source resistance, 200K in this example
Since it discharges through the resistance of Ω, this gate capacitance and N
The turn-off time of the N MOSFET 1 in the output stage is extended from 0.8 μS to 2.8 μS, for example, corresponding to the time constant determined by the drain-source resistance of the MOSFET 6.
【００１１】なお、その他の動作については図７と同様
である。図２は本発明の出力回路の異なる実施例を示す
回路図である。図２に示す本発明の出力回路は図７に示
す従来の出力回路において、前段のインバータのＰ Ｍ
ＯＳＦＥＴ３と電源端子Ｖ1 との間に、そのドレインが
電源端子Ｖ1 にそのソースがＰ ＭＯＳＦＥＴ３のドレ
インにそれぞれ接続されるＰ ＭＯＳＦＥＴ９を設け、
このＰ ＭＯＳＦＥＴ９のゲートには電源端子Ｖ2 の電
圧ｖ2 が抵抗１０および１１によって分圧されて入力さ
れる。The other operations are the same as in FIG. FIG. 2 is a circuit diagram showing another embodiment of the output circuit of the present invention. The output circuit of the present invention shown in FIG. 2 corresponds to the conventional output circuit shown in FIG.
Between the OSFET 3 and the power supply terminal V 1 , a P MOSFET 9 whose drain is connected to the power supply terminal V 1 and whose source is connected to the drain of the P MOSFET 3 is provided,
The voltage v 2 of the power supply terminal V 2 is divided by the resistors 10 and 11 and input to the gate of the P MOSFET 9.
【００１２】この出力回路の動作は次の通りである。ま
ず、抵抗１０および１１の抵抗値を調整してＰ ＭＯＳ
ＦＥＴ９のゲートに入力される電圧をこのＰ ＭＯＳＦ
ＥＴ９のスレッシュ電圧１．１Ｖより僅かに高い１．２
ＶとするとこのＰ ＭＯＳＦＥＴ９のドレイン・ソース
間抵抗は、例えば２００ＫΩ程度となる。この状態で入
力端子Ｉに「Ｈ」の信号が入力された場合を考えると、
前段のインバータのＰＭＯＳＦＥＴ３はオン，Ｎ ＭＯ
ＳＦＥＴ４はオフとなり、出力段のＮ ＭＯＳＦＥＴ１
のゲートはＰ ＭＯＳＦＥＴ９のドレイン・ソースを通
して電源端子Ｖ1 に導通する。これにより、出力段のＮ
ＭＯＳＦＥＴ１のゲートには電源端子Ｖ1 からＰ Ｍ
ＯＳＦＥＴ９のドレイン・ソース間の抵抗、この例では
２００ＫΩの抵抗を通して充電されるので、ゲート容量
とＰ ＭＯＳＦＥＴ９のドレイン・ソース間の抵抗値で
定まる時定数に対応して、出力段のＮ ＭＯＳＦＥＴ１
の、例えば０．８μＳから２．８μＳに延長される。The operation of this output circuit is as follows. First, by adjusting the resistance values of the resistors 10 and 11, the PMOS
The voltage input to the gate of FET9 is
1.2 which is slightly higher than the threshold voltage of ET9 1.1V
Assuming V, the drain-source resistance of this P MOSFET 9 is, for example, about 200 KΩ. Considering the case where a signal of "H" is input to the input terminal I in this state,
The PMOSFET 3 of the inverter in the previous stage is ON, N MO
SFET4 is turned off, and the output stage NMOSFET1
The gate of is connected to the power supply terminal V 1 through the drain / source of the P MOSFET 9. As a result, the output stage N
The gate of MOSFET 1 has power supply terminals V 1 to P M
Since it is charged through the drain-source resistance of the OSFET 9, which is a resistance of 200 KΩ in this example, the N MOSFET 1 of the output stage corresponds to the time constant determined by the gate capacitance and the resistance value between the drain-source of the P MOSFET 9.
, For example, from 0.8 μS to 2.8 μS.
【００１３】なお、その他の動作については図７と同様
である。図３は本発明の出力回路の更に異なる実施例を
示す回路図である。図３に示す本発明の出力回路は図７
に示す従来の出力回路において、前段のインバータのＰ
ＭＯＳＦＥＴ４と接地端子との間に、そのドレインがＮ
ＭＯＳＦＥＴ４のソースにそのソースが接地端子にそ
れぞれ接続されるＮ ＭＯＳＦＥＴ６と、前段のインバ
ータのＰ ＭＯＳＦＥＴ３と電源端子Ｖ1 との間に、そ
のドレインが電源端子Ｖ1 にそのソースがＰ ＭＯＳＦ
ＥＴ３のドレインにそれぞれ接続されるＰ ＭＯＳＦＥ
Ｔ９とを設け、これらＮ ＭＯＳＦＥＴ６とＰ ＭＯＳ
ＦＥＴ９の各ゲートには電源端子Ｖ2 の電源ｖ2 が抵抗
１２，１３および１４によって印加される。The other operations are the same as those in FIG. FIG. 3 is a circuit diagram showing still another embodiment of the output circuit of the present invention. The output circuit of the present invention shown in FIG. 3 is shown in FIG.
In the conventional output circuit shown in FIG.
The drain is N between the MOSFET 4 and the ground terminal.
Between the source of the MOSFET 4 and the N MOSFET 6 whose sources are respectively connected to the ground terminal, and between the P MOSFET 3 and the power supply terminal V 1 of the preceding stage inverter, its drain is the power supply terminal V 1 and its source is P MOSF.
P-MOSFE connected to the drain of ET3
T9 and these N MOSFET 6 and P MOS
The power supply v 2 of the power supply terminal V 2 is applied to each gate of the FET 9 by the resistors 12, 13 and 14.
【００１４】この出力回路は図１に示す出力回路と図２
に示す出力回路の回路構成を併せて有するもので、その
動作はこれら出力回路の動作を併せたものである。図４
は本発明の出力回路の更に異なる実施例を示す回路図で
ある。図４は図１の抵抗７および８に代えて、そのドレ
インが抵抗１６を介して電源端子Ｖ2 にそのソースが接
地端子にそれぞれ接続され、そのドレインとゲート間が
短絡されたＮ ＭＯＳＦＥＴ１５を設け、このＮ ＭＯ
ＳＦＥＴ１５のゲートを前段のインバータのＮ ＭＯＳ
ＦＥＴ６のゲートに接続したものである。ここで、Ｎ
ＭＯＳＦＥＴ１５とＮ ＭＯＳＦＥＴ６とは電流ミラー
回路を構成しており、抵抗１６に流れる電流Ｉ0 に等し
い電流がＮ ＭＯＳＦＥＴ６のドレイン・ソースを通し
て流れる（Ｎ ＭＯＳＦＥＴ１５とＮ ＭＯＳＦＥＴ６
の容量が等しいとして）。This output circuit is similar to the output circuit shown in FIG.
The circuit configuration of the output circuit shown in (1) is also included, and the operation is a combination of the operations of these output circuits. Figure 4
FIG. 7 is a circuit diagram showing still another embodiment of the output circuit of the present invention. In FIG. 4, instead of the resistors 7 and 8 of FIG. 1, an N MOSFET 15 is provided, the drain of which is connected to the power supply terminal V 2 through the resistor 16 and the source of which is connected to the ground terminal, and the drain and gate of which are short-circuited. , This N MO
The gate of SFET15 is the NMOS of the previous stage inverter.
It is connected to the gate of the FET 6. Where N
The MOSFET 15 and the N MOSFET 6 form a current mirror circuit, and a current equal to the current I 0 flowing through the resistor 16 flows through the drain / source of the N MOSFET 6 (N MOSFET 15 and N MOSFET 6).
Of equal capacity).
【００１５】この出力回路の動作は次の通りである。ま
ず、抵抗１６の抵抗値を調整して電流Ｉ0 の電流値を、
例えば２５μＡに調整する（例えば、電源端子Ｖ2 の電
圧ｖ 2 を５Ｖ，抵抗１６を２００ＫΩとして）。この状
態で入力端子Ｉに「Ｌ」の信号が入力されると前段のイ
ンバータのＰ ＭＯＳＦＥＴ３はオフ，Ｎ ＭＯＳＦＥ
Ｔ４はオンとなり、出力段のＮ ＭＯＳＦＥＴ１のゲー
トはＮ ＭＯＳＦＥＴ６のドレイン・ソースを通して接
地される。ここで、このＮ ＭＯＳＦＥＴ６はＮ ＭＯ
ＳＦＥＴ１５と電流ミラー回路を構成しているので、こ
のＮ ＭＯＳＦＥＴ６のドレイン・ソースを通して流れ
る電流は抵抗１６を流れる電流Ｉ0 に等しく制御され、
出力段のＮ ＭＯＳＦＥＴ１のゲート容量に蓄積された
電荷はこの電流Ｉ0 によって、この例では２５μＡの電
流で放電されるので、このゲート容量と電流Ｉ0 の電流
値とで定まる時定数に対応して出力段のＮ ＭＯＳＦＥ
Ｔ１のターンオフ時間は、例えば０．８μＳから２．８
μＳに延長される。The operation of this output circuit is as follows. Well
Without adjusting the resistance value of the resistor 160Current value of
For example, it is adjusted to 25 μA (for example, power supply terminal V2Electric power
Pressure v 25V and resistance 16 to 200KΩ). This state
In this state, when the signal of “L” is input to the input terminal I,
Inverter P MOSFET3 is off, N MOSFE
T4 is turned on, and the gate of N MOSFET1 of the output stage is turned on.
Is connected through the drain and source of N MOSFET 6.
Grounded. Here, this N MOSFET 6 is N MO
Since it constitutes a current mirror circuit with SFET15,
Flow through the drain and source of N MOSFET 6
Current I flowing through the resistor 160Is controlled equal to
Accumulated in the gate capacitance of N MOSFET1 in the output stage
The electric charge is this current I0Therefore, in this example, 25 μA
This gate capacitance and current I0Current
N MOSFE of the output stage corresponding to the time constant determined by
The turn-off time of T1 is, for example, 0.8 μS to 2.8.
It is extended to μS.
【００１６】なお、その他の動作については図７と同様
である。図５は本発明の出力回路の更に異なる実施例を
示す回路図である。図５は図２の抵抗１０および１１に
代えて、そのドレインが電源端子Ｖ2 にそのソースが抵
抗１６を介して接続端子にそれぞれ接続され、そのソー
スとゲート間が短絡されたＰ ＭＯＳＦＥＴ１７を設
け、このＰ ＭＯＳＦＥＴ１７のゲートを前段のインバ
ータのＰ ＭＯＳＦＥＴ９のゲートに接続したものであ
る。ここで、Ｐ ＭＯＳＦＥＴ１７とＰ ＭＯＳＦＥＴ
９とは電流ミラー回路を構成しており、抵抗１６に流れ
る電流Ｉ0 に等しい電流がＰ ＭＯＳＦＥＴ９のドレイ
ン・ソースを通して流れる（Ｐ ＭＯＳＦＥＴ１７とＰ
ＭＯＳＦＥＴ６の容量が等しいとして）。The other operations are the same as in FIG. FIG. 5 is a circuit diagram showing still another embodiment of the output circuit of the present invention. In FIG. 5, instead of the resistors 10 and 11 of FIG. 2, a P MOSFET 17 is provided, the drain of which is connected to the power supply terminal V 2 and the source of which is connected to the connection terminal through the resistor 16, and the source and gate of which are short-circuited. The gate of the P MOSFET 17 is connected to the gate of the P MOSFET 9 of the preceding inverter. Here, P MOSFET 17 and P MOSFET
9 constitutes a current mirror circuit, and a current equal to the current I 0 flowing through the resistor 16 flows through the drain / source of the P MOSFET 9 (P MOSFET 17 and P MOSFET 17).
(Assuming that the capacitances of MOSFET 6 are equal).
【００１７】この出力回路の動作は次の通りである。ま
ず、抵抗１６の抵抗値を調整して電流Ｉ0 の電流値を、
例えば２５μＡに調整する（例えば、電源端子Ｖ2 の電
圧ｖ 2 を５Ｖ，抵抗１６を２００ＫΩとして）。この状
態で入力端子Ｉに「Ｈ」の信号が入力されると前段のイ
ンバータ回路のＰ ＭＯＳＦＥＴ３はオン，Ｎ ＭＯＳ
ＦＥＴ４はオフとなり、出力段のＮ ＭＯＳＦＥＴ１の
ゲートはＰ ＭＯＳＦＥＴ９のドレイン・ソースを通し
て電源端子Ｖ1 に導通する。ここで、このＰＭＯＳＦＥ
Ｔ９はＰ ＭＯＳＦＥＴ１７と電流ミラー回路を構成し
ているので、このＰ ＭＯＳＦＥＴ９のドレイン・ソー
スを通して流れる電流は抵抗１６を流れる電流Ｉ0 に等
しく制御され、出力段のＮ ＭＯＳＦＥＴ１のゲート容
量はこの電流Ｉ0 によって、この例では２５μＡの電流
で充電されるので、このゲート容量と電流Ｉ0 の電流値
とで定まる時定数対応して出力段のＮ ＭＯＳＦＥＴ１
のターンオン時間は、例えば０．８μＳから２．８μＳ
に延長される。The operation of this output circuit is as follows. Well
Without adjusting the resistance value of the resistor 160Current value of
For example, it is adjusted to 25 μA (for example, power supply terminal V2Electric power
Pressure v 25V and resistance 16 to 200KΩ). This state
When the "H" signal is input to the input terminal I,
The P MOSFET 3 of the inverter circuit is ON, and the N MOS is
FET4 is turned off, and the output stage N MOSFET1
The gate is through the drain and source of P MOSFET 9.
Power terminal V1Conduct to. Where this PMOS FE
T9 forms a current mirror circuit with P MOSFET 17
Therefore, the drain and saw of this P MOSFET 9
Current flowing through the resistor 16 is the current I flowing through the resistor 16.0And so on
Controlled, the gate capacitance of N MOSFET1 in the output stage
The amount is this current I0In this example, the current of 25 μA
This gate capacitance and current I0Current value
N MOSFET1 at the output stage corresponding to the time constant determined by
The turn-on time of is, for example, 0.8 μS to 2.8 μS
Be extended to.
【００１８】なお、その他の動作については図７と同様
である。図６は本発明の出力回路の更に異なる実施例を
示す回路図である。図６は図３の抵抗１２，１３および
１４に代えて、そのソースが接地端子に接続されそのド
レインとゲート間が短絡されたＮ ＭＯＳＦＥＴ１５
と、そのドレインが電源端子Ｖ1 に接続され、そのソー
スとゲート間が短絡されたＰ ＭＯＳＦＥＴ１７と、こ
のＰ ＭＯＳＦＥＴ１７のソースとＮ ＭＯＳＦＥＴ１
５のドレインとの間に接続された抵抗１６とを設け、Ｎ
ＭＯＳＦＥＴ１５のゲートをＮ ＭＯＳＦＥＴ６のゲ
ートに、Ｐ ＭＯＳＦＥＴ１７のゲートをＰ ＭＯＳＦ
ＥＴ９のゲートに接続したものである。The other operations are the same as in FIG. FIG. 6 is a circuit diagram showing a further different embodiment of the output circuit of the present invention. FIG. 6 shows an N MOSFET 15 whose source is connected to the ground terminal and whose drain and gate are short-circuited, instead of the resistors 12, 13 and 14 of FIG.
And its drain is connected to the power supply terminal V 1 and its source and gate are short-circuited, and the source of this P MOSFET 17 and the N MOSFET 1
And a resistor 16 connected between the drain and the drain of
The gate of MOSFET 15 is the gate of N MOSFET 6, and the gate of P MOSFET 17 is P MOSF.
It is connected to the gate of ET9.
【００１９】この出力回路は図４に示す出力回路と図５
に示す出力回路の回路構成を併せて有するもので、その
動作はこれら出力回路の動作を併せたものである。前述
の図４〜６に示す実施例において、抵抗１６を通して流
れる電流Ｉ0 の電流値は、前述のように抵抗１６の抵抗
値を調整して設定してもよいし、あるいは電源端子Ｖ2
の電圧ｖ2 の電圧値を調整して設定してもよい。This output circuit is similar to the output circuit shown in FIG.
The circuit configuration of the output circuit shown in (1) is also included, and the operation is a combination of the operations of these output circuits. In the embodiments shown in FIGS. 4 to 6 described above, the current value of the current I 0 flowing through the resistor 16 may be set by adjusting the resistance value of the resistor 16 as described above, or the power supply terminal V 2
The voltage value of the voltage v 2 may be adjusted and set.
【００２０】また、図１〜図６に示す実施例において、
図７に示す従来の回路に追加し設けたＮ ＭＯＳＦＥＴ
６，Ｐ ＭＯＳＦＥＴ９，Ｎ ＭＯＳＦＥＴ１５，Ｐ
ＭＯＳＦＥＴ１７および抵抗７，８，１０，１１，１
２，１３，１４，１６はゲート制御用のごく小容量であ
り、これらを設けても半導体チップの面積はそれ程増大
することはない。In the embodiment shown in FIGS. 1 to 6,
N MOSFET added to the conventional circuit shown in FIG.
6, P MOSFET 9, N MOSFET 15, P
MOSFET 17 and resistors 7, 8, 10, 11, 1
Reference numerals 2, 13, 14, and 16 are very small capacitors for gate control, and even if they are provided, the area of the semiconductor chip does not increase so much.
【００２１】なお、図１〜図６に示す実施例においては
出力段のＭＯＳＦＥＴはＮ ＭＯＳＦＥＴとして説明し
たが、Ｐ ＭＯＳＦＥＴの場合この極性としに応じて、
前段のインバータの各ＭＯＳＦＥＴあるいは各実施例で
追加したＭＯＳＦＥＴの極性を選定することで同様に実
施できることは勿論である。In the embodiments shown in FIGS. 1 to 6, the MOSFET in the output stage is described as an N MOSFET, but in the case of a P MOSFET, the polarity is changed according to the polarity.
Of course, the same operation can be performed by selecting the polarity of each MOSFET of the preceding inverter or the MOSFET added in each embodiment.
【００２２】[0022]
【発明の効果】本発明の出力回路は出力段のＭＯＳＦＥ
Ｔのターンオフ時間あるいはターンオン時間を延長して
スイッチング時における回路のノイズ電圧を低減したの
で回路の信頼性が向上するとともに、半導体集積回路と
して形成した場合に半導体チップの面積がそれ程増大す
ることがなく低コストとなる。このことは、特に出力回
路の個数の多いサーマルヘッドドライバーなどで効果が
大きい。According to the output circuit of the present invention, the output stage MOSFE is provided.
Since the turn-off time or turn-on time of T is extended to reduce the noise voltage of the circuit at the time of switching, the reliability of the circuit is improved and the area of the semiconductor chip does not increase so much when it is formed as a semiconductor integrated circuit. Low cost. This is particularly effective in a thermal head driver having a large number of output circuits.
【図１】本発明の出力回路の一実施例を示す回路図FIG. 1 is a circuit diagram showing an embodiment of an output circuit of the present invention.
【図２】本発明の出力回路の異なる実施例を示す回路図FIG. 2 is a circuit diagram showing another embodiment of the output circuit of the present invention.
【図３】本発明の出力回路の更に異なる実施例を示す回
路図FIG. 3 is a circuit diagram showing still another embodiment of the output circuit of the present invention.
【図４】本発明の出力回路の更に異なる実施例を示す回
路図FIG. 4 is a circuit diagram showing still another embodiment of the output circuit of the present invention.
【図５】本発明の出力回路の更に異なる実施例を示す回
路図FIG. 5 is a circuit diagram showing still another embodiment of the output circuit of the present invention.
【図６】本発明の出力回路の更に異なる実施例を示す回
路図FIG. 6 is a circuit diagram showing still another embodiment of the output circuit of the present invention.
【図７】従来の出力回路の一例を示す回路図FIG. 7 is a circuit diagram showing an example of a conventional output circuit.
１ Ｎ ＭＯＳＦＥＴ（出力段の） ３ Ｐ ＭＯＳＦＥＴ（前段のインバータの第１の） ４ Ｎ ＭＯＳＦＥＴ（前段のインバータの第２の） ６ Ｎ ＭＯＳＦＥＴ（第１の限流要素） ９ Ｐ ＭＯＳＦＥＴ（第２の限流要素） 1 N MOSFET (of output stage) 3 P MOSFET (first of inverter of previous stage) 4 N MOSFET (second of inverter of previous stage) 6 N MOSFET (first current limiting element) 9 P MOSFET (second of current limiting element) Current limiting element)
Claims (10)
と、電源端子と接地端子間に直列に接続され、かつそら
れのゲートが互に接続された他極性チャンネルおよび一
極性チャンネルの第１および第２のＭＯＳＦＥＴとから
なる前段のインバータとで構成された出力回路におい
て、前記第２のＭＯＳＦＥＴと接地端子の間に限流要素
（以下第１の限流要素と称する）を設けたことを特徴と
する出力回路。1. A unipolar channel MOSFET for an output stage.
And a front-stage inverter comprising a first polarity MOSFET and a second polarity MOSFET of another polarity channel connected in series between a power supply terminal and a ground terminal and having their gates connected to each other. In the output circuit, a current limiting element (hereinafter referred to as a first current limiting element) is provided between the second MOSFET and the ground terminal.
と、電源端子と接地端子間に直列に接続され、かつそら
れのゲートが互に接続された他極性チャンネルおよび一
極性チャンネルの第１および第２のＭＯＳＦＥＴとから
なる前段のインバータとで構成された出力回路におい
て、前記第１のＭＯＳＦＥＴと電源端子の間に限流要素
（以下第２の限流要素と称する）を設けたことを特徴と
する出力回路。2. A unipolar channel MOSFET of the output stage.
And a front-stage inverter comprising a first polarity MOSFET and a second polarity MOSFET of another polarity channel connected in series between a power supply terminal and a ground terminal and having their gates connected to each other. In the output circuit, a current limiting element (hereinafter referred to as a second current limiting element) is provided between the first MOSFET and the power supply terminal.
と、電源端子と接地端子間に直列に接続され、かつそら
れのゲートが互に接続された他極性チャンネルおよび一
極性チャンネルの第１および第２のＭＯＳＦＥＴとから
なる前段のインバータとで構成された出力回路におい
て、前記第２のＭＯＳＦＥＴと接地端子の間および前記
第１のＭＯＳＦＥＴと電源端子との間にそれぞれ第１お
よび第２の限流要素を設けたことを特徴とする出力回
路。3. A unipolar channel MOSFET of the output stage.
And a front-stage inverter comprising a first polarity MOSFET and a second polarity MOSFET of another polarity channel connected in series between a power supply terminal and a ground terminal and having their gates connected to each other. In the output circuit, the output circuit further comprises first and second current limiting elements provided between the second MOSFET and the ground terminal and between the first MOSFET and the power supply terminal, respectively.
限流要素はそのゲートにスレッシュ電圧より僅かに高い
電圧が印加される一極性チャンネルのＭＯＳＦＥＴから
なることを特徴とする出力回路。4. The output circuit according to claim 1, wherein the first current limiting element is a unipolar channel MOSFET having a gate to which a voltage slightly higher than a threshold voltage is applied.
限流要素はそのゲートにスレッシュ電圧より僅かに高い
電圧が印加される他極性チャンネルのＭＯＳＦＥＴから
なることを特徴とする出力回路。5. The output circuit according to claim 2, wherein the second current limiting element comprises a MOSFET of another polarity channel having a gate to which a voltage slightly higher than a threshold voltage is applied.
限流要素はそのゲートにスレッシュ電圧より僅かに高い
電圧が印加される一極性チャンネルのＭＯＳＦＥＴから
なり、第２の限流要素はそのゲートにスレッシュ電圧よ
り僅かに高い電圧が印加される他極性チャンネルのＭＯ
ＳＦＥＴからなることを特徴とする出力回路。6. The output circuit according to claim 3, wherein the first current limiting element is a unipolar channel MOSFET having a gate to which a voltage slightly higher than a threshold voltage is applied, and the second current limiting element is A voltage slightly higher than the threshold voltage is applied to its gate
An output circuit comprising an SFET.
限流要素は電流ミラー回路に構成されて所定の電流値の
電流を通電する一極性チャンネルのＭＯＳＦＥＴからな
ることを特徴とする出力回路。7. The output circuit according to claim 1, wherein the first current limiting element is a unipolar channel MOSFET which is configured as a current mirror circuit and conducts a current of a predetermined current value. circuit.
限流要素は電流ミラー回路に構成されて所定の電流値の
電流を通電する他極性チャンネルのＭＯＳＦＥＴからな
ることを特徴とする出力回路。8. The output circuit according to claim 2, wherein the second current limiting element comprises a MOSFET of another polarity channel configured as a current mirror circuit and conducting a current of a predetermined current value. circuit.
限流要素は電流ミラー回路に構成されて所定の電流値の
電流を通電する一極性チャンネルのＭＯＳＦＥＴからな
り、第２の限流要素は電流ミラー回路に構成されて所定
の電流値の電流を通電する他極性チャンネルのＭＯＳＦ
ＥＴからなることを特徴とする出力回路。9. The output circuit according to claim 3, wherein the first current limiting element comprises a MOSFET of a unipolar channel configured as a current mirror circuit to pass a current having a predetermined current value, and a second current limiting element. The element is a MOSF of another polarity channel that is configured as a current mirror circuit and conducts a current of a predetermined current value.
An output circuit comprising an ET.
特徴とする請求項１ないし９の出力回路。10. The output circuit according to claim 1, which is formed as a semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05003644A JP3089873B2 (en) | 1993-01-13 | 1993-01-13 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05003644A JP3089873B2 (en) | 1993-01-13 | 1993-01-13 | Output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06216735A true JPH06216735A (en) | 1994-08-05 |
| JP3089873B2 JP3089873B2 (en) | 2000-09-18 |
Family
ID=11563194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05003644A Expired - Fee Related JP3089873B2 (en) | 1993-01-13 | 1993-01-13 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3089873B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001094406A (en) * | 1999-09-20 | 2001-04-06 | Fuji Electric Co Ltd | Drive circuit |
| JP2004072424A (en) * | 2002-08-06 | 2004-03-04 | Denso Corp | Gate drive circuit of mos gate transistor |
| JP2008103895A (en) * | 2006-10-18 | 2008-05-01 | Fuji Electric Device Technology Co Ltd | Driving circuit of insulated gate type device |
| JP2009141690A (en) * | 2007-12-06 | 2009-06-25 | Fuji Electric Device Technology Co Ltd | Driver circuit |
| JP2011239666A (en) * | 2010-05-04 | 2011-11-24 | Samsung Electronics Co Ltd | Drive circuit, and power supply device and electric apparatus including the same |
| CN102810539A (en) * | 2011-06-03 | 2012-12-05 | 美国亚德诺半导体公司 | Metal oxide semiconductor output circuits and methods of forming the same |
| WO2014199818A1 (en) * | 2013-06-14 | 2014-12-18 | 富士電機株式会社 | Gate-driving circuit |
| JP5791758B1 (en) * | 2014-05-15 | 2015-10-07 | 三菱電機株式会社 | Gate drive circuit |
-
1993
- 1993-01-13 JP JP05003644A patent/JP3089873B2/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001094406A (en) * | 1999-09-20 | 2001-04-06 | Fuji Electric Co Ltd | Drive circuit |
| JP2004072424A (en) * | 2002-08-06 | 2004-03-04 | Denso Corp | Gate drive circuit of mos gate transistor |
| JP2008103895A (en) * | 2006-10-18 | 2008-05-01 | Fuji Electric Device Technology Co Ltd | Driving circuit of insulated gate type device |
| JP2009141690A (en) * | 2007-12-06 | 2009-06-25 | Fuji Electric Device Technology Co Ltd | Driver circuit |
| JP2011239666A (en) * | 2010-05-04 | 2011-11-24 | Samsung Electronics Co Ltd | Drive circuit, and power supply device and electric apparatus including the same |
| CN102810539A (en) * | 2011-06-03 | 2012-12-05 | 美国亚德诺半导体公司 | Metal oxide semiconductor output circuits and methods of forming the same |
| JP2012253326A (en) * | 2011-06-03 | 2012-12-20 | Analog Devices Inc | Metal oxide semiconductor output circuits and methods of forming the same |
| WO2014199818A1 (en) * | 2013-06-14 | 2014-12-18 | 富士電機株式会社 | Gate-driving circuit |
| US9525414B2 (en) | 2013-06-14 | 2016-12-20 | Fuji Electric Co., Ltd. | Gate drive circuit providing constant driving current |
| JP5791758B1 (en) * | 2014-05-15 | 2015-10-07 | 三菱電機株式会社 | Gate drive circuit |
| JP2015220519A (en) * | 2014-05-15 | 2015-12-07 | 三菱電機株式会社 | Gate drive circuit |
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| Publication number | Publication date |
|---|---|
| JP3089873B2 (en) | 2000-09-18 |
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