JPH0691323B2 - Low temperature firing type ceramic multilayer wiring board - Google Patents
Low temperature firing type ceramic multilayer wiring boardInfo
- Publication number
- JPH0691323B2 JPH0691323B2 JP1044261A JP4426189A JPH0691323B2 JP H0691323 B2 JPH0691323 B2 JP H0691323B2 JP 1044261 A JP1044261 A JP 1044261A JP 4426189 A JP4426189 A JP 4426189A JP H0691323 B2 JPH0691323 B2 JP H0691323B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- multilayer wiring
- wiring board
- ceramic multilayer
- low temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、セラミック多層配線基板に関し、更に詳細に
は、抵抗体を内蔵した低温焼成型セラミック多層配線基
板に関するものである。Description: TECHNICAL FIELD The present invention relates to a ceramic multilayer wiring board, and more particularly to a low temperature firing type ceramic multilayer wiring board having a built-in resistor.
（従来の技術） 従来の低温焼成型セラミック多層配線基板は、Al2O3−
ガラス系等を主成分とするセラミック材料にバインダを
加えてセラミックグリーンシートを作成し、該シートの
所定の箇所にスルーホールを形成したのち、該シートの
主面および上記スルーホール部分にAg等の導電材料ペー
ストを用いて所定の配線パターンを形成し、これらのシ
ートを複数枚積層・圧着し、得られた積層体を所定の寸
法に切断したのち、大気中、900℃程度の温度で焼成す
ることにより形成される。(Prior Art) A conventional low temperature firing type ceramic multilayer wiring board is made of Al 2 O 3 −.
A binder is added to a ceramic material containing glass or the like as a main component to form a ceramic green sheet, and through holes are formed at predetermined portions of the sheet, and then Ag or the like is formed on the main surface of the sheet and the through hole portion. A predetermined wiring pattern is formed using a conductive material paste, a plurality of these sheets are laminated and pressure-bonded, the obtained laminated body is cut into a predetermined dimension, and then fired in the atmosphere at a temperature of about 900 ° C. It is formed by
上記セラミック多層配線基板の内部に抵抗体を形成する
場合、上記のごとく配線パターンを形成したセラミック
グリーンシート上にさらにRuO2−ガラス系の抵抗材料ペ
ーストを所定の形状に印刷し、これらのシートを上記と
同様に複数枚積層・圧着し、得られた積層体を所定の寸
法に切断したのち、上記と同様に焼成することにより得
られる。When a resistor is formed inside the ceramic multilayer wiring board, RuO 2 -glass-based resistance material paste is further printed in a predetermined shape on the ceramic green sheet on which the wiring pattern is formed as described above, and these sheets are formed. It can be obtained by laminating and pressing a plurality of sheets in the same manner as described above, cutting the obtained laminated body to a predetermined size, and then firing in the same manner as above.
（発明が解決しようとする課題） しかしながら、上記従来の抵抗体を内蔵したセラミック
多層配線基板は、上記基板を焼成する際に避けることの
できない炉内の温度や雰囲気等の条件の微妙な変動によ
り、RuO2−ガラス系の抵抗体材料の反応状態が大きく影
響を受け、その結果、上記抵抗体の抵抗値にばらつきが
生じ、多層配線基板の製品歩留りが大きく低下してしま
うという問題点が発生していた。(Problems to be Solved by the Invention) However, the above-mentioned conventional ceramic multilayer wiring board with a built-in resistor is subject to subtle fluctuations in conditions such as temperature and atmosphere in the furnace that cannot be avoided when firing the board. , RuO 2 − The reaction state of the glass-based resistor material is greatly affected, and as a result, the resistance value of the above-mentioned resistor varies, resulting in a problem that the product yield of the multilayer wiring board is significantly reduced. Was.
本発明の目的は、上記従来の問題点を解決して、内蔵す
る抵抗体の抵抗値が焼成時の条件変動の影響を受け難い
低温焼成型セラミック多層配線基板を提供することにあ
る。An object of the present invention is to solve the above conventional problems and provide a low temperature firing type ceramic multilayer wiring board in which the resistance value of a built-in resistor is not easily affected by fluctuations in conditions during firing.
（課題を解決するための手段） 本発明は、AgもしくはAg合金を配線導体として用いた低
温焼成型セラミック多層配線基板において、ガラス材料
を含まないAg-Pd系合金からなる抵抗体を内蔵している
ことを特徴とするものである。(Means for Solving the Problems) The present invention relates to a low temperature firing type ceramic multilayer wiring board using Ag or an Ag alloy as a wiring conductor, in which a resistor made of an Ag-Pd-based alloy containing no glass material is incorporated. It is characterized by being present.
（作用） 本発明の低温焼成型セラミック多層配線基板において
は、原子比が1:1前後で、比較的高い電気抵抗率を示す
ガラス材料を含まないAgとPdの合金を抵抗体として用い
ることにより、該合金のそれぞれの成分が固溶状態にあ
るため、焼成条件等の変動に対して安定である。(Operation) In the low temperature firing type ceramic multilayer wiring board of the present invention, by using an alloy of Ag and Pd having an atomic ratio of about 1: 1 and not containing a glass material showing a relatively high electrical resistivity as a resistor, Since each component of the alloy is in a solid solution state, it is stable against changes in firing conditions and the like.
（実施例） 実施例１ Al2O3 45wt%、SiO2 35wt%、B2O3 8wt%、CaO 5wt%、MgO 3.5w
t%、Cr2O3 3wt%、Li2O 0.5wt%からなる低温焼成セラミッ
ク材料粉末に有機バインダとしてポリビニルブチラール
を8wt％、溶剤としてイソプロピルアルコールとトルエ
ンの１対１混合液を100wt％、可塑剤としてジブチルフ
タレートを6wt％添加して混合し、得られたスラリをド
クタブレード法によりシート状に形成し、得られたセラ
ミックグリーンシートを所定の大きさに切断し、必要な
箇所にビアホールを形成した。(Example) Example 1 Al 2 O 3 45 wt%, SiO 2 35 wt%, B 2 O 3 8 wt%, CaO 5 wt%, MgO 3.5 w
Low-temperature fired ceramic material powder consisting of t%, Cr 2 O 3 3wt%, Li 2 O 0.5wt%, polyvinyl butyral as organic binder 8wt%, solvent 1: 1 mixture of isopropyl alcohol and toluene 100wt%, plastic Add 6 wt% of dibutyl phthalate as an agent and mix it.The obtained slurry is formed into a sheet by the doctor blade method, the obtained ceramic green sheet is cut into a predetermined size, and a via hole is formed at a required location. did.
しかる後、Agを主成分とする導体ペーストで、上記セラ
ミックグリーンシート上に配線パターンを印刷した。こ
の時、上記ビアホールは導体ペーストで充填される。After that, a wiring pattern was printed on the ceramic green sheet with a conductor paste containing Ag as a main component. At this time, the via holes are filled with a conductive paste.
次に、内部抵抗を形成するために、AgとPdを重量比で5
0:50（原子比で約5:5）の割合で含む合金の粉末と有機
ビヒクルからなる抵抗体ペーストで、上記セラミックグ
リーンシート上に所定の形状に印刷した。この形状は、
具体的には、幅0.25mm、長さ20mmの線状パターンであ
る。Next, Ag and Pd are mixed in a weight ratio of 5 to form an internal resistance.
A resistor paste composed of an alloy powder containing 0:50 (atomic ratio of about 5: 5) and an organic vehicle was printed in a predetermined shape on the ceramic green sheet. This shape is
Specifically, it is a linear pattern having a width of 0.25 mm and a length of 20 mm.
このようにして得られたシートを複数枚重ね、100℃、2
50kg/cm2で10分間熱圧着したのち、50mm×30mmの寸法に
切断し、セラミックグリーンシート積層体を得た。Multiple sheets obtained in this way are stacked and
After thermocompression bonding at 50 kg / cm 2 for 10 minutes, it was cut into a size of 50 mm × 30 mm to obtain a ceramic green sheet laminate.
こうして得られた積層体を、大気中で700℃まで４℃／
分で昇温し、700℃から920℃まで20℃／分で昇温し、92
0℃で20分キープしたのち、再び室温まで−20℃／分で
降温するパターンで焼成して、セラミック多層配線基板
を得た。こうして得られた基板の内部に形成された抵抗
体について、抵抗体の単位長さ（1cm）当たりの抵抗値
を測定したところ、25Ωであった。The laminate thus obtained was heated to 700 ° C in the atmosphere at 4 ° C /
The temperature rises in minutes, from 700 ° C to 920 ° C at 20 ° C / min, and
After being kept at 0 ° C. for 20 minutes, it was fired again in a pattern in which the temperature was lowered to room temperature at −20 ° C./minute to obtain a ceramic multilayer wiring board. With respect to the resistor formed inside the substrate thus obtained, the resistance value per unit length (1 cm) of the resistor was measured and found to be 25Ω.
この方法を用いて、50Ωの抵抗体を20本内蔵するセラミ
ック多層配線基板を100個作成し、それぞれの抵抗体の
抵抗値を測定した後、20本の抵抗体のすべてが40Ω〜60
Ωの規格内のセラミック多層配線基板を良品として製品
歩留りを算出した結果、99％であった。Using this method, 100 ceramic multilayer wiring boards containing 20 50Ω resistors were created, and after measuring the resistance value of each resistor, all 20 resistors were 40Ω to 60Ω.
The product yield was calculated as 99% when the ceramic multilayer wiring board within the standard of Ω was regarded as a good product.
実施例２ 抵抗体ペーストのAgとPdの合金のAgとPdの重量比を6:4
（AgとPdの原子比で約6:4）に変え、抵抗体の長さを25m
mにしたこと以外は上記実施例１と同様にしてセラミッ
ク多層配線基板を得た。こうして得られた基板の内部に
形成された抵抗体について、抵抗体の単位長さ（1cm）
当たりの抵抗値を測定したところ、20Ωであった。この
方法を用いて、50Ωの抵抗体を20本内蔵するセラミック
多層配線基板を100個作成し、それぞれの抵抗体の抵抗
値を測定したところ、製品歩留りは99％であった。Example 2 The weight ratio of Ag and Pd of the resistor paste Ag and Pd alloy was set to 6: 4.
(The atomic ratio of Ag and Pd is about 6: 4), and the length of the resistor is 25m.
A ceramic multilayer wiring board was obtained in the same manner as in Example 1 except that the thickness was changed to m. Unit length of the resistor (1 cm) for the resistor formed inside the substrate thus obtained
When the resistance value per contact was measured, it was 20Ω. Using this method, 100 ceramic multilayer wiring boards containing 20 50Ω resistors were created, and the resistance value of each resistor was measured. The product yield was 99%.
実施例３ 抵抗体ペーストのAgとPdの合金のAgとPdの重量比を3:7
（AgとPdの原子比で約3:7）に変え、抵抗体の長さを25m
mにしたこと以外は上記実施例１と同様にしてセラミッ
ク多層配線基板を得た。こうして得られた基板の内部に
形成された抵抗体について、抵抗体の単位長さ（1cm）
当たりの抵抗値を測定したところ、20Ωであった。この
方法を用いて、50Ωの抵抗体を20本内蔵するセラミック
多層配線基板を100個作成し、それぞれの抵抗体の抵抗
値を測定したところ、製品歩留りは99％であった。Example 3 The weight ratio of Ag and Pd in the resistor paste Ag and Pd alloy was 3: 7.
(The atomic ratio of Ag and Pd is about 3: 7), and the length of the resistor is 25m.
A ceramic multilayer wiring board was obtained in the same manner as in Example 1 except that the thickness was changed to m. Unit length of the resistor (1 cm) for the resistor formed inside the substrate thus obtained
When the resistance value per contact was measured, it was 20Ω. Using this method, 100 ceramic multilayer wiring boards containing 20 50Ω resistors were created, and the resistance value of each resistor was measured. The product yield was 99%.
実施例４ 抵抗体ペーストを、Ag単体とPd単体を重量比で1:1（原
子比で約1:1）の割合で含む粉末と有機ビヒクルからな
るものに変えたこと以外は上記実施例１と同様にしてセ
ラミック多層配線基板を得た。こうして得られた基板の
内部に形成された抵抗体について、抵抗体の単位長さ
（1cm）当たりの抵抗値を測定したところ、25Ωであっ
た。この方法を用いて、50Ωの抵抗体を20本内蔵するセ
ラミック多層配線基板を100個作成し、それぞれの抵抗
体の抵抗値を測定したところ、製品歩留りは99％であっ
た。Example 4 Example 1 described above except that the resistor paste was changed to a powder containing an Ag simple substance and a Pd simple substance in a weight ratio of 1: 1 (atomic ratio of about 1: 1) and an organic vehicle. A ceramic multilayer wiring board was obtained in the same manner as. With respect to the resistor formed inside the substrate thus obtained, the resistance value per unit length (1 cm) of the resistor was measured and found to be 25Ω. Using this method, 100 ceramic multilayer wiring boards containing 20 50Ω resistors were created, and the resistance value of each resistor was measured. The product yield was 99%.
比較例 抵抗体ペーストを、RuO2−ガラス系を主成分とする抵抗
材料と有機ビヒクルからなるものに変えたこと以外は上
記実施例１と同様にして、50Ωの抵抗体を20本内蔵する
セラミック多層配線基板を100個作成したところ、製品
歩留りは73％であった。Comparative Example A ceramic containing 20 resistors of 50 Ω in the same manner as in Example 1 except that the resistor paste was changed to a resistor material containing RuO 2 -glass as a main component and an organic vehicle. When 100 multi-layer wiring boards were created, the product yield was 73%.
以上の実施例および比較例の結果に示される通り、本発
明の実施例では、所望の抵抗値を有する抵抗体を内蔵し
た低温焼成型セラミック多層配線基板を高い歩留りで得
られたのに対し、従来の抵抗体材料を用いた比較例で
は、満足な抵抗値を有する抵抗体を内蔵したセラミック
多層配線基板を高い歩留りで得ることはできなかった。As shown in the results of the above Examples and Comparative Examples, in the examples of the present invention, while low-temperature firing type ceramic multilayer wiring substrate incorporating a resistor having a desired resistance value was obtained with a high yield, In the comparative example using the conventional resistor material, it was not possible to obtain a ceramic multilayer wiring board incorporating a resistor having a satisfactory resistance value with a high yield.
なお、Ag-Pd系系合金からなる抵抗体で得ることが可能
な抵抗値の範囲は、従来の厚膜抵抗体で得られる範囲に
比べてかなり限定されるが、例えば高周波回路で終端抵
抗として用いられる50Ω前後の抵抗体等としては、十分
に使用可能である。Note that the range of resistance values that can be obtained with a resistor made of an Ag-Pd-based alloy is considerably limited compared to the range that can be obtained with a conventional thick film resistor. It can be sufficiently used as a resistor of around 50Ω used.
また、上記実施例に示す通り、AgとPdの原子比を6:4か
ら3:7とした場合には比較的高い抵抗値が得られるが、
本発明はこれに限定されるものでなく、これ以外の範囲
でも本発明の効果は得られる。Further, as shown in the above examples, when the atomic ratio of Ag and Pd is 6: 4 to 3: 7, a relatively high resistance value is obtained,
The present invention is not limited to this, and the effects of the present invention can be obtained in other ranges.
また、他の公知の微量添加物を加えることにより、相応
の添加効果を得ることができる。Further, by adding other known trace additives, it is possible to obtain a corresponding addition effect.
更に、実施例４に示したように、抵抗体ペーストの原材
料に、Ag粉末とPd粉末を混合して用いても、焼成の過程
で合金化がおこり、最初から合金の粉末を用いたものと
同様な効果が得られる。Further, as shown in Example 4, even if Ag powder and Pd powder were mixed and used as the raw material of the resistor paste, alloying occurred in the process of firing, and the alloy powder was used from the beginning. Similar effects are obtained.
（効果） 本発明の低温焼成型セラミック多層配線基板によれば、
焼成時の条件変動に対して安定な所望の抵抗値を有する
抵抗体を内蔵し、製品歩留りのよい小型かつ高密度のセ
ラミック多層配線基板を得ることができる。(Effect) According to the low temperature firing type ceramic multilayer wiring board of the present invention,
It is possible to obtain a small-sized and high-density ceramic multilayer wiring board with a high product yield by incorporating a resistor having a desired resistance value that is stable against fluctuations in conditions during firing.
Claims (1)
低温焼成型セラミック多層配線基板において、ガラス材
料を含まないAg-Pd系合金からなる抵抗体を内蔵してい
ることを特徴とする低温焼成型セラミック多層配線基
板。1. A low temperature firing type ceramic multi-layer wiring board using Ag or an Ag alloy as a wiring conductor, wherein a low temperature firing method comprising a resistor made of an Ag-Pd type alloy containing no glass material. Type ceramic multilayer wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1044261A JPH0691323B2 (en) | 1989-02-25 | 1989-02-25 | Low temperature firing type ceramic multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1044261A JPH0691323B2 (en) | 1989-02-25 | 1989-02-25 | Low temperature firing type ceramic multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02224298A JPH02224298A (en) | 1990-09-06 |
| JPH0691323B2 true JPH0691323B2 (en) | 1994-11-14 |
Family
ID=12686574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1044261A Expired - Fee Related JPH0691323B2 (en) | 1989-02-25 | 1989-02-25 | Low temperature firing type ceramic multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691323B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006060634A1 (en) * | 2006-12-21 | 2008-06-26 | Robert Bosch Gmbh | Method for producing an electrical resistance on a substrate |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4957366A (en) * | 1972-10-04 | 1974-06-04 | ||
| JPS5543275A (en) * | 1978-09-22 | 1980-03-27 | Ntn Toyo Bearing Co Ltd | Closed type automatic valve clearance controller |
| JPS61274397A (en) * | 1985-05-30 | 1986-12-04 | 株式会社住友金属セラミックス | Low temperature baked ceramic substrate and manufacture thereof |
| JPH0719968B2 (en) * | 1987-04-20 | 1995-03-06 | 株式会社日立製作所 | Method for manufacturing multi-layer hybrid IC substrate |
-
1989
- 1989-02-25 JP JP1044261A patent/JPH0691323B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02224298A (en) | 1990-09-06 |
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