JPH0691234B2 - Photoelectric conversion device - Google Patents
Photoelectric conversion deviceInfo
- Publication number
- JPH0691234B2 JPH0691234B2 JP61125937A JP12593786A JPH0691234B2 JP H0691234 B2 JPH0691234 B2 JP H0691234B2 JP 61125937 A JP61125937 A JP 61125937A JP 12593786 A JP12593786 A JP 12593786A JP H0691234 B2 JPH0691234 B2 JP H0691234B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- diffusion layer
- region
- photoelectric conversion
- conversion device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 12
- 239000010410 layer Substances 0.000 description 51
- 238000009792 diffusion process Methods 0.000 description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000002184 metal Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14681—Bipolar transistor imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14806—Structural or functional details thereof
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Photovoltaic Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は光電変換装置に係り、特にトランジスタの第一
導電型の半導体からなる制御電極領域に電荷を蓄積する
光電変換装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device that accumulates charges in a control electrode region made of a first conductivity type semiconductor of a transistor.
従来、半導体撮像装置としてはCCD型半導体撮像装置,MO
S型半導体撮像装置等があるが、MOS型半導体撮像装置は
高集積化の点で、CCD型半導体撮像装置は製造歩留の点
で問題を残している。Conventionally, as a semiconductor image pickup device, a CCD type semiconductor image pickup device, MO
Although there are S-type semiconductor image pickup devices and the like, the MOS type semiconductor image pickup device has a problem in terms of high integration, and the CCD type semiconductor image pickup device has a problem in terms of manufacturing yield.
これらの問題を解決するものとして、トランジスタの制
御電極領域に蓄積電荷を発生させ、この蓄積電荷を制御
することによって光信号の検出を行う光電変換装置を用
いた半導体撮像装置がある。As a solution to these problems, there is a semiconductor imaging device using a photoelectric conversion device that generates accumulated charges in the control electrode region of a transistor and controls the accumulated charges to detect an optical signal.
以下、この光電変換装置について説明する。The photoelectric conversion device will be described below.
第３図は上記光電変換装置の一例センサセルの説明図で
あり、（ａ）は平面図、（ｂ）は平面図（ａ）のＡ−
Ａ′断面図である。3A and 3B are explanatory views of a sensor cell as an example of the photoelectric conversion device, where FIG. 3A is a plan view and FIG. 3B is a plan view of FIG.
It is an A'cross section figure.
第３図において、１はセンサセルで大きさは基本寸法
（最小加工寸法であり、ここでは金属配線11,13のコン
タクトホールの一辺の長さａ）の10×５倍である。セン
サセル１は次のような構成をとる。２はＮ型シリコン基
板であり、このＮ型シリコン基板２には、Ｎ型分離拡散
層3,P型ベース拡散層5,P型ソース拡散層7,P型ドレイン
拡散層６が設けられ、さらに前記Ｐ型ベース拡散層５中
には、Ｎ型エミッタ拡散層８が設けられる。Ｎ型エミッ
タ拡散層8,P型ベース拡散層5,N型シリコン基板２はNPN
型バイポーラトランジスタを構成し、またＰ型ソース拡
散層7,P型ドレイン拡散層６及びゲート酸化膜12を介し
て設けられたゲート電極９でＰ型MOSトランジスタを構
成する。11,13は金属配線である。In FIG. 3, reference numeral 1 denotes a sensor cell having a size of 10 × 5 times the basic size (the minimum processing size, which is the length a of one side of the contact hole of the metal wirings 11 and 13 here). The sensor cell 1 has the following configuration. Reference numeral 2 denotes an N-type silicon substrate. The N-type silicon substrate 2 is provided with an N-type isolation diffusion layer 3, a P-type base diffusion layer 5, a P-type source diffusion layer 7, and a P-type drain diffusion layer 6, and An N-type emitter diffusion layer 8 is provided in the P-type base diffusion layer 5. N-type emitter diffusion layer 8, P-type base diffusion layer 5 and N-type silicon substrate 2 are NPN
Type bipolar transistor, and a P-type MOS transistor is formed by the gate electrode 9 provided via the P-type source diffusion layer 7, the P-type drain diffusion layer 6 and the gate oxide film 12. 11, 13 are metal wiring.
以下、上記光電変換装置の動作について述べる。The operation of the photoelectric conversion device will be described below.
光が入射されると、半導体内に光量に対応した電子−正
孔対が発生し、電子は正電位にバイアスされたＮ型シリ
コン基板２側から流れ出してしまうが、正孔はＰ型ベー
ス拡散層５に蓄積される（蓄積動作）。When light is incident, electron-hole pairs corresponding to the amount of light are generated in the semiconductor, and the electrons flow out from the N-type silicon substrate 2 side biased to a positive potential, but the holes diffuse into the P-type base. It is accumulated in the layer 5 (accumulation operation).
蓄積された正孔によってベース電位は上昇する。Ｎ型エ
ミッタ拡散層８と、コレクタであるＮ型シリコン基板２
との間に電圧を印加し、またゲート電極９に正の電圧を
印加することによって、更にベース電位を上昇させる。
このベース電位の変化をコレクタ電流として読み出すこ
とで、入射光量に対応した電気信号を得ることができる
（読み出し動作）。また、Ｐ型ベース拡散層５に蓄積さ
れた電荷を除去するには、前記Ｐ型MOSトランジスタを
オンすることにより、金属配線13を通して外部に電荷を
逃せばよい（リフレッシュ動作）。以後上述の蓄積、読
み出し、リフレッシュという各動作が繰り返される。The base potential rises due to the accumulated holes. N-type emitter diffusion layer 8 and N-type silicon substrate 2 which is a collector
By applying a voltage between the gate electrode 9 and the gate electrode 9 and by applying a positive voltage to the gate electrode 9, the base potential is further increased.
By reading this change in the base potential as the collector current, an electric signal corresponding to the amount of incident light can be obtained (reading operation). To remove the charges accumulated in the P-type base diffusion layer 5, the P-type MOS transistor may be turned on to let the charges escape to the outside through the metal wiring 13 (refresh operation). Thereafter, the above-mentioned operations of accumulation, reading and refresh are repeated.
上記従来例においては、リフレッシュ動作がＰ型MOSト
ランジスタを用いて行われるが、センサセル１の面積が
Ｐ型MOSトランジスタの為に増大し、高集積化には不利
であった。In the above-mentioned conventional example, the refresh operation is performed using the P-type MOS transistor, but the area of the sensor cell 1 is increased due to the P-type MOS transistor, which is disadvantageous for high integration.
高集積化が可能なものとしてはＰ型MOSトランジスタを
用いず、Ｐ型ベース拡散層５上のゲート酸化膜12上に電
極を設け、この電極に電圧を印加することで、蓄積電荷
を逃がすリフレッシュ方式がある。しかしながらこの方
式においては、ベース電位が明確に固定されず光電変換
特性の直線性が悪くなる問題点を有していた。As a device that can be highly integrated, a P-type MOS transistor is not used, an electrode is provided on the gate oxide film 12 on the P-type base diffusion layer 5, and a voltage is applied to this electrode to refresh accumulated charges. There is a method. However, this method has a problem that the base potential is not clearly fixed and the linearity of the photoelectric conversion characteristic is deteriorated.
本発明の目的は光電変換特性の直線性を維持し且つ高集
積化に適する光電変換装置を提供することにある。An object of the present invention is to provide a photoelectric conversion device that maintains linearity of photoelectric conversion characteristics and is suitable for high integration.
上記の問題点は、トランジスタの第一導電型の半導体か
らなる制御電極領域に電荷を蓄積する光電変換装置にお
いて、 半導体基板上に設けられた第一導電型の半導体からなる
埋込領域と、該埋込領域及び該基板上に設けられた該第
一導電型とは反対の第二導電型の半導体からなる半導体
領域と、を具備し、 該制御電極領域が該半導体領域を介して該埋込領域上に
位置しており、該埋込領域に、該制御電極領域に蓄積さ
れた電荷を該埋込領域に逃がす為の所定の電圧を印加す
る構成の本発明の光電変換装置によって解決される。The above problem is that in a photoelectric conversion device that accumulates charges in a control electrode region made of a semiconductor of the first conductivity type of a transistor, an embedded region made of a semiconductor of the first conductivity type provided on a semiconductor substrate, A semiconductor region made of a semiconductor of a second conductivity type opposite to the first conductivity type provided on the substrate, wherein the control electrode region is embedded through the semiconductor region. A photoelectric conversion device according to the present invention, which is located on a region and is configured to apply a predetermined voltage to the buried region so as to allow the charges accumulated in the control electrode region to escape to the buried region, is solved. .
本発明は、埋込領域と、この埋込領域上に形成された半
導体領域と、この半導体領域上に設けられた制御電極領
域とでトランジスタを構成し、前記埋込領域に電圧を印
加してパンチスルーを起こさせ、制御電極領域に蓄積さ
れた電荷を埋込領域に逃がすことによって光電変換装置
のリフレッシュ動作を行わせようとするものである。According to the present invention, a transistor is composed of a buried region, a semiconductor region formed on the buried region, and a control electrode region provided on the semiconductor region, and a voltage is applied to the buried region. Punch through is caused to allow the charge accumulated in the control electrode region to escape to the buried region so that the photoelectric conversion device is refreshed.
以下、本発明の実施例を図面を用いて詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明の光電変換装置のセンサセルの説明図で
あり、（ａ）は平面図，（ｂ）は平面図（ａ）のＡ−
Ａ′断面図である。なお、本実施例において制御電極領
域に電荷を蓄積するトランジスタはバイポーラトランジ
スタであり、制御電極領域はベース領域である。FIG. 1 is an explanatory view of a sensor cell of a photoelectric conversion device of the present invention, (a) is a plan view, (b) is a plan view of A-.
It is an A'cross section figure. In this embodiment, the transistor that accumulates charges in the control electrode region is a bipolar transistor, and the control electrode region is the base region.
第１図において、14はセンサセルであり、基本寸法（こ
こでは金属配線23のコンタクトホールの一辺の長さｂ）
の５×４倍であり、後述するように素子分離にLOCOS法
を用いるが、第３図に示した従来例と比べて面積が1/2.
5に縮小されている。センサセル14は以下の製造方法に
よって形成される。まずCZP（100）１Ω−cmシリコン基
板25にシート抵抗20Ω／□のＮ型埋込拡散層24を形成し
不純物濃度1015/cm3のＰ型エピタキシャル成長層15を厚
さ3.5μｍ形成する。次いでLOCOS法により、Ｐ型分離拡
散層16及び厚さ１μｍのフィールド酸化膜17を形成す
る。その後、深さ0.8μｍの制御電極領域となるＮ型ベ
ース拡散層18を形成後、厚さ500Åの酸化膜等の絶縁膜1
9を形成し、その上に厚さ4000Åのポリシリコンの電極2
0を形成する。この電極20はＮ型ベース拡散層18に対す
るゲート電極となる。次いでゲートセルフアライン法に
より深さ0.3μｍのＰ型エミッタ拡散層21を形成する。
その後層間絶縁膜22,金属配線23を形成する。Ｐ型エミ
ッタ拡散層21,N型ベース拡散層18,P型エピタキシャル成
長層15はPNP型バイポーラトランジスタを形成し、電極2
0によって蓄積電荷（電子）の制御を行う。In FIG. 1, 14 is a sensor cell, and has a basic dimension (here, the length b of one side of the contact hole of the metal wiring 23).
5 × 4 times that of LOCOS, which is used for element isolation as will be described later, but the area is half that of the conventional example shown in FIG.
It has been reduced to 5. The sensor cell 14 is formed by the following manufacturing method. First, an N type buried diffusion layer 24 having a sheet resistance of 20 Ω / □ is formed on a CZP (100) 1Ω-cm silicon substrate 25, and a P type epitaxial growth layer 15 having an impurity concentration of 10 15 / cm 3 is formed to a thickness of 3.5 μm. Next, the P-type isolation diffusion layer 16 and the field oxide film 17 having a thickness of 1 μm are formed by the LOCOS method. After that, an N-type base diffusion layer 18 to be a control electrode region having a depth of 0.8 μm is formed, and then an insulating film 1 such as an oxide film having a thickness of 500 Å is formed.
Form 9 and on it a 4000 Å thick polysilicon electrode 2
Form 0. This electrode 20 becomes a gate electrode for the N-type base diffusion layer 18. Then, a P-type emitter diffusion layer 21 having a depth of 0.3 μm is formed by the gate self-alignment method.
After that, the interlayer insulating film 22 and the metal wiring 23 are formed. The P-type emitter diffusion layer 21, the N-type base diffusion layer 18, and the P-type epitaxial growth layer 15 form a PNP-type bipolar transistor, and the electrode 2
0 controls the accumulated charge (electrons).
前記Ｎ型埋込拡散層24,P型エピタキシャル成長層15,N型
ベース拡散層18はNPN型の縦型トランジスタあるいはＮ
型JFETを構成する。Ｎ型ベース拡散層18に蓄積された光
電荷はＮ型埋込拡散層24に正電圧を印加し、前記Ｎ型ベ
ース拡散層18とＮ型埋込拡散層24間をパンチスルーさせ
ることによって、前記Ｎ型埋込拡散層24を通って、排出
される。The N type buried diffusion layer 24, the P type epitaxial growth layer 15, and the N type base diffusion layer 18 are NPN type vertical transistors or N type.
Configure a type JFET. The photocharges accumulated in the N-type base diffusion layer 18 are applied with a positive voltage to the N-type buried diffusion layer 24 to punch through between the N-type base diffusion layer 18 and the N-type buried diffusion layer 24. It is discharged through the N-type buried diffusion layer 24.
本発明の光電変換装置はＮ型ベース拡散層に蓄積された
電荷を逃がすためのMOS型トランジスタを形成すること
はないのでセル寸法を縮小させることができ、基本寸法
２μｍでは10×８＝80μm2となり基本寸法が同等である
256 k DRAMのセル面積70μm2と比べても遜色のない値と
なる。Since the photoelectric conversion device of the present invention does not form a MOS transistor for releasing the charge accumulated in the N-type base diffusion layer, the cell size can be reduced. At a basic size of 2 μm, 10 × 8 = 80 μm 2 And have the same basic dimensions
The value is comparable to the cell area of 70 μm 2 of 256 k DRAM.
また、本発明の光電変換装置はオーバーフロードレイン
構造でもある。The photoelectric conversion device of the present invention also has an overflow drain structure.
第２図は上記実施例の光電変換装置のポテンシャルの特
性図であり、第２図（ａ）は光電荷が蓄積されていない
状態、第２図（ｂ）は過剰な光電荷が蓄積された状態を
示す。FIG. 2 is a potential characteristic diagram of the photoelectric conversion device of the above-described embodiment. FIG. 2 (a) shows a state in which no photocharge is accumulated, and FIG. 2 (b) shows an excessive photocharge. Indicates the status.
第２図（ａ），（ｂ）において、26はＰ型エミッタ拡散
層21のエネルギーレベル,27はＮ型ベース拡散層18のエ
ネルギーレベル,28はＰ型エピタキシャル成長層15のエ
ネルギーレベル,30はＮ型埋込拡散層24のエネルギーレ
ベルを示す。In FIGS. 2A and 2B, 26 is the energy level of the P-type emitter diffusion layer 21, 27 is the energy level of the N-type base diffusion layer 18, 28 is the energy level of the P-type epitaxial growth layer 15, and 30 is N. The energy level of the buried buried diffusion layer 24 is shown.
Ｐ型エピタキシャル成長層15近傍で発生した光電荷であ
る電子は、拡散により、Ｎ型ベース拡散層18に蓄積され
る。電子が蓄積されると、第２図（ｂ）に示すようにＮ
型ベース拡散層18のエネルギーレベル27は上昇し、Ｐ型
エピタキシャル成長層15のエネルギーレベル28とほぼ同
レベルとなり、電子の蓄積は行われなくなる。即ち、過
剰な電子はＮ型埋込拡散層24に移動することとなる。Electrons that are photocharges generated in the vicinity of the P-type epitaxial growth layer 15 are accumulated in the N-type base diffusion layer 18 by diffusion. When the electrons are accumulated, as shown in FIG.
The energy level 27 of the type base diffusion layer 18 rises to almost the same level as the energy level 28 of the P type epitaxial growth layer 15, and electrons are not accumulated. That is, excess electrons move to the N-type buried diffusion layer 24.
本発明はＮ型埋込拡散層24に電圧を印加させ、Ｎ型ベー
ス拡散層18に蓄積された電荷をパンチスルーさせて、Ｎ
型埋込拡散層24に移動させるものであり、光電変換特性
の直線性を保ち、且つブルーミング耐性に関しても非常
に良好な光電変換装置を与えることができる。The present invention applies a voltage to the N-type buried diffusion layer 24 to punch through the charge accumulated in the N-type base diffusion layer 18,
The photoelectric conversion device is moved to the embedded buried diffusion layer 24, and it is possible to provide a photoelectric conversion device that maintains the linearity of the photoelectric conversion characteristics and has very good blooming resistance.
なお、上記実施例において、フィールド酸化膜17にLOCO
S法を用いず、従来のホトエッチング法を使用しても良
い。また必要ならば、シリコン基板をＰ型でなくＮ型に
することも可能である。In the above-mentioned embodiment, the LOCO is formed on the field oxide film 17.
A conventional photoetching method may be used instead of the S method. If necessary, the silicon substrate can be made N-type instead of P-type.
本発明の他の実施例として、上記実施例の半導体層の導
電型を全て反対導電型として光電変換装置を構成しても
よい。この場合、Ｎ型ベース拡散層18をＰ型とした時に
は、ベース領域形成後、ドーパントであるボロンが熱処
理を受けることによりフィールド酸化膜に吸出され、界
面濃度が低下し、そのためチャンネルリークが生じやす
くなるために更に対策を必要とする。As another embodiment of the present invention, the photoelectric conversion device may be configured such that the conductivity types of the semiconductor layers of the above embodiments are all opposite conductivity types. In this case, when the N-type base diffusion layer 18 is of P-type, after the base region is formed, boron as a dopant is subjected to heat treatment and is absorbed into the field oxide film, and the interface concentration is lowered, so that channel leakage easily occurs. Therefore, further measures are required.
以上、詳細に説明したように、本発明によれば、制御電
極領域に蓄積された電荷を埋込領域に逃がすことによっ
て、光電変換特性の直線性を損うことなく、またMOSト
ランジスタ等を設けることがないので高集積化が容易
で、安価な製造が可能な光電変換装置を提供することが
できる。As described in detail above, according to the present invention, the charge accumulated in the control electrode region is allowed to escape to the embedded region, so that the linearity of the photoelectric conversion characteristic is not impaired and a MOS transistor or the like is provided. Therefore, it is possible to provide a photoelectric conversion device which can easily be highly integrated and can be manufactured at low cost.
第１図（ａ），（ｂ）は本発明の光電変換装置のセンサ
セルの説明図である。 第２図（ａ），（ｂ）は上記光電変換装置のポテンシャ
ルの特性図である。 第３図（ａ），（ｂ）は従来の光電変換装置の一例のセ
ンサセルの説明図である。 14……センサセル、15……Ｐ型エピタキシャル成長層、
16……Ｐ型分離拡散層、17……フィールド酸化膜、18…
…Ｎ型ベース拡散層、19……絶縁膜、20……電極、21…
…Ｐ型エミッタ拡散層、22……層間絶縁膜、23……金属
配線、24……Ｎ型埋込拡散層、25……Ｐ型シリコン基
板。1 (a) and 1 (b) are explanatory views of a sensor cell of the photoelectric conversion device of the present invention. 2A and 2B are potential characteristic diagrams of the photoelectric conversion device. 3 (a) and 3 (b) are explanatory views of a sensor cell as an example of a conventional photoelectric conversion device. 14 …… Sensor cell, 15 …… P-type epitaxial growth layer,
16 ... P-type isolation diffusion layer, 17 ... Field oxide film, 18 ...
… N-type base diffusion layer, 19… Insulating film, 20… Electrode, 21…
… P type emitter diffusion layer, 22 …… interlayer insulating film, 23 …… metal wiring, 24 …… N type buried diffusion layer, 25 …… P type silicon substrate.
Claims (1)
る制御電極領域に電荷を蓄積する光電変換装置におい
て、 半導体基板上に設けられた第一導電型の半導体からなる
埋込領域と、該埋込領域及び該基板上に設けられた該第
一導電型とは反対の第二導電型の半導体からなる半導体
領域と、を具備し、 該制御電極領域が該半導体領域を介して該埋込領域上に
位置しており、該埋込領域に、該制御電極領域に蓄積さ
れた電荷を該埋込領域に逃がす為の所定の電圧を印加す
る構成の光電変換装置。1. A photoelectric conversion device for accumulating charges in a control electrode region made of a first conductivity type semiconductor of a transistor, comprising: a buried region made of a first conductivity type semiconductor provided on a semiconductor substrate; An embedded region and a semiconductor region provided on the substrate and made of a semiconductor of a second conductivity type opposite to the first conductivity type, the control electrode region including the semiconductor region and the embedded region. A photoelectric conversion device which is located above and is configured to apply a predetermined voltage to the buried region so as to allow the charges accumulated in the control electrode region to escape to the buried region.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61125937A JPH0691234B2 (en) | 1986-06-02 | 1986-06-02 | Photoelectric conversion device |
| AT87300853T ATE109593T1 (en) | 1986-02-04 | 1987-01-30 | PHOTOELECTRIC CONVERSION ELEMENT AND PROCESS FOR ITS MANUFACTURE. |
| EP87300853A EP0232148B1 (en) | 1986-02-04 | 1987-01-30 | Photoelectric converting device and method for producing the same |
| DE3750300T DE3750300T2 (en) | 1986-02-04 | 1987-01-30 | Photoelectric conversion element and method for its production. |
| US07/411,219 US5089425A (en) | 1986-02-04 | 1989-09-22 | Photoelectric converting device having an electrode formed across an insulating layer on a control electrode and method for producing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61125937A JPH0691234B2 (en) | 1986-06-02 | 1986-06-02 | Photoelectric conversion device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62283661A JPS62283661A (en) | 1987-12-09 |
| JPH0691234B2 true JPH0691234B2 (en) | 1994-11-14 |
Family
ID=14922656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61125937A Expired - Lifetime JPH0691234B2 (en) | 1986-02-04 | 1986-06-02 | Photoelectric conversion device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691234B2 (en) |
-
1986
- 1986-06-02 JP JP61125937A patent/JPH0691234B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62283661A (en) | 1987-12-09 |
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