JPH069109B2 - DATA TRANSMISSION METHOD AND DEVICE - Google Patents

Description

TECHNICAL FIELD The present invention relates to a data transmission method and device for transmitting information data.

[Conventional technology]

Conventionally, in transmission of digital data signals, particularly in magnetic recording of digital data signals, a method of converting 8-bit data into 9-bit data in order to suppress low frequency components of the recorded digital data signal (8/9 Conversion) was used. However, this method has a drawback that the redundancy increases, and a method that does not increase the redundancy has been demanded as the amount of data increases and the recording density increases.

Therefore, as a method that does not increase the redundancy, for example, mapping coding or the like can be used. Mapping coding can be applied when the correlation between adjacent data is strong as a statistical property of the input signal, and this property is used to suppress low frequency components of the coded data sequence. Is used for differential encoding, and the differential data has a Laplace distribution that concentrates near zero of the positive and negative quantization levels. To suppress low frequency components of the mapping encoded data sequence, the DSV of the data sequence is suppressed. (Digital Su
m Vau) is converted into a data sequence selected as a parameter, and there is, for example, a 4/4 mapping coding system in which input difference data of 4 bits is converted into data of 4 bits.

[Problems to be solved by the invention]

By the way, the mapping coding can suppress the low frequency component of the encoded data sequence, but cannot remove the DC component because of the n / n conversion (n is a positive integer).

Also, when other additional information data such as error detection or correction data is inserted into the encoded data sequence, the low frequency component suppression effect of the data sequence is significantly reduced, and as a result, the code at the time of decoding is encoded. The error rate will increase.

FIG. 2 is a diagram showing a configuration example of a conventional data frame,
The information data in the figure shows the mapping coded data series, and the error detection / correction code shows check points such as Hamming code and Reed-Solomon code.

FIG. 3 shows an inner code (row check code) in the data frame as shown in FIG. 2, a plurality of such data frames are arranged vertically, and an outer code (column check code) is arranged in the vertical direction. It is a diagram that is configured so as to be “codes as a whole. Note that, in the case of such a configuration, particularly because the information data and the check code are two-dimensionally arranged, it is suitable for image data and the like. It will be composed.

However, in the case of the configuration shown in FIG. 3, the inner code,
Since there is no correlation between the data in the portion where the outer code check points are continuous, the mapping code cannot be used, and the effect of suppressing the low frequency component is significantly reduced. In particular, in a data frame composed of only outer code and inner code check points, the check points will be continuous for a long period of time, and the low frequency component suppression effect of the data series in the vicinity will be significantly reduced. There are drawbacks.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a transmission method and apparatus having a high effect of suppressing low frequency components.

[Means for solving problems]

The data transmission method of the present invention is a method of arranging the sub information data with respect to the main information data so that the sub information data will not be arranged continuously during the transmission, and transmitting these.

Further, the data transmission apparatus of the present invention comprises means for changing the arrangement order of the main information data every time the sub information data is generated, means for generating the sub information data according to the arrangement order of the main information data, and transmission thereof. And a means for doing so.

[Action]

As described above, since the sub information data generated from the main information data is generated and transmitted so as not to be arranged continuously at the time of transmission, it is possible to perform transmission with extremely high suppression effect of low frequency components. it can.

〔Example〕

 Hereinafter, description will be made using examples.

FIG. 4 shows an example of the product code structure of the present invention.

Further, FIG. 5 shows the direction of the time axis when the product code structure as shown in FIG. 4 is transmitted by an arrow, after transmitting from the synchronous data to the inner code check point in one data frame. , The data frame of the next row is sent.

The outer code check points, which are the check points of the columns, are coded for the respective columns in FIG. 3, but, for example, as shown in FIG. 4, the positions of the outer code check points are changed diagonally for each column. With the above arrangement, the inspection points will not be extremely continuous when they are transmitted in the order shown in FIG.

FIG. 1 is a schematic configuration diagram of a recording system of a digital VTR to which the present invention is applied as an embodiment of the present invention.

The digital data input in FIG. 1 is input to the mapping coding circuit 1 word by word, and the digital data is subjected to mapping coding to suppress low frequency components. Then, the digital data subjected to the mapping encoding is temporarily stored in the memory 2. The digital data is written in the memory 2 in an arrangement corresponding to that excluding the synchronous data portion shown in FIG.

Therefore, k from the upper left to the right end of the means
After the word data is accumulated, the data is written in the order that the next k word data is accumulated from the left end to the right end one stage below. This write operation is sequentially divided. This write operation operates so that the column address K and the row address are sequentially generated when the address control circuit 3 synchronizes with the input data.

Then, the outer code coding circuit 4 adds outer code check points. As shown in FIG. 3, the outer code check points are calculated on vertical columns of information data, and the check points are added to the same column. The data is read into the outer coding circuit 4 in order from the highest data for a certain column, and the operation is performed to write a check point at the bottom. However, in the present invention, this is encoded starting point for each column. Are shifted to obtain outer code check points arranged as shown in FIG. Therefore, the address control circuit 3 generates addresses whose start points are shifted for each corresponding column so that the outer code check points are arranged as shown in FIG. This operation will be described later.

Then, with respect to the data in which the outer code check points are diagonally arranged as shown in FIG. 4, the data is next read out in the horizontal direction, and the inner coding circuit 5 adds the inner code check points for each row. Further, after synchronizing data is added by the synchronizing signal adding circuit 6, it is recorded on a tape (not shown) in the recording section 7.

Here, the address control circuit 3 in the above outer coding will be described in detail.

FIG. 8 is a diagram showing an example of the configuration of the address control circuit 3 of FIG. 1, in which the outer code read / generated by the clock generator 8 is read.
The write word clock is a row counter 9 and a column counter 1.
0 is input, and each counter counts up each time the clock is input. The line counter 9
The column counter 10 is a k-ary counter, 1
1 is a carrier output of the counter 9.

Further, the count output of the column counter 10 is inverted by the inverter 12 and is added to the count output of the row counter 9 by the adder 13, so that the row count 9 is output from the adder 13.
A value obtained by subtracting the value of the column count 10 from the value of is calculated and output.

Then, the output of the adder 13 is input to the arithmetic unit 14, and the arithmetic circuit 14 obtains the row address as a value of 0 to (-1).

If the inverter 12 for inverting the count output (column address output) of the column counter 10 is not used, the inclination of the outer code check points diagonally arranged can be reversed. The slope of the slope can be changed by adding a constant in the adder 13.

FIG. 9 is a schematic block diagram of a reproducing system of a digital VTR for reproducing the information recorded on the tape by the recording system of FIG.

In FIG. 9, the sync data is separated from the reproduced signal reproduced from the tape (not shown) by the reproducing unit 15 by the sync separating circuit 16, and the other data string except the sync data is subjected to inner code error detection correction decoding. Input to the circuit 17.

The inner code error detection / correction decoding circuit 17 detects and corrects a data error in the serially input data by using the inner code, and the data subjected to the error detection / correction by the inner code is It is stored in the memory 18.

The memory 18 performs the same write operation as the memory 2 of FIG. 1, and the write operation is controlled by the address control circuit 19.

As for the data stored in the memory 18, the column data is sequentially read by the address control circuit 19 and is input to the outer code error detection / correction circuit 20. The outer code error detection / correction circuit 20 detects an error in the data of the column read from the memory 18 by using the outer code and corrects it.
The data subjected to the error detection and correction by the outer code is stored in the memory 18 again. The outer code check points are arranged obliquely as described above, for example, as shown in FIG.
Since the data stored in the above specific address becomes the data of the outer code, other data will not be erroneously read.

After the data that has been subjected to the error detection and correction by the inner code and the outer code as described above is stored in the memory 18, the read address is controlled and read by the address control circuit 19 so that the data is read in the row data order. The reproduced data is decoded by the mapping decoding circuit 21 into reproduced image data.

In the present embodiment, the mapping coding circuit is used as the low frequency component suppressing means, but it can be applied to the present invention as long as there is a coding circuit having a low band suppression effect, for example, block coding, and the like. In this case, the low frequency suppression effect can be further enhanced.

Further, in the present embodiment, the case where the present invention is applied to the digital VTR has been described, but the present invention is not limited to this, and the present invention can also be applied to data communication, a disk recording / reproducing device and the like.

〔The invention's effect〕

As described above, by using the present invention, it is possible to provide a data transmission method and apparatus that are highly effective in suppressing low frequency components.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a recording system of a digital VTR to which the present invention is applied as an embodiment of the present invention. FIG. 2 is a diagram showing a configuration example of a conventional data frame. FIG. 3 is a diagram showing an example of a configuration in which a product code is constructed using the data frame of FIG. FIG. 4 is a diagram showing the structure of the product code of the present invention. FIG. 5 is a diagram showing the transmission order of product codes. FIG. 6 is a diagram showing a configuration example of the address control circuit of FIG. FIG. 7 is a diagram showing a schematic structure of a reproducing system of a digital VTR to which the present invention is applied as one embodiment of the present invention. 1 ... Mapping coding circuit, 2,18 ... Memory, 3,19 ... Address control circuit, 4 ... Outer code coding, 20 ... Outer code error detection / correction decoding circuit, 21 ... Mapping decoding circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shin Shimogoriyama, No. 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Masahiro Takei, 770 Shimonoge, Takatsu-ku, Kawasaki-shi, Kanagawa Canon Inc. Company Tamagawa Plant (72) Inventor Hiroji Takahashi 770 Shimonoge, Takatsu-ku, Kawasaki-shi, Kanagawa Canon Inc., Tamagawa Plant

Claims (6)

[Claims] 1. A data transmission method comprising arranging sub-information data with respect to main information data so that the sub-information data will not be arranged continuously during transmission, and transmitting the sub-information data. 2. A means for changing the arrangement order of the main information data every time the sub information data is generated, a means for generating the sub information data according to the arrangement order of the main information data, and transmitting the information data. And a data transmission device. 3. The data transmission method according to claim 1, wherein the main information data is information data in which a low frequency component is suppressed. 4. The data transmission method according to claim 1, wherein the sub information data is information data in which a low frequency component is not suppressed. 5. The data transmission device according to claim 2, wherein the information data is information data in which a low frequency component is suppressed. 6. The data transmission device according to claim 2, wherein the sub information data is information data in which a low frequency component is not suppressed.