JPH0690855B2 - Minimum bit inversion period detection circuit - Google Patents

Description

The present invention relates to a reproducing device for reproducing a recording medium in which at least a PCM signal and a single frequency signal are recorded in a time division manner, for example, a rotary head type digital audio tape recorder. The present invention relates to a minimum bit inversion period detection circuit for detecting the minimum bit inversion period of a reproduced PCM signal.

[Conventional technology]

Conventionally, a rotary head type digital audio tape recorder which is an example of this kind of reproducing apparatus is called R-DAT,
A PCM audio area, a sub-code area, and a tracking area are formed in a time-division manner on each track to be recorded by helical scanning of a magnetic tape forming a recording medium.

Then, in the PCM audio area, the PCM signal of the audio information forming the main information is recorded, in the subcode area the PCM signal of the video or audio information forming the sub information is recorded, and in the tracking area the ATF signal and A so-called single frequency pilot signal for playback tracking control is recorded.

In addition, in order to prevent overwriting, etc., a margin area in which a single frequency signal set to the highest frequency of 1T, 4.702 MHz, is recorded is provided between the start and end of each track and between each area. Has been.

Further, at both ends of the PCM audio area and the tracking area, guards for preventing overwriting called interblock guards are provided, and a single frequency signal having a period of 3T is recorded in the guards.

The pilot signal consists of a low-frequency single-frequency signal that is sufficiently lower than the inter-block guard single-frequency signal.

In addition, the frequency of the PCM signal in the PCM audio area and subcode area changes according to the data content,
When the data contents are all 0s, it becomes a signal of cycle 2T.

The magnetic tape is a standard playback mode in which the tape speed and running direction are the same as during recording, or special playback in which one or both of the tape speed and running direction is different from that during recording, due to the alternating scan of a pair of rotating heads. Played in mode.

At this time, in the standard reproduction mode, each track of the tape is sequentially helical-scanned, and the reproduction signal of each 1-scan becomes a signal in which the signal recorded in each 1-track is sequentially reproduced. If so, a plurality of tracks on the tape are obliquely crossed by one scan, so that the reproduced signal of each one scan is a signal obtained by combining the signals recorded in a part of each of the plurality of tracks.

The minimum bit inversion period of the reproduced PCM signal (hereinafter referred to as the reproduced PCM signal) varies depending on the reproducing mode and also changes due to fluctuations in the tape speed during reproduction.

Therefore, regardless of the playback mode, to accurately extract the playback PCM signal from the playback signal and perform playback processing, for example, follow the minimum bit inversion cycle of the playback PCM signal and play back the playback P
It is necessary to control the sampling clock generation circuit of the CM signal and variably control the frequency of the sampling clock of the playback PCM signal by following the minimum bit inversion period.

In the specification and drawings of the application of Japanese Patent Application No. 61-126719, the fluctuation of the minimum bit inversion cycle of the reproduced PCM signal is detected from the fluctuation of the reproduced frequency of the single frequency signal recorded in the above-mentioned margin area. In order to variably control the frequency of the sampling clock, the minimum bit inversion period detection circuit (channel clock frequency detector) of the first or second configuration described below is provided and is proportional to the minimum bit inversion period of the detection circuit. Based on the detected voltage signal, the oscillation frequency variable range of the voltage controlled oscillator of the sampling clock generation circuit is moved and changed according to the playback mode, and the sampling clock frequency is always the minimum bit inversion of the playback PCM signal regardless of the playback mode. It is described that the control is performed following the cycle.

By the way, the minimum bit inversion period detection circuit of the first configuration described in the specification and drawings of the above-mentioned Japanese Patent Application No. 61-126719 uses a reproduction signal (hereinafter referred to as an RF signal) of a rotary head as a frequency / voltage. A gate signal obtained by converting and forming a voltage signal that is converted in proportion to the frequency of the RF signal, and comparing the AM detection signal of the RF signal with a preset reference voltage for on-track detection. And a gate signal obtained by gate-processing the head switching pulse signal, that is, a gate signal having a pulse width during the expected reproduction period of the margin area in which the single frequency signal to be detected is recorded, and the gate signal is detected. A gate signal is formed at the timing of the reproduction period of a single frequency signal to be sampled, and the voltage signal is sample-held based on the gate signal to be proportional to the minimum bit inversion period of the reproduction PCM signal. And outputs a detection signal that changes.

In addition, the minimum bit inversion period detection circuit of the second configuration reproduces by performing the operation of a preset arithmetic expression based on the detection signal of the rotational speed of the rotary head, that is, the scanning speed and the detection signal of the tape running speed. A detection signal that changes in proportion to the minimum bit inversion period of the PCM signal is output.

However, in the case of the minimum bit inversion period detection circuit of the first configuration, the AM detection level of the RF signal changes due to the material of the tape, the recording condition, the dropout of the RF signal, the secular change, and the like. Since it becomes difficult to form the signal accurately, it becomes difficult to accurately sample and hold only the voltage signal of the single frequency signal to be detected.

Further, in the case of the minimum bit inversion period detection circuit of the second structure, since the calculation of the calculation formula is performed, a complicated calculation circuit is required, the structure is significantly complicated and expensive, and the RF signal is not used. Since the minimum bit inversion period is indirectly detected by the scanning speed detection signal of the rotating head and the tape speed detection signal, it becomes difficult to increase the detection accuracy to a certain degree or more.

Therefore, it is conceivable to eliminate the above-mentioned inconvenience by configuring the minimum bit period detection circuit as shown in FIG.

By the way, in FIG. 7, (1) is an input terminal for the RF signal of the rotating head, (2) is a frequency / voltage converter connected to the input terminal (1), and (3) is connected to a converter (2). The flat portion detection unit (4) is a sample hold unit connected to the conversion unit (2) and the detection unit (3).

Further, in the detection unit (3), (5), (6),
(7) and (8) are four comparators, and the inverting input terminal (-) of the comparator (5) and the non-inverting input terminal (+) of the comparator (6) are directly connected to the conversion unit (2). The inverting input terminal (−) of the comparator (7) and the non-inverting input terminal (+) of the comparator (8) are connected to the capacitor (9) and the differential circuit (1) of the resistor (10).
It is connected to the converter (2) via 1). (12) is a charging circuit formed by connecting a resistor (13) and a capacitor (14) in series between the power supply terminal (+ B) and ground,
The connection point between the resistor (13) and the capacitor (14) is connected to the output terminals of the comparators (5) to (8). Reference numeral (15) is a waveform shaping gate connected to the connection point between the resistor (13) and the capacitor (14).

(16) and (17) are the detection reference voltages in the playback frequency range described later.
There are two reference voltage terminals to which Vh and Vl are applied. The voltage terminal (16) is connected to the non-inverting input terminal (+) of the comparator (15), and the voltage terminal (17) is connected to the comparator (6). ) Is connected to the inverting input terminal (+). Reference numerals (18) and (19) denote two reference voltage terminals to which flat plate detection reference voltages Vp and Vn, which will be described later, are applied, and the voltage terminal (18) is a non-inverting input terminal () of the comparator (7). The voltage terminal (19) is connected to the inverting input terminal (-) of the comparator (8).

Further, in the sample-hold section (4), (20) is a gate pulse generating circuit consisting of a monostable multivibrator, which is connected to the input terminal gate (15) and is used for holding from Q, output terminals (q), (). , Outputs the sampling gate signals Gh and Gs, respectively. Reference numeral (21) is a sample and hold circuit including first and second sample and hold circuits (22) and (23) connected in series to the conversion unit (2),
The sample hold circuit (22) operates by the gate signal Gs, and the sample hold circuit (23) operates by the gate signal Gh.

The conversion unit (2) comprises a comparator, a monostable multivibrator, and a low-pass filter, and the input terminal (1)
To form an FM demodulation circuit for the reproduced signal of, that is, the RF signal of the rotating head.

By the way, for example, the RF signal input to the input terminal (1) in the standard reproduction mode is the signal recorded in each track as shown in FIG. 8 (a) for each scan of the rotary head. Become.

In FIG. 8 (a), (A) and (B) are trace start and end margin areas, (C) is a PCM audio area, (D) and (E) are subcode areas, respectively.
(F), (G) are tracking areas, (H),
(I) and (J) are intermediate margin areas,
A PCM signal is recorded in each of the areas (C), (D), and (E), and a pilot signal of a single frequency is recorded in each of the areas (F) and (G), and the areas (A) and (B) are recorded. ，
(H), (I), and (J) are margin cycles, respectively.
The 1T single frequency signal, that is, the specific single frequency signal to be detected is recorded.

Then, the conversion unit (2) converts the input RF signal into a digital signal of logic 0, 1 by comparing the comparator based on the threshold level Vs of FIG. First, the duty cycle of the output signal of the monostable multivibrator is changed according to the frequency of the input RF signal, and the low-pass filter allows the specific single frequency among the signals of the monostable multivibrator. Only the low-frequency component necessary for detecting the fluctuation of the signal is extracted and output, and at this time, the voltage of the output signal of the low-pass filter changes in proportion to the frequency of the extracted low-frequency component.

That is, the conversion unit (2) converts the frequency of the RF signal into a voltage and outputs the voltage signal in which the frequency of the low frequency component necessary for detecting the fluctuation of the specific single frequency signal is converted into the voltage.

The voltage signal of the converter (2) for the RF signal of FIG. 8 (a) is as shown in FIG. 8 (b), and the reproduction frequency is constant in the portion of the single frequency signal, so a flat waveform is obtained. become.

Then, the voltage signal of the conversion unit (2) is input to the detection unit (3) and the sample hold unit (4).

At this time, the voltage signal of the conversion unit (2) is applied to the inverting input terminal (−) of the comparator (5) of the detection unit (3) and the non-inverting input terminal (+) of the comparator (6). , The inverting input terminal (−) of the comparator (7) of the detection unit (3) and the non-inverting input terminal (+) of the comparator (6) are the conversion unit () differentiated by the differentiation circuit (11). The voltage signal of 2), that is, the differential voltage signal of FIG. 8C is applied.

By the way, the comparators (5) and (6) are provided to detect a voltage signal in a reproduction frequency range of a specific single frequency signal having a period of 1T, and the non-inverting input terminal (+) of the comparator (5), The inverting input terminal (-) of the comparator (6) has a detection reference voltage of the reference voltage terminals (16) and (17), that is, the voltage of the voltage signal of the maximum and minimum frequencies of the specific single frequency signal of the period 1T. The voltages Vh and Vl, which are slightly larger and smaller, are applied.

Further, the comparators (7) and (8) are provided to detect the flat portion of the voltage signal, and the non-inverting input terminal (+) of the comparator (7) and the inverting input terminal (−) of the comparator (8). ) Is the detected reference voltage of the reference voltage terminals (18) and (19), that is, the cycle
Voltages Vp and Vn at the positive and negative limits of the gentle voltage fluctuation range of the voltage signal based on a specific single frequency signal of 1T are applied.

Then, the comparators (5) and (6) detect whether or not the voltage of the voltage signal output from the conversion unit (2) is within the range of Vh to Vl in FIG. If the voltage is in the range of Vl, the transistors in the output stages of the comparators (5) and (6) are both turned off.

Further, the differential voltage of the voltage signal output from the conversion unit (2) is changed by the comparators (7) and (8) from Vp to Vn in FIG. 8 (c).
It is detected whether or not the voltage is in the range of Vp, and if the voltage is in the range of Vp to Vn, the transistors in the output stages of the comparators (7) and (8) are both turned off.

Therefore, when the voltage of the voltage signal output from the conversion unit (2) becomes a voltage in the range of Vh to Vl and the fluctuating voltage of the voltage signal becomes a voltage in the range of Vp to Vn, that is, when the period is 1T. Only when the voltage at the plateau due to a specific single frequency signal is reached, the final stage transistors of all the comparators (5) to (8) are turned off.

By the way, in the final stage transistor of each of the comparators (5) to (8), the emitter is grounded and the collector is connected to the connection point of the resistor (13) and the capacitor (14).

Then, the capacitor (14) is charged only when the final stage transistors of all the comparators (5) to (8) are turned off, and any one of the comparators (5) to (8) is the final stage. When the transistor of is turned on, the capacitor (14) is immediately reset and discharged.

Furthermore, when the capacitor (14) is charged for a certain period of time and the charging voltage reaches the threshold level of the gate (15), the output signal of the gate (15) rises to a high level as shown in FIG. The output signal of the gate (15) is held at high level until 14) is reset and discharged.

That is, the detection unit (3) detects a flat portion of the voltage signal due to a specific single frequency signal with a period of 1T, and at this time, the voltage signal fluctuates during the sample hold period of the sample hold unit (4) due to noise or the like. In order to prevent this, the high-level detection pulse composed of the output signal of the gate (15) is output only when the flat part where the voltage signal output from the conversion part (2) becomes flat for a certain period or more is detected. To do.

Then, the detection pulse output from the gate (15) is input to the generation circuit (20), at which time the generation circuit (20) is triggered by the rising edge of the detection pulse and set by the time constant. During the period τ, that is, the period τ required for sample hold, the Q output terminal (q) becomes high level and the output terminal () becomes low level,
From the output terminal () to the first sample and hold circuit (22)
8e, the gate signal Gs shown in FIG. 8E is output, and the Q output terminal (q) outputs the gate signal Gh shown in FIG. 8 (f) to the second sample hold circuit (23).

On the other hand, both sample-hold circuits (23) connected in cascade,
(24) has the same structure using, for example, a switch for sampling and holding, a capacitor, and an amplifier for output buffer, and is controlled by the gate signals Gs and Gh in the sample mode and the hold mode in reverse to each other.

The sample-hold circuit (22) enters the hold mode by turning off the sample-hold switch only during the period τ when the gate signal Gs is high level. The sample-hold circuit (23) changes the gate signal Gh to low level. Only during the period τ, the sample and hold switch is turned on to enter the sample mode.

Therefore, the sample-hold circuit (22) holds the voltage signal input at the timing of the leading edge of the detection pulse, that is, the voltage signal of the flat portion by the detected specific single frequency signal for the period τ. The sample-hold circuit (23) outputs the sample signal to the sample-hold circuit (23), and the sample-hold circuit (23) samples the hold signal output from the sample-hold circuit (23) during the period τ. As shown in Fig. 8 (g), it becomes a hold signal of the signal of the flat part sampled by the sample and hold circuit (22), and its voltage is the reproduction frequency of the specific single frequency signal of period 1T in the RF signal. Changes in proportion to.

That is, the sample and hold unit (4) includes the detection unit (3).
Based on the detection pulse of, the sampled and held voltage signal of the flat part due to the detected specific single frequency signal, at this time, the voltage of the output signal of the sample hold circuit (23) becomes the reproduction frequency of the specific single frequency signal. The playback frequency of a specific single frequency signal changes proportionally and plays back PCM
Since the signal is proportional to the minimum bit inversion period of the signal, the hold voltage signal of the sample hold circuit (23) is output as the detection signal of the minimum bit inversion period of the reproduced PCM signal.

In the case of the minimum bit inversion period detection circuit of FIG. 7, a specific single frequency signal is obtained by using only the voltage signal of the conversion unit (2) that has converted the RF signal without using the head switching pulse signal or the like. In order to detect the flat part of the voltage signal directly based on this, and to detect the minimum bit inversion period by sample-holding the detected flat part voltage signal,
Even if the signal reproduction level (AM detection level) changes due to the difference in tape material, recording condition, etc., the minimum bit inversion period can be detected accurately and reliably, and no complicated arithmetic circuit is required. Therefore, the configuration is simplified and the cost is reduced, and the adjustment and the like are also simplified, and the above-mentioned inconvenience can be eliminated.

[Problems to be solved by the invention]

By the way, in the case of the detection circuit of FIG. 7, in order to detect that the flat part of the specific single frequency signal of the period 1T is a voltage signal, the comparators (5) and (6) of the detection part (3) are provided. A preset fixed reference voltage Vh, Vl is applied, and the reference voltage Vh, Vl is a voltage for detecting a voltage signal in a range slightly wider than the variation range of the voltage signal based on the specific single frequency signal. Is set to.

On the other hand, in special playback mode such as high-speed search where the magnetic tape runs at high speed and when starting playback in each mode,
The frequency fluctuation of the RF signal becomes large, and at this time, the fluctuation range of the reproduction frequency of each signal such as the reproduction PCM signal and the single frequency signal in the RF signal also becomes wide.

Therefore, the frequency of a specific single-frequency signal to be detected and the frequency of a single-frequency signal that should not be detected, such as another single-frequency signal that is not detected, or all bit 0 or (29) PCM signals. , The voltage signal based on the signal of the single frequency that should not be detected fluctuates within the range of the voltage Vh to Vl in the high-speed search mode or at the start of reproduction, and erroneous detection may occur. is there.

Now, let f ₀ be the frequency of the specific unit frequency signal to be detected, and select the frequency among the single frequency signals that should not be detected.
f ₀ from the high frequency side, the frequency of the low frequency side each of the nearest signal and f _1, f ₂ respectively, and f _0, f _1, the voltage of the f ₂ of the voltage signal V _0, V _1, V ₂ respectively And the maximum fluctuation rate α of the reproduction frequency of the RF signal is, the fluctuation range of the voltage signal corresponding to the single frequency signal to be detected is V ₀ (1 + α) to V ₀ (1-
.alpha.), the voltages Vh and Vl are set as shown in FIG.

On the other hand, the fluctuation range of the voltage signal corresponding to each of the signals of the frequencies f ₁ and f ₂ is V ₁ (1 + α) to V ₁ (1-α), V ₂ (1+
α) to V ₂ (1-α) respectively.

Then, (1-α) f ₁ <(1 + α) f ₀ or (1-α)
When f ₀ <(1 + α) f ₂ , the frequency becomes as shown in FIG.
The voltage signal corresponding to the signal of f ₁ or f ₂ fluctuates in the range of voltages Vh to Vl.

By the way, in the case of R-DAT, the specific single frequency signal becomes a signal of the highest frequency of the period 1T, and the single frequency signal closest to the specific single frequency signal is
It becomes a PCM signal with a period of 2T when all bits are 0, that is, a signal having a frequency half that of a specific single frequency signal.

Therefore, in the case of the detection circuit of FIG. 7 applied to the R-DAT, especially under the condition of (1-α) f ₀ <(1 + α) f ₂ , erroneous detection occurs and at this time, f ₀ = Since the relationship of 2f ₂ is established, the condition that false detection occurs is α> 1/3 (= 0.33)
become.

That is, in the case of the detection circuit of FIG. 7, when the maximum fluctuation rate α of the reproduction frequency is 0.33 or more, that is, when the minimum bit inversion cycle of the reproduction PCM signal changes by about ± 30% or more, or when the reproduction is started, There is a problem that the minimum bit inversion period cannot be accurately detected.

[Means for solving problems]

The present invention has been made with the above points in mind,
At least a PCM signal, provided in a reproducing device for reproducing a recording medium in which a single frequency signal is time-division recorded, in a minimum bit inversion period detection circuit for detecting the minimum bit inversion period of the PCM signal included in the reproduction signal, A frequency for converting the frequency of the reproduction signal into a voltage and outputting a voltage signal that changes in proportion to the frequency of the reproduction signal.
The voltage converter and the specific single frequency signal based on the comparison between the voltage signal and the detection reference voltage in the reproduction frequency range of the specific single frequency signal and the fluctuation voltage of the voltage signal and the detection reference voltage in the reproduction frequency flattening unit. A flat portion detection unit that detects a flat portion of the voltage signal by one frequency signal and outputs a detection pulse; a sample and hold of the voltage signal in the detection period based on the detection pulse; and the held voltage signal is the minimum bit. A sample hold unit for outputting a detection signal of an inversion period is provided, and the flat portion detection unit is provided with a reference voltage forming unit for dividing the hold voltage signal to form a detection reference voltage in the reproduction frequency range. This is a minimum bit inversion period detection circuit.

[Action]

Then, the detection reference voltage in the reproduction frequency range of the flat portion detection unit changes following the hold voltage signal of the sample hold unit, and at this time, the hold voltage signal changes following the reproduction frequency of the reproduction signal, The detection reference voltage in the reproduction frequency range changes following the reproduction frequency of the reproduction signal, and the reproduction frequency range detected by the flat part detection unit is changed according to the change in the reproduction frequency of the reproduction signal.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings of FIGS. 1 to 6 showing its embodiment.

FIG. 1 shows a case where it is applied to an R-DAT. In the figure, the difference from FIG. 7 is that instead of the detection unit (3) in FIG.
The point is that a flat part detection part (24) to which the hold voltage signal of the sample hold part (4) is fed back is provided.

In addition, FIG. 2 shows a detailed configuration of each part of FIG. 1, in which (25), (26) and (27) are a comparator, a monostable multivibrator, which form a conversion part (2), It is a low-pass filter, and the filter (27) is formed by a resistor (28), a capacitor (29) and a buffer amplifier (30) for the filter.

Reference numeral (31) is a comparator for detecting the reproduction frequency range provided in place of the comparators (5) and (6) in FIG. 7, and the non-inverting input terminal (+) is connected to the conversion unit (2). , The output terminal is connected to the connection point of the resistor (13) and the capacitor (14). (32), (33) and (34) are 3 for voltage division provided in series between the power supply terminal (+ B) of the detection section (24) and the ground.
Resistances (32) and (33) are connected to the voltage terminal (18), resistors (33) and (34) are connected to the voltage terminal (19), and the reference voltage Set Vq and Vn.

Reference numeral (35) is a third sample-hold circuit provided in place of the sample-hold circuit (23) shown in FIG. 7, and includes a sample-hold switch (36), a capacitor (37), and an output buffer amplifier (38). And capacitors (37)
And a switch (39) for discharge reset of the switch, the switch (36) is switched by the gate signal Gh of the generator circuit (20), and the switch (39) is reset by the reset signal of the reset terminal (40). Switch.

Reference numerals (41) and (42) are two resistors for voltage division forming the reference voltage forming means of the detection section (24), which are provided in series between the output terminal of the sample hold circuit (35) and the ground. At the same time, the connection point of both resistors (41) and (42) is connected to the comparator (3
It is connected to the inverting input terminal (-) of 1).

By the way, in the case of this embodiment as well, as in the case of FIG. 7, the period 1T (=
The highest single frequency signal of 4.704 MHz) is the specific single frequency signal to be detected.

Therefore, the voltage signal output from the conversion unit (2) based on the RF signal of the specific single frequency signal to be detected is
It changes in a voltage range higher than the voltage signal output from the conversion unit (2) based on the RF signal of other signals such as the reproduced PCM signal.

Since the voltage signal in the reproduction frequency range of the specific single frequency signal to be detected can be detected only by the comparator (6) in FIG. 7, this embodiment corresponds to the comparator (6). The comparator (31) is provided, and the comparator corresponding to the comparator (5) is omitted.

In addition, the hold voltage signal of the sample hold unit (4),
That is, in the mode in which the detection signal of the minimum bit inversion period is not required, the hold voltage signal of the sample and hold section (4) is held at the ground level. Therefore, in this embodiment, the sample and hold circuit having the switch (39) ( 3
5) is provided, and based on the reset signal of the reset terminal (40), the switch (39) is turned on to hold the discharge of the capacitor (37) during the mode in which the detection signal is not required, and the sample hold unit (4) Hold voltage signal is held at ground level.

Further, the voltage at the inverting input terminal (-) of the comparator (31), that is, the detection reference voltage in the reproduction frequency range corresponding to the reference voltage Vl in FIG. 7, is the connection point of the resistors (41) and (42). Voltage
If Vx is the voltage of the hold voltage signal that is formed by Vr and the resistance of the resistors (41) and (42) is R1, R2, and the single frequency signal to be detected with period 1T is Vx, Is expressed by the following equation (1).

Then, by switching to a mode in which a hold voltage signal is required, as shown in FIG. 3 (a), the reset terminal (40)
When the reset signal of (3) falls from high level to low level at t ₀ , for example, the switch (39) is inverted from on to off at this time, and the discharge reset of the capacitor (37) is released.

Therefore, in the period T ₀ before t ₀ , both the voltages Vx and Vr are held at the ground level as shown by the solid line vx and the broken line vr in FIG. 3B, and the comparator (31)
, The transistor in the final stage is kept on regardless of the voltage of the voltage signal of the conversion unit (2).

On the other hand, when the discharge reset of the capacitor (37) is released at t ₀ , the sample-hold section (4) operates normally, the voltage Vx of the hold voltage signal rises, and the voltage follows the rise of the voltage Vx. Vt rises.

By the way, in the case of R-DAT, the signal of the single frequency closest to the specific single frequency signal of the period 1T to be detected is the reproduced PCM signal of the period 2T of all bits 0 as described above, and the frequency thereof is It becomes 1 / 2T.

Then, when the voltage of the voltage signal with respect to the signal of the single frequency of the period 2T is Vz, the following expression (2) is always established between the voltages Vx and Vz.

On the other hand, in order not to erroneously detect a single frequency signal with a period of 2T as a specific single frequency signal to be detected, always:
It is necessary to satisfy the condition of the following expression (3).

Vr> Vz ………… (3) Formula Then, based on the formulas (1), (2) and (3), the resistance value
If R1 and R2 satisfy the condition of the following equation (4), erroneous detection does not occur.

R2> R1 ··································································································· At this time, the voltage Vz is one-dot chain line in Figure 3 (b) As shown in vz, the voltage Vx is always lower than the voltage Vr after t _0. Note that t ₁ , t ₂ , and t _{3 in} FIG. 3B change in the voltage Vx due to the frequency fluctuation of the RF signal. Showing each timing,
T _1, T _2, T ₃ represent, respectively, _{t 0 ~t 1, t 1 ~t} 2, t 2 period of.

That is, while the voltage Vr changes following the voltage Vx, for example, in the periods T ₂ and T ₃ , unless the voltage Vx changes to the voltage Vr immediately before the time t ₁ or t ₂ , respectively, the voltage is always constant.
Vz becomes lower than voltage Vr.

When the instantaneous fluctuation rate of the voltage Vx is β, the condition of Vr> Vz is satisfied as long as the following expression (5) is satisfied. Therefore, by substituting the expression (5) into the expression (1), The condition of is obtained.

(1-β) Vx> Vr …………………………………………………………………………………………………………………………………………………………………………………………………… of (4) It is selected based on the conditions of.

Since the voltage Vr is always higher than the voltage Vz, for example, in the high-speed search mode or when the reproduction is started, even if the maximum fluctuation rate α of the reproduction frequency becomes 0.33 or more, the specific single frequency signal of the cycle 1T to be detected is detected. Only when the voltage signal is detected, the final-stage transistor of the comparator (31) is turned on, and erroneous detection does not occur, and the minimum bit inversion cycle can always be detected accurately.

By the way, in the above-mentioned embodiment, the reference voltage forming means is formed by the resistors (41) and (42). However, as shown in FIG. 4, a resistor (43) and a constant current source (44) composed of a transistor are provided. It can also be formed.

Further, in the above embodiment, since the specific single frequency signal to be detected is set to the highest frequency, only the lower limit voltage is set as the detection reference voltage in the reproduction frequency range. When a single-frequency signal exists above and below a specific single-frequency signal to be detected, such as when applied to a reproducing apparatus other than the above, a reference voltage forming means or the like is shown in FIG. 5 or FIG. It may be formed as shown.

In FIG. 5, (45), (46), and (47) are two resistors for voltage division and an operational amplifier forming a reference voltage forming means, and connection points of the resistors (45) and (46). And the output terminal of the amplifier (47) to the comparator (5) of FIG.
The comparators (48) and (49) corresponding to (6) are supplied with the voltages Vh and Vl.
The reference voltages corresponding to are output. Note that (5
0) and (51) are two resistors for setting the gain of the amplifier (47).

Further, in FIG. 6, (52) and (53) are two buffer amplifiers, and (54) and (55) are for voltage dividing provided between the output terminal of the amplifier (52) and the power supply terminal (+ B). Resistance, constant current source, (56), (57) are voltage dividing resistors, constant current sources, (58), (59) provided between the output terminal of the buffer amplifier (53) and ground are shown in FIG. Are two comparators corresponding to the comparators (48) and (49).

In the case of FIG. 6, the reference voltage forming means is formed by the amplifiers (52), (53), the resistors (54), (56), the current sources (55), (57), and the resistor (54 ), The connection point of the current source (55) and the connection point of the resistor (56) and the current source (57) to the comparators (58) and (59), respectively, to output reference voltages corresponding to the voltages Vh and Vl. It

In addition, in the above-mentioned embodiment, the case where the invention is applied to the R-DAT has been described, but it is needless to say that the invention can be applied to various reproducing apparatuses other than the R-DAT, and in this case, a specific single unit to be detected on the recording medium is used. Even when the frequency signal and one or more single frequency signals having a frequency different from the standing frequency signal are recorded in time division, the flat portion of the voltage signal based on the specific single frequency signal is always detected accurately. However, the minimum bit inversion period can be accurately detected.

〔The invention's effect〕

As described above, according to the minimum bit inversion period detection circuit of the present invention, the detection reference voltage in the reproduction frequency range of the flat part detection part changes following the hold voltage signal of the sample hold part. However, since it changes following the reproduction frequency of the reproduction signal, the detection reference voltage in the reproduction frequency range changes following the reproduction frequency of the reproduction signal, and the reproduction frequency range detected by flat part detection is The flat part of the voltage signal based on a specific single-frequency signal can be accurately detected even when the maximum fluctuation rate of the reproduction frequency becomes large because it is changed according to the change of the reproduction frequency of the reproduction signal, and it is always accurate. In addition, the minimum bit inversion period can be detected.

[Brief description of drawings]

1 to 6 show an embodiment of a minimum bit inversion period detection circuit of the present invention. FIG. 1 is a block diagram of one embodiment, FIG. 2 is a detailed block diagram of FIG. 1, and FIG. 2A and 2B are timing charts for explaining the operation of FIG. 2, FIGS. 4, 5, and 6 are wiring diagrams showing other examples of reference voltage forming means, and FIG. 7 is a conventional diagram. Block diagram of the improved minimum bit inversion period detection circuit of Fig.8 (a)
~ (G) is a timing chart for explaining the operation of FIG.
FIG. 9 is a waveform diagram for explaining the operation of FIG. (2) ... Frequency / voltage conversion section, (4) ... Sample hold section, (24) ... Flat section detection section.

Claims (1)

[Claims] 1. A minimum bit inversion for detecting a minimum bit inversion period of the PCM signal included in the reproduction signal, which is provided in a reproduction device for reproducing a recording medium in which at least a PCM signal and a single frequency signal are time-division recorded. In the cycle detection circuit, a frequency / frequency that converts the frequency of the reproduction signal into a voltage and outputs a voltage signal that changes in proportion to the frequency of the reproduction signal.
The voltage converter and the specific single frequency signal based on the comparison between the voltage signal and the detection reference voltage in the reproduction frequency range of the specific single frequency signal and the fluctuation voltage of the voltage signal and the detection reference voltage in the reproduction frequency flattening unit. A flat portion detection unit that detects a flat portion of the voltage signal by one frequency signal and outputs a detection pulse; and a sample and hold of the voltage signal in the detection period based on the detection pulse, and the held voltage signal is the minimum. A sample and hold section for outputting as a detection signal of a bit inversion period, and the flat section detection section is provided with reference voltage forming means for dividing the hold voltage signal to form a detection reference voltage in the reproduction frequency range. A minimum bit inversion period detection circuit.