JPS63103477A - Minimum bit inversion period detecting circuit - Google Patents

Abstract

PURPOSE:To exactly execute a detection by converting a frequency of a reproducing signal to a voltage, and also, detecting a flat part of a voltage signal by a single frequency signal, sample-holding the voltage signal of the detected flat part, and detecting the minimum bit inversion period of a PCM signal which is reproduced. CONSTITUTION:By a frequency/voltage converting part 12, a frequency of a reproducing signal is converted to a voltage, and also, by a flat part detecting part 13, a flat part of a voltage signal by a single frequency signal is detected, based on a detection of a voltage of a voltage signal of the frequency/voltage converting part 12 and a variation voltage. Also, based on a detecting pulse of the flat part detecting part 13, the voltage signal of the detected flat part is brought to sample-holding by a sample holding part 16, a detecting signal of a voltage being proportional to the minimum bit inversion period of a PCM signal which is reproduced is outputted from the sample-holding part 16, and the minimum bit inversion period is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a reproducing apparatus for reproducing a recording medium on which at least a PCM multiplied signal single frequency signal is time-divisionally recorded, such as a rotary head type digital audio chip recorder. The present invention relates to a minimum bit inversion period detection circuit that is provided in a PCM signal and detects the minimum bit inversion period of a reproduced PCM signal.

[Conventional technology]

Conventionally, a rotary head type digital audio tape recorder, which is an example of this type of playback device, is called a 几DAT. A code area and a tracking area are formed in a time division manner.

In the PCM audio area, a PCM signal of audio information forming main information is recorded, in the subcode area a PCM signal of video or audio information forming sub information is recorded, and in the tracking area, a PCM signal called ATF is recorded. A pilot signal for playback tracking control is recorded.

Additionally, margin areas in which a single frequency signal is recorded are provided at the beginning and end of each track and between each area in order to prevent overlapping recording.

By alternately scanning a pair of rotating heads, the magnetic tape can be played either in standard playback mode, where the tape speed and running direction are the same as during recording, or in special playback mode, where one or both of the tape speed and running direction are different from those during recording. mode.

At this time, in the standard playback mode, each track of the tape is sequentially scanned, and the playback signal of each scan is a signal obtained by sequentially playing back the signals recorded on each track, and in the special playback mode. In this case, multiple tracks of the tape are scanned diagonally across in one scan, so the playback signal for each scan is a signal that is a composite of the signals recorded on a portion of each of the multiple tracks. .

The minimum bit inversion period of the reproduced PCM signal (hereinafter referred to as the signal to the reproduction PC8) differs depending on the reproduction mode and also changes due to fluctuations in the tape speed during reproduction.

Therefore, in order to accurately extract the reproduced PCM signal from the 2 reproduced signals and perform reproduction processing regardless of the reproduction mode, for example, the reproduction PCM signal extraction clock generation circuit must be configured to follow the minimum bit inversion period of the reproduced PCM signal. It is necessary to variably control the frequency of the sampling clock of the reproduced PCM signal to follow the minimum bit inversion period.

In the specification and drawings of Japanese Patent Application No. 126719/1984, a minimum bit inversion period detection circuit (channel clock frequency detector) of the first or second configuration described below is provided, and the detection circuit Based on the detection signal of the voltage proportional to the minimum bit inversion period of It is described that control is performed by following the minimum bit inversion period of a reproduced PCM signal.

Next, the first. Each of the minimum bit inversion period detection circuits of the second configuration will be explained.

First, a first configuration of the minimum bit inversion period detection circuit will be explained. The detection circuit is horizontally mounted as shown in Fig. 13, in which (1) is the input terminal for the rotary head playback signal (hereinafter referred to as ItF signal), and (2) is the pulse signal for head switching. (hereinafter referred to as SW multiplier signal) input terminals, (3) and (4) are the frequency/pressure conversion circuit and AM detection circuit connected to the input terminal (1), (5) is the non-inverting input terminal (+) is a voltage comparison circuit connected to the detection circuit (4), and a reference voltage for detecting the on-track state of the reference voltage terminal (61) is applied to the inverting input terminal ←.

(7) is a gate circuit connected to input terminal (2), (8
) is an AND gate into which the output signals of the comparison circuit (5) and gate circuit (7) are input, and (9) is a sample hole that samples and holds the output signal of the conversion circuit (3) using the output signal of the AND gate (8). A hold signal is output to the detection output terminal aQ.

The detection circuit shown in FIG. 13 detects the variation in the minimum bit inversion period of the reproduced PCM signal from the variation in the reproduction frequency of the single frequency signal recorded in the margin area.

That is, the input terminals (1) and (21 in FIG. 14(a)
), (1)) When the RF multiplied signal SW multiplied signal is input, the RF multiplied signal frequency is converted into voltage by the conversion circuit (3), and the RF multiplied signal is detected by the conversion circuit (4). , the detection signal shown in FIG. 4(c) is output from the conversion circuit (4) to the comparison circuit (5).

Furthermore, the voltage of the detection signal of the conversion circuit (4) and the reference voltage of the input terminal (6), that is, the reference voltage indicated by the dashed line in FIG. 14(C), are compared by the comparison circuit (5). The circuit (5) outputs a gate signal having a pulse width of the RF signal period in the on-track state, as shown in FIG. 4(d).

Further, based on the SW signal of the input terminal (2), the gate circuit (7) detects the gate signal shown in FIG. Forms and outputs a pulse-width gate signal.

Then, during the period when the gate signals of the comparator circuit (5) and the gate circuit (7) overlap, that is, during the reproduction detection period of the single frequency signal to be detected, the AND gate (8) samples and holds the output, and the gate signal causes The sample and hold circuit (9) samples and holds the output signal of the conversion circuit (3), and at this time, the voltage of the output signal of the conversion circuit (3) changes according to the reproduction frequency of the single frequency signal containing the RF multiplied signal. Therefore, from the sample hold circuit (9) to the output terminal G
The voltage of the hold signal output to O also changes depending on the reproduction frequency of the single frequency signal, and the hold signal is output to P
CΔ (becomes the detection signal of the minimum bit inversion period of the signal.

Note that the signal at the output terminal Q (l) is the PL of the voltage controlled oscillator.
is input to the adder in the L control circuit, and the adder causes
The control voltage signal formed by LL control and the output terminal (
10 signals are added, and the voltage controlled oscillator is controlled by the output signal of the adder.

Next, a minimum bit inversion period detection circuit having a second configuration will be explained. The detection circuit is composed of an arithmetic circuit that calculates a preset arithmetic expression based on a detection signal of the rotational speed of the rotary head, that is, a detection signal of the scanning speed, and a detection signal of the tape running speed. Outputs a signal similar to .

In other words, in order to reproduce the reproduced PCM signal by controlling the frequency of the sampling clock in accordance with the reproduced PCM signal, regardless of the reproduction mode, the R-DAT conventionally has the above-mentioned first or second configuration. A minimum bit inversion period detection circuit is provided.

In addition, instead of controlling the frequency of the sampling clock, for example, by the detection signal of the minimum bit inversion period detection circuit,
It is also possible to reproduce the reproduced PCM signal by controlling the reproduction servo circuit to control the scanning speed of the rotary head and variably controlling the relative speed between the tape and the head in accordance with the reproduction PCM signal.

In addition, this type of playback device such as a rotary head type tape recorder and a disk playback device other than R-DAT,
That is, even in a reproducing apparatus that reproduces a recording medium such as a magnetic tape or a magnetic disk on which at least a PCM signal and a single frequency signal are time-divisionally recorded, in order to reproduce the reproduced PCM signal, the above-mentioned first and second It is necessary to provide a minimum bit inversion period detection circuit similar to the minimum bit inversion period detection circuit of configuration 2.

[Problem that the invention seeks to solve]

By the way, in the case of the minimum bit inversion period detection circuit of the first configuration, the RF multiplied signal AM detection level is as follows.

It also changes due to differences in tape material, recording conditions, RF multiplied signal dropout, aging, etc., making it difficult to form the gate signal of the comparison circuit (5) accurately, and also making it difficult to form the gate signal of the gate circuit (7). The gate signal is S
Since it is formed based on the W signal, it is difficult to form the gate signal of the gate circuit (7) accurately when the margin area where the single frequency signal to be detected is recorded is narrow. .

Then, the sample and hold circuit (9) detects the RF of the margin area where the single frequency signal to be detected is recorded.
There is a problem in that the output signal of the conversion circuit (3) based on the doubled signal cannot be accurately sampled and held, and the minimum bit inversion period cannot be detected accurately.

In addition, there is a problem with the minimum pit inversion period detection port of the second configuration, and the minimum bit inversion period is indirectly detected by the detection signal of the scanning speed of the rotary head and the detection signal of the tape speed without using the RF multiplied signal. As a result, it is difficult to increase the detection accuracy beyond a certain level, and as with the first configuration, there is a problem that the minimum bit inversion period cannot be detected accurately.

[Failure to solve the problem]

The present invention has been developed with the above-mentioned points in mind, and is provided in a reproducing apparatus for reproducing a recording medium on which at least a PCM signal and a single frequency signal are time-divisionally recorded, and the reproducing apparatus is provided to reproduce the reproduced PCM signal. In the minimum bit inversion period detection circuit that detects the minimum bit inversion period of
a voltage conversion unit; based on a comparison between the voltage signal and a detection reference voltage of a reproduction frequency range of the single frequency signal, and a comparison between a fluctuation voltage of the voltage signal and a detection reference voltage of a flat portion of the voltage signal;
a flat part detection section that detects a flat part of the voltage signal based on the single frequency signal and outputs a detection pulse;

A minimum bit inversion period detection circuit comprising a sample and hold unit that samples and holds the voltage signal of the flat portion based on the detection puffless and outputs the held voltage signal as a detection signal of the minimum bit inversion period. be.

[For production]

Therefore, the frequency/voltage converter converts the frequency of the reproduced signal into a voltage, and the flat part detector detects the voltage of the voltage signal of the frequency/voltage converter and the fluctuation voltage of the voltage signal, and detects the head A flat portion of a voltage signal due to a single frequency signal is detected without generating a gate signal from a switching signal or the like.

Furthermore, based on the detected puff frequency of the flat part detection part, the sample and hold part samples and holds the voltage signal of the detected flat part, and the detection signal of the voltage proportional to the minimum bit inversion period of the reproduced PCM signal is sampled and held. The minimum bit inversion period is detected.

〔Example〕

Next, this invention. This embodiment will be described in detail with reference to FIGS. 1 to 12 showing examples thereof.

(First Embodiment) First, the first embodiment will be explained with reference to FIGS. 1 to 8 showing the first embodiment.

Figure 1 shows the case where it is applied to R-DAT. In the example in the figure, αB is the input terminal of the reproduced signal, and (6) is the input terminal qυ
The frequency/voltage converter CI4 is connected to the converter (2
) is connected to the flat part detection section, (14) is the detection section (to)
The gate pulse generation circuit connected to
) is a sample-and-hold circuit that samples and holds the output signal of the generator circuit α using the sump frequency gate signal of the generator circuit α.
form.

As shown in FIG.
It consists of a monostable multivibrator (hereinafter referred to as MM) (g), a low-pass filter (11), and forms a reproduced signal when the input terminal is 0, that is, an RF multiplied signal FM demodulation circuit of the rotary head.

By the way, R of input terminal (1) in standard playback mode
Figure 3 (a) for each scan of the F-fold signal and the rotating head.
As shown in the figure, the signals are recorded on each track.

In addition, in Fig. 3(a), (A), CB)
(C) is the PCM audio area, (D) and (E) are the subcode areas, and (F) are the margin areas at the start and end of the trace.

(G) are tracking regions, (E(), (I
) and (J) are the intermediate margin areas, respectively.

And areas (C), (D), and (E) each have a PC.
M signal is recorded, pilot signals are recorded in areas (F) and CG), and areas (A) and (B) I
Single frequency signals for margin are recorded in H), (I), and (J), respectively.

Note that the pilot signals in regions (, F) and (G) are signals with a higher frequency than each 1-station wave number signal, that is, a single frequency signal not used for detection.

On the other hand, in the special playback mode, for example, in the search mode for high-speed playback in the forward direction, the input terminal (one RF multiplied signal, as shown in FIG. 4(a), The signal is obtained by diagonally crossing the track of (A)' in the figure.

CB)', -, (I)', (J)' are shown in Figure 3 (
Each area (A), (B) of a).

. . . In addition to the signal portions of the regions corresponding to (I) and (J), the reproduction level varies greatly due to scanning of the reverse azimuth portion, etc.

Then, the power of the comparator a is determined based on the threshold level Vs of FIGS. 8(a) and 4(a), and the input RF multiplied signal m
0. Based on the output signal of the comparator 0η, the duty cycle of the output signal changes according to the input RF multiplied signal frequency.

Furthermore, the filter 09 to which the output signal of M changes in proportion to the frequency of

That is, the converter (2) converts the RF multiplied signal frequency into a voltage, and outputs a voltage signal obtained by converting the frequency of the low frequency component required for single frequency detection into a voltage.

The voltage signals of the converter α for the RF multiplied signals in FIGS. 3(a) and 4(a) are shown in FIGS. 3(b) and 4(b).
As shown in each figure, since the reproduction frequency is constant in the single frequency signal part, it is basically at a constant level, but for example, as shown in the fluctuating part (α) in Figure 4 (1)), , when the RF multiplied signal level is low, level fluctuations occur.

Next, the detection unit 0 to which the voltage signal of the conversion unit (6) is input
3 has four comparators (A), (21
1゜■, @, a differential circuit (24I) formed by a capacitor (CI), a resistor (R1), a charging circuit formed by a resistor (R2), a capacitor (C2), and a waveform shaping gate ■ Note that (10B) in the figure is the positive power supply voltage terminal.

The comparator Q1) is provided to detect the voltage signal in the reproduction frequency range of the single frequency signal, and the comparator
The non-inverting input terminal (+) of the comparator (2II), the reference voltage terminal (A), Voltages Vh and VO are applied respectively.

Further, in the comparator, (23I is provided to detect the flat part of the voltage signal, and the non-inverting input terminal (+) of the comparator -,
A reference voltage terminal, C, is connected to the inverting input terminal (-) of comparator G.
30+ detection reference voltages, that is, positive and negative limit voltages Vp and Vn of a gradual voltage fluctuation range of a voltage signal based on a single frequency signal, respectively, are applied.

The voltage signal of the converter @ is input to the inverting input terminal (-) of the comparator and the non-inverting input terminal (+) of the comparator, respectively, and after being differentiated in the differentiating circuit, the voltage signal is The signal is input to the inverting input terminal (-) of the comparator 123 and the non-inverting input terminal (+) of the comparator 123).

Now, as shown in Fig. 6(a), for example, Fig. 3(b)
) is input to the detection unit αJ.

Note that the time axis in FIG. 6(a) has been expanded from that in FIG. 3(b). Further, (β) and (γ) in FIG. 6(a) indicate fluctuations due to noise or the like.

Then, the comparators - and [21+ detect whether the voltage of the voltage signal is in the range of Vh to v6, and
If the voltage is in the range of , both the comparator (a) and the transistor in the output stage of 1211 are turned off.

Still, based on the voltage signal of FIG. 6(a), the differential signal of FIG. 6(b) is input from the differentiating circuit to the comparator,
The comparator (231) changes the voltage of the differential signal from Vp to V
It is detected whether the voltage is in the range of n, and if the voltage is in the range of Vp to Vn, both the comparator tn and the transistor in the output stage of (231) are turned off.

Therefore, only when the voltage of the voltage signal becomes a voltage in the range of vh to V6 and the fluctuating voltage of the voltage signal becomes a voltage in the range of Vp to Vn, that is, the voltage of the flat part due to a single frequency signal. , all the final stage transistors of comparators (4) to are turned off.

By the way, the emitter of the final stage transistor of each comparator (231) is grounded, and the collector is connected to a resistor (231).
R2) is connected to the connection point of the capacitor (C2).

Then, only when the final stage transistors of all the comparators C31 are turned off, the capacitor (C2) is charged as shown in FIG. If the final stage transistor turns on at any time, the capacitor (C2) is immediately reset and discharged.

Furthermore, when the capacitor (C2) is charged for a certain period of time and the charging voltage reaches the threshold level of gate (261) v Vs' shown in FIG. The output signal of the gate is held at a high level until the capacitor (C2) is reset and discharged.

That is, the detection unit side detects the flat part of the voltage signal based on the single frequency signal, and at this time, in order to prevent the voltage signal from fluctuating during the sample and hold period of the sample and hold unit QQ due to noise etc., the voltage signal is A high-level detection pulse consisting of the output signal of gate (2) is output only when a flat portion that remains flat for a certain period of time or more is detected.

Next, the generation circuit α→ and the sample hold circuit αQ are configured as shown in FIG.
]) The sample hold circuit α9 consists of the first sample hold circuit α9, the second sample hold circuit t32), and (33+).

MMC3]) is triggered by the rising edge of the detection pulse and has a period τ set by a time constant.

In other words, for the period τ required for sample and hold, the Q output terminal (q) goes high and the output terminal (q
) becomes low level, the first gate signal Ga for sample bold is output from the Q output terminal (q) to the first sample hold circuit +321, and the second gate signal Ga is output from the Q output terminal (q) to the second sample hold circuit +321. ) outputs a second gate signal Gb for sample and hold.

In addition, both sample hold circuits connected in series □□□,
+331 are configured in the same manner using, for example, a sample and hold circuit, a capacitor, and an amplifier for output buffer, and are controlled to be in sample mode and hold mode inversely with each other by first and second gate signals Ga and Gb. .

Note that the sample and hold circuit (32) turns on the sample and hold switch while the first gate signal Ga is at the high level and enters the sample mode, and the sample and hold circuit (33) enters the sample mode when the second gate signal Gb is at the high level. During this time, the sample hold switch is turned on and the sample hold mode is entered.

Then, the sample hold circuit +315 is shown in FIG. 8(a).
When the voltage signal in the region (J) of FIG. 3(b) shown in FIG. 3(b) is input, the detection pulse of FIG. 6(d), that is, the detection pulse shown in FIG. 3]) and is output from the output terminal a) of MMe3υ at this time. only goes into hold mode.

Therefore, the sample and hold signal becomes a voltage signal input immediately before the detection pulse, ie, a voltage signal of the detected flat portion, during the period τ from the leading edge of the detection pulse, as shown in FIG. 2(d).

Furthermore, based on the second gate signal Gb in FIG. 8(e) which is output from the Q output terminal (q) of MM (3υ) to the sample and hold circuit (33) based on the detection pulse, the sample and hold circuit is activated only for the sample and hold. become.

Therefore, the output signal of the sample and hold circuit i331 becomes the hold mode output signal of the sample and hold circuit i33), that is, the signal of the detected flat part, as shown in FIG. The frequency changes in exact proportion to the reproduction frequency of the signal.

That is, the sample and hold section αG samples and holds the voltage signal of the detected flat part based on the detection pulse of the detection section α field! The voltage of the output signal in (8) changes in proportion to the reproduction frequency of the single frequency signal, and the reproduction frequency of the single frequency signal is proportional to the minimum bit inversion period of the reproduction PCM signal, so it is a held voltage signal. The output signal of the sample hold circuit (33) is output as a detection signal of the minimum bit inversion period of the reproduced PCM signal.

In the case of the minimum bit inversion period detection circuit shown in Fig. 1, the detection circuit is based on a single frequency signal, using only the voltage signal of the converter (2) which has been converted into an RF multiplied signal, without using a head switching pulse signal or the like. In order to directly detect the flat part of the voltage signal and to detect the sample-hold inversion cycle of the detected flat part of the voltage signal, the RF multiplied signal reproduction level /L/
Even if the CAM detection signal (L/) changes due to differences in tape material, recording conditions, etc., the minimum bit inversion period can be detected accurately and reliably.

In addition, since no complicated arithmetic circuit is required, the configuration is simplified and the cost is reduced, and adjustment is also simpler than, for example, when a head switching pulse signal is used.

By the way, based on the comparison of the comparator (n, f21+), a voltage signal in the range of vb to V6 set by the detection reference voltage Vh and V6 of the voltage terminal, that is, a voltage signal in the reproduction frequency range of the single frequency signal is detected. In order to detect the flat part of the PCM signal whose voltage is outside the range of vh to Vl,
There is no possibility of erroneously detecting a flat part of a voltage signal such as a pilot signal.

Since false detection based on a single frequency pilot signal different from a single frequency signal is prevented, R-D A
When applied to a playback device other than T, for example, even if the playback signal includes a PCM signal, a single frequency signal to be detected, and one or more single frequency signals with different frequencies that are not detected, As long as the voltage in the reproduced frequency range of each single frequency signal to be detected does not overlap Vh - Vl, the flat part of the voltage signal based on the single frequency signal to be detected is accurately detected, and the minimum pit inversion of the reproduced PCM signal is achieved. The cycle can be detected accurately.

(Second Embodiment) Next, FIGS. 9 to 11 showing a second embodiment will be described.

In FIG. 9, the same symbols as in FIGS. 1 to 8 indicate the same things, and the difference from the first embodiment is that instead of the gate pulse generating circuit 0 in FIG. Gate pulse generation circuit (341, 0151 and reset circuit (
7) is provided with a gate pulse generation circuit 37).

The generation circuits +341, 1351 and the reset circuit (to) are configured as shown in FIG.
(It is a MM consisting of a CI 28 integrated circuit, and has resistors (R8) and (R4) for time constants, respectively.

(R5) and capacitors (C3), (C4), (C
5), the time constant is set, and the clear terminal <ce) is connected to the power supply terminal (10B), and M M f3
The detection pulse of the converter (to) is input to the rising trigger terminal (i) of 81.

(41) is a flip-flop (hereinafter referred to as FF) made of an integrated circuit with model number 74HC74, and the detection pulse of the detection section (to) is input to the data input terminal (d) and the clear terminal (C6), and the clock MMQOI on terminal
The output signal of the output terminal (Nae) is input, and the output signal of the output terminal
) output signal to the falling trigger terminal of M M '39i (
i).

(421, t, 43+ are inverters connected to the Q output terminal (Q) of M M!381 and the Q output terminal α of M M (391), respectively, and the first gate is connected to the inverter!4z color sample hold circuit t3a. A third gate signal Gc instead of the signal Ga is output, and the inverter (
A fourth gate signal Gd instead of the second gate signal GbO is output from the sample-and-hold circuit G31.

In addition, the falling trigger terminal (T) of MM So is grounded,
MN i3ri! , the rising trigger terminal (i) of FFHn and the preset terminal (pr) of FFHn are connected to the power supply terminal (10B
)It is connected to the.

Also, MM! 3&! output terminal G) is M M (
Connected to the falling trigger terminal (T) of 4■, M M f
A pull-up resistor (R6) is provided between the top output terminal surface of 39) and the power supply terminal (10B).

Then, the voltage signal shown in FIG. 11(a), that is, the voltage signal in which the fluctuation part (δ) due to RF multiplied signal level drop, noise, etc. exists in the region of a single frequency signal, is input to the input terminal α. In this case, there is a delay in the charging and discharging of 1 in the charging circuit based on the transmission time of the comparator in the detection part, so to be more precise, the charging voltage is delayed by the delay time as shown in Figure (b). It changes with a delay of ΔT, so
The rising and falling edges of the detection pulse are output with a delay of ΔT as shown in FIG. Note 5 Figure 11(b).

ts and ts' in (e) indicate the timings at which the charging voltage reaches the threshold level Vs' and the detection pulse rises, respectively.

By the way, in the case of the first embodiment, the first . The second gate signals Ga and Gb are inverted, and the sample and hold circuit +3z, (3 (to) becomes the hold mode and sample mode respectively. For example, if the rising edge ts of the detection pulse shifts to the position of the fluctuation part (δ),
The hold voltage of the sample and hold section αQ is
), which may result in erroneous detection of the minimum bit inversion period.

Therefore, in this embodiment, a reset circuit (to) is especially provided to control the sample and hold circuit (33) to the hold mode only when the detection pulse does not fall within a period ΔT' that is slightly longer than the delay time ΔT from the rise. This prevents the above-mentioned false detection.

That is, in FIG. 10, the detection pulse signal of FIG. 11(C) is M M ! 381, M M
The GFA is triggered at each of the rising edges ts and ts' of the detection pulse, and the Q of M M +38i is maintained for a period τ' set by a resistor (R8) and a capacitor (C3).
The output signal of the output terminal (q) and the output signal of the G output terminal (q) become high level and low level, respectively, and at this time, the output signal of the Q output terminal (9) of the MMI381 is inverted by the inverter +42), From the inverter (421) to the sample hold circuit f3Z, the third
A gate signal Gc is output.

Also, the output signal from the Kuzu output terminal surface of M M 138+ is M
M (4Q double input sale, M M (401u, M M
+38i OQ is triggered at each falling edge of the output signal of the output terminal G), that is, each rising edge ts, ts' of the detection pulse, and resistor (R4).

The output signal on the G output terminal surface becomes high level for a period ΔT' set by the capacitor (C4).

Furthermore, while a high level detection pulse is not input, F
M
Only when the output signal on the output terminal surface 4010 falls, the output signal on the set output terminal (q) falls to low level.

That is, the output signal of the FF (41 + output terminal G) continues to be output for a period longer than the period ΔT' from the rise of the detection pulse, and the flat part of the single frequency signal fluctuates for a period longer than the period ΔT from the rise of the detection pulse. 1st only when not
As shown in Figure 1 (e), the period Δ from the rise of the detection pulse
After T' has elapsed, it falls to a low level and is held at a low level until the detection puffless falls.

Furthermore, due to the fall of the output signal of F
, becomes low level for a period τ set by the capacitor (C5).

Then, the output signal of the output terminal α) connected to M M color 9) is inverted by the inverter (431),
From 3 to sample hold circuit (3), Fig. 1t (f)
A fourth gate signal Gd shown in is output.

That is, the generator circuit outputs the third gate signal Gc falling to a low level in synchronization with the rise of the detection pulse to the sample hold circuit [3Z, and outputs the third gate signal Gc to the sample bold circuit 13
Switch Z from sample mode to hold mode.

At this time, if the mode switching of the sample-and-hold circuit 134 deviates to the position of the variation part (δ), for example, based on the delay in the rise of the detection pulse, the output signal of the sample-and-hold circuit +321 is disturbed by the variation part (δ).

On the other hand, when the detection pulse falls within a period of 217 from the rising edge of the reset circuit (to), that is, when the output signal of the sample and hold circuit (3'A) may be disturbed by the fluctuation part (δ), etc., the FF (41 + G output terminal (q
) is held at a high level to reset and hold the generating circuit (351), and only when the detection pulse falls with a delay of more than a period ΔT' from the rise, the period ΔT' has elapsed since the rise of the detection pulse. Afterwards, the reset signal is set to low level to release the reset on the generating circuit side.

Further, the generation circuit (351) outputs the fourth gate signal Gd that rises in synchronization with the falling edge of the reset signal to the sample and hold circuit 133) only when the reset is released, and the sample and hold circuit 133) 4 gate signal G
d Switch to sample mode only during the high level period.

Then, the sample and hold circuit G3+ is configured such that the output signal of the second hold mode of the sample and hold circuit is in the variation section (δ
), etc., the output signal of the hold mode of the sample and hold circuit port 4 is sampled and held.

Therefore, the hold voltage of sample and hold section 0Q,
In other words, the voltage of the detection signal of the minimum bit inversion period is not affected by charging and discharging delays of the charging circuit, and more accurately detects the minimum bit inversion period of the reproduced PCM signal compared to the first embodiment. Detection can be performed.

Note that in order to switch the sample and hold circuit f331 to the ho/read mode before the sample and hold circuit G2 switches to the sample mode, the fall of the fourth gate signal Gd is set before the rise of the third gate signal Gc by a period ΔT'. The time constant of M M @9i etc. are set so that.

(Third Embodiment) Next, FIG. 12 showing a third embodiment will be described.

In FIG. 12, 031' is the detection unit α1 of the first embodiment.
It is a flat part detection section provided in place of , and the detection section αJ
In the charging circuit G, a counter (42,
It is formed using an inverter (431).

KE is a gate pulse generation circuit provided in place of the generation circuit α4 of the first embodiment, and instead of M M (to),
F F f44), counter (4 equal, inverter ←0
and Nante Gate T471, Anto Game) 148
It is formed using 1.

The counter (42) has a clear terminal (CI) connected to the power supply terminal (10B) via a pull-up resistor (R7), and is connected to the output terminal of each comparator (231), and The reference clock for counting of the clock terminal (49) is input to the clock terminal, and the output terminal (
The output signal of qn) is fed back to the enable terminal (en) via an inverter (431).

In addition, the clock terminal of the FF (441) is connected to the output terminal (Qn) of the counter (4), the data input terminal (d) is connected to the power supply terminal (10B), and the Q output terminal (q) is connected to the output terminal (Qn) of the FF (441). The clear terminal of the counter (4) and the Nant gate (4η) are connected to the AND gate (48).

Furthermore, the counter (451) has a clock terminal connected to the input terminal 9), and an output terminal (qn) connected to the clear terminal of the FF 4) via the inverter +46).
>, a Nant gate uη, and an AND gate t48).

Then, when the transistor at the final stage of the comparator ~ edict is turned off, the counter clear reset of 4 is released,
The counter u4 counts the reference clock of the input terminal (49), and when a period of time equal to the fixed time required for the charging voltage of the capacitor (C2) of the charging circuit to reach the threshold level Vs' has elapsed, the counter u4 counts the reference clock of the input terminal (49). output terminal (q
The output signal of n) is inverted from low level to high level.

Note that when the terminal transistor of any one of the comparators (1) to (c) turns off, the counter a7J is immediately cleared and reset.

Also, the counter! When the output signal of the output terminal (Qn) of 4z rises to high level, the enable terminal (en) of counter 47J falls to low level, and at this time, counter 4z stops counting operation.

Therefore, the counters L, A'2, (431) act in the same manner as the charging circuit G and the gate, and the detection unit 03' outputs a detection pulse similar to the detection pulse of the detection unit α3.

Next, when the output signal of the output terminal ((In) of the counter (4z) rises, the output signal of the Q output terminal (q) of the FF (44) rises to a high level, and at this time, the output signal of the counter (45)
1 clear reset is canceled.

Then, the counter (451) counts the reference clock of the input terminal (49), and when the period τ set by the time constant of MMCIυ has elapsed, the output signal of the output terminal (Qn) of the counter (4151) becomes high level. stand up

By the way, when the output signal of the Q output terminal (q) of the FF (2) rises to a high level, the output signal of the output terminal (Qn) of the counter (4 (g)) is held at a low level. Therefore, the output signal of the Nandt gate t471 falls to a low level, and the output signals of the AND gates (4 to 4) rise to a high level.

Then, when the output signal of the output terminal (qn) of the counter (451) rises to a high level, at this time F F (441
Since the output signal of the Q output terminal (q) of the NAND gate 471 is held at a high level, the output signal of the NAND gate 471 rises to a high level, and the output signal of the NAND gate 1481 falls to a low level.

Further, when the output signal of the counter (441) output terminal (q) falls to a high level ρ, the FF (441) is cleared and reset, and the output signal of the Q output terminal (q) falls to a low level.

Therefore, the output signal of Nando Game) 17] is MMO
It changes in the same way as the output signal of the Q output terminal (q) of υ, and the output signal of the Antogame 14 (to) changes in the same way as the output signal of the Q output terminal (q) of MMC3υ.

Then, the output signal of the Nantes gate ←η is used as the first gate signal Ga as the sample ho tv )' II i in FIG.
Since the output signal of the AND gate (49) is output as the second gate signal to the sample hold circuit +33+ in the same figure, the generation circuit α4 is output to the generation circuit a
Works the same as <.

In the case of this embodiment, the charging circuit (251, MM
(Instead of 391 etc., counter 2, +4+
5), FF←(1), etc., and has the advantage of being able to integrate the circuit, especially since no charging circuit is provided.

In each of the above embodiments, the case where the present invention is applied to the R-DAT has been described, but it is of course applicable to various other main devices other than the R-DAT, and in this case, the present invention can be applied to various main devices other than the R-DAT. As in, a PCM signal, a single frequency 'e! Even if one or more single-frequency signals with frequencies different from the single-frequency signal have been time-divisionally recorded together with the single-frequency signal, the flat part of the voltage signal based on the single-frequency signal is detected, and the minimum bit inversion is performed. Periods can be detected.

〔Effect of the invention〕

As described above, according to the minimum bit f inversion period detection circuit of the present invention, the frequency/voltage converter converts the frequency of the reproduced signal into a voltage, and the flat part detector converts the voltage signal of the frequency/voltage converter into a voltage. Based on the detection of the voltage of the voltage signal and the voltage fluctuation of the voltage signal, the flat part of the voltage signal by the single frequency signal is detected without generating a gate signal from the head switching signal etc., and the detection pulse of the flat part detection part is detected. Based on this, we sampled and held the output voltage signal of the flat part and detected the minimum bit inversion period of the reproduced PCM signal. It can be detected accurately.

[Brief explanation of the drawing]

1 to 8 show a first embodiment of the minimum bit inversion period detection circuit of the present invention, FIG. 1 is a block diagram, and FIG.
Figures 5 and 7 are detailed book diagrams of each part, Figure 3 (a), (b), and Figure 4 (a), (b).
6(a) to (d) and FIG. 8(a) to (f) are timing charts for explaining the operation of each part, FIG. 9 is a block diagram of the second embodiment of the present invention, and FIG. 10 is a detailed wiring diagram of a part of FIG. 9, FIGS. 11(a) to (f) are timing charts for explaining the operation of FIG. 10, and FIG.
Figures (a) to (f) are timing charts for explaining the operation of Figure 13. □□□・・・Frequency/voltage converter, (13, αa′・
... Flat part detection section, αG, ae'... Sample hold section.

Claims (1)

[Claims] (1) A minimum bit inversion period detection circuit, which is provided in a reproducing device for reproducing a recording medium on which at least a PCM signal and a single frequency signal are time-divisionally recorded, and detects the minimum bit inversion period of the reproduced PCM signal, a frequency/voltage conversion unit that converts the frequency of the reproduced signal into a voltage and outputs a voltage signal that changes in proportion to the frequency of the reproduced signal; and a detection reference voltage for the reproduced frequency range of the voltage signal and the single frequency signal. Based on the comparison of the fluctuation voltage of the voltage signal and the detection reference voltage of the flat part of the voltage signal,
a flat part detection unit that detects a flat part of the voltage signal based on the single frequency signal and outputs a detection pulse; 1. A minimum bit inversion period detection circuit, comprising: a sample hold section that outputs a minimum bit inversion period detection signal.