JPH0685327A - Manufacture of optical semiconductor device - Google Patents
Manufacture of optical semiconductor deviceInfo
- Publication number
- JPH0685327A JPH0685327A JP4233244A JP23324492A JPH0685327A JP H0685327 A JPH0685327 A JP H0685327A JP 4233244 A JP4233244 A JP 4233244A JP 23324492 A JP23324492 A JP 23324492A JP H0685327 A JPH0685327 A JP H0685327A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- optical semiconductor
- optical
- smd
- light emitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
- Led Device Packages (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、立体電極を施したリー
ドレスタイプの面実装型光半導体装置の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a leadless type surface-mount type optical semiconductor device having a three-dimensional electrode.
【０００２】[0002]
【従来の技術】従来の技術について図４乃至図６を参照
して説明する。図４及び図５は、従来のリードレスタイ
プの面実装型光半導体装置（以下、ＳＭＤ光半導体装置
と記す）の製造工程を示す平面図、図６（ａ）は完成し
たＳＭＤ光半導体装置の平面図、図６（ｂ），（ｃ）は
それぞれ、図６（ａ）のＡ−Ａ’断面図及びＢ−Ｂ’断
面図である。2. Description of the Related Art A conventional technique will be described with reference to FIGS. 4 and 5 are plan views showing a manufacturing process of a conventional leadless surface-mount type optical semiconductor device (hereinafter referred to as SMD optical semiconductor device), and FIG. 6A shows a completed SMD optical semiconductor device. The plan view and FIGS. 6B and 6C are respectively the AA ′ sectional view and the BB ′ sectional view of FIG. 6A.
【０００３】図４に示すように、樹脂基板１には、立体
電極を形成するスルーホールメッキ部２及び受発光素子
３を搭載するためのヘッダー部４、前記受発光素子３を
Ａｕワイヤ５で結線するための２ｎｄ部６からなるメッ
キパターン７を形成している。この樹脂基板１のヘッダ
ー部４に受発光素子３をダイボンドし、次いでこの受発
光素子３と２ｎｄ部６をＡｕワイヤ５で結線する。As shown in FIG. 4, a resin substrate 1 is provided with a through-hole plated portion 2 forming a three-dimensional electrode, a header portion 4 for mounting a light emitting / receiving element 3, and the light emitting / receiving element 3 with an Au wire 5. A plating pattern 7 composed of the 2nd portion 6 for connection is formed. The light emitting / receiving element 3 is die-bonded to the header portion 4 of the resin substrate 1, and then the light receiving / emitting element 3 and the 2nd portion 6 are connected by an Au wire 5.
【０００４】次に、図５に示すように、複数の受発光素
子３を横一列に覆うようにして、透光性樹脂８を用いて
トランスファーモールドする。この際、各受発光素子３
上にレンズ９を形成するようにする。その後、ダイシン
グライン１０の位置で分割カットすることにより図６
（ａ）乃至（ｃ）に示すような単独のＳＭＤ光半導体装
置が完成する。Next, as shown in FIG. 5, a plurality of light emitting / receiving elements 3 are covered in a row in a horizontal direction, and transfer molding is performed using a transparent resin 8. At this time, each light emitting / receiving element 3
The lens 9 is formed on the top. After that, by dividing and cutting at the position of the dicing line 10, as shown in FIG.
A single SMD optical semiconductor device as shown in (a) to (c) is completed.
【０００５】[0005]
【発明が解決しようとする課題】ところで、従来方法に
よって得られた単独のＳＭＤ光半導体装置を複数個、基
板等に並べて実装使用する場合があるが、この際には個
々のＳＭＤ光半導体装置の位置ずれが生じ高精度の実装
位置を得ることは困難であった。また、その場合、各Ｓ
ＭＤ光半導体装置の電極すべてについてそれぞれ半田付
を行う必要があり、手間がかかりコストアップにつなが
っていた。By the way, there are cases where a plurality of single SMD optical semiconductor devices obtained by the conventional method are mounted side by side on a substrate or the like. In this case, the individual SMD optical semiconductor devices are mounted. It was difficult to obtain a highly accurate mounting position due to the displacement. In that case, each S
It is necessary to solder all the electrodes of the MD optical semiconductor device, which is troublesome and leads to an increase in cost.
【０００６】そこで、本発明の目的は、複数の受発光素
子を基板等へ実装する時、各受発光素子の実装を高精度
に位置決めできるとともに、実装工程を簡略化できる光
半導体装置の製造方法を提供することにある。Therefore, an object of the present invention is, when mounting a plurality of light emitting / receiving elements on a substrate or the like, can mount each of the light emitting / receiving elements with high accuracy and simplify the mounting process. To provide.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するため
に本発明は、樹脂基板に立体メッキパターンを形成し、
該立体メッキパターンに複数個の光学素子を搭載し、そ
の後前記各光学素子をモールドした後分割カットしてリ
ードレスタイプの面実装型光半導体装置を製造する光半
導体装置の製造方法において、前記立体メッキパターン
は前記複数個の光学素子を電気的に接続するように形成
されてなり、前記分割カット時に前記複数個の光学素子
を連結一体化するようカットしてなることを特徴とす
る。In order to achieve the above object, the present invention provides a three-dimensional plating pattern on a resin substrate,
In the method for manufacturing an optical semiconductor device, a plurality of optical elements are mounted on the three-dimensional plating pattern, and then the optical elements are molded and then divided and cut to manufacture a leadless type surface mount optical semiconductor device. The plating pattern is formed so as to electrically connect the plurality of optical elements, and is cut so as to connect and integrate the plurality of optical elements at the time of the division cutting.
【０００８】[0008]
【作用】本発明による光半導体装置の製造方法は、上記
のような方法であるので、これによって得られるＳＭＤ
光半導体装置は、各光学素子が同一樹脂基板上に一体的
に搭載されることとなり、基板等への実装時には各光学
素子の位置がばらつくことなく、高精度の位置合わせが
できる。さらに、各光学素子はパターンによって電気的
に接続されているので、基板への実装時、従来のように
各光学素子ごとにすべての電極を半田付する必要はない
ので、工程数の低減化、コストダウンを図れる。The method of manufacturing an optical semiconductor device according to the present invention is the method as described above, and the SMD obtained thereby is obtained.
In the optical semiconductor device, each optical element is integrally mounted on the same resin substrate, and when mounted on a substrate or the like, the position of each optical element does not vary, and highly accurate alignment is possible. Furthermore, since each optical element is electrically connected by a pattern, it is not necessary to solder all the electrodes for each optical element when mounting on a substrate, which reduces the number of steps, The cost can be reduced.
【０００９】[0009]
【実施例】本発明の一実施例について、図１乃至図３を
参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.
【００１０】図１及び図２は、本実施例によるＳＭＤ光
半導体装置の製造工程を示す平面図、図３（ａ）は完成
したＳＭＤ光半導体装置の平面図、図３（ｂ），（ｃ）
はそれぞれ、図３（ａ）のＡ−Ａ’断面図及びＢ−Ｂ’
断面図である。なお、図４乃至図６に示す従来例と同一
機能部分には同一記号を付している。1 and 2 are plan views showing a manufacturing process of an SMD optical semiconductor device according to this embodiment, FIG. 3A is a plan view of a completed SMD optical semiconductor device, and FIGS. 3B and 3C. )
3A is a cross-sectional view taken along the line AA ′ of FIG.
FIG. The same functional parts as those of the conventional example shown in FIGS. 4 to 6 are designated by the same symbols.
【００１１】ここでは、従来例と異なる点についてのみ
説明する。図１は射出成型によって得られた樹脂基板１
に、各メッキパターン７、受発光素子３の搭載、Ａｕワ
イヤ５の結線を完了した状態を示す平面図である。ここ
で、図４に示す従来例と異なる点は、受発光素子３が搭
載されるメッキパターン７が、左右の他の受発光素子３
が搭載されるパターンに接続されている（図中、１１で
示す）点である。Here, only points different from the conventional example will be described. FIG. 1 shows a resin substrate 1 obtained by injection molding.
FIG. 3 is a plan view showing a state in which each plating pattern 7, mounting of the light emitting / receiving element 3 and connection of the Au wire 5 are completed. Here, the point different from the conventional example shown in FIG. 4 is that the plating pattern 7 on which the light emitting / receiving element 3 is mounted is different from the other light receiving / emitting elements 3 on the left and right.
Is connected to a pattern to be mounted (indicated by 11 in the figure).
【００１２】次に、図２に示すように、樹脂基板１に透
光性樹脂８によるトランスファーモールドを受発光素子
３上にレンズ９を形成するように行う。この後、ダイシ
ングライン１２に沿って分割カットする。この結果、図
３に示すように、２個の受発光素子３を有するＳＭＤ光
半導体装置が得られる。Next, as shown in FIG. 2, transfer molding is performed on the resin substrate 1 using the translucent resin 8 so that the lens 9 is formed on the light receiving / emitting element 3. After that, division cutting is performed along the dicing line 12. As a result, as shown in FIG. 3, an SMD optical semiconductor device having two light emitting / receiving elements 3 is obtained.
【００１３】以上のように、本実施例によって得られる
ＳＭＤ光半導体装置は、２個の受発光素子を有してお
り、従来のように、例えば基板等に２個のＳＭＤ光半導
体装置を併置する際に位置ずれが発生するといった問題
はない。しかも、２個の受発光素子を搭載するヘッダー
部のメッキパターンは、樹脂基板の状態で予め接続され
ているので（図中、１１で示すパターン部）、従来のよ
うに各ＳＭＤ光半導体装置のすべての電極について半田
付する必要はなく、工程の簡略化及びコストダウンを図
れる。例えば、図３（ａ）のように受発光素子３が２個
の場合、従来であれば電極ａ，ｂ，ｃ，ｄのすべてを半
田接続する必要があったが、本実施例においては、電極
ａ，ｂ，ｃを半田接続するだけでよい。As described above, the SMD optical semiconductor device obtained according to the present embodiment has two light emitting / receiving elements, and two SMD optical semiconductor devices are arranged side by side on a substrate or the like as in the conventional case. There is no problem that a position shift occurs when performing. In addition, since the plating pattern of the header portion on which the two light emitting / receiving elements are mounted is connected in advance in the state of the resin substrate (the pattern portion indicated by 11 in the figure), the conventional SMD optical semiconductor device Since it is not necessary to solder all the electrodes, the process can be simplified and the cost can be reduced. For example, when there are two light emitting / receiving elements 3 as shown in FIG. 3A, conventionally, all of the electrodes a, b, c, d had to be soldered, but in the present embodiment, Only the electrodes a, b and c need to be soldered.
【００１４】なお、本実施例においては、受発光素子を
２個有する場合をとりあげたが、２個以上の場合につい
ても、ダイシングラインを変更し分割カット数を変える
だけで、容易に実現できる。また、連結一体化する光半
導体装置に搭載する素子は同一素子に限るものではな
く、異なる種類の素子でもよい。さらに、メッキパター
ン形状、トランスファーモールド形状も上記例に限るも
のではない。In this embodiment, the case of having two light emitting / receiving elements is taken up, but the case of two or more light emitting / receiving elements can be easily realized by changing the dicing line and changing the number of divided cuts. Further, the elements mounted on the optical semiconductor device to be connected and integrated are not limited to the same element, but may be elements of different types. Further, the plating pattern shape and the transfer mold shape are not limited to the above examples.
【００１５】[0015]
【発明の効果】以上説明したように本発明によれば、基
板等にＳＭＤ光半導体装置の搭載素子を複数個位置合わ
せする際の位置ぎめ精度を向上できる。さらに、基板実
装時の工程数を低減でき、コストダウンを図れる。As described above, according to the present invention, it is possible to improve the positioning accuracy when aligning a plurality of mounting elements of an SMD optical semiconductor device with a substrate or the like. Further, the number of steps for mounting on the board can be reduced, and the cost can be reduced.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の一実施例によるＳＭＤ光半導体装置の
製造工程を示す平面図である。FIG. 1 is a plan view showing a manufacturing process of an SMD optical semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例によるＳＭＤ光半導体装置の
製造工程を示す平面図である。FIG. 2 is a plan view showing a manufacturing process of an SMD optical semiconductor device according to an embodiment of the present invention.
【図３】（ａ）は本発明の一実施例によるＳＭＤ光半導
体装置の平面図、（ｂ）及び（ｃ）はそれぞれ、（ａ）
のＡ−Ａ’断面図及び（ａ）のＢ−Ｂ’断面図である。3A is a plan view of an SMD optical semiconductor device according to an embodiment of the present invention, and FIGS. 3B and 3C are respectively FIG. 3A and FIG.
2A is a cross-sectional view taken along the line AA ′ of FIG.
【図４】従来例によるＳＭＤ光半導体装置の製造工程を
示す平面図である。FIG. 4 is a plan view showing a manufacturing process of a conventional SMD optical semiconductor device.
【図５】従来例によるＳＭＤ光半導体装置の製造工程を
示す平面図である。FIG. 5 is a plan view showing a manufacturing process of a conventional SMD optical semiconductor device.
【図６】（ａ）は従来例によるＳＭＤ光半導体装置の平
面図、（ｂ）及び（ｃ）はそれぞれ、（ａ）のＡ−Ａ’
断面図及び（ａ）のＢ−Ｂ’断面図である。6A is a plan view of an SMD optical semiconductor device according to a conventional example, and FIGS. 6B and 6C are AA ′ of FIG.
It is a sectional view and a BB 'sectional view of (a).
１ 樹脂基板 ３ 光学素子（受発光素子） ７’ 立体メッキパターン ８ モールド樹脂 １２ ダイシングライン 1 resin substrate 3 optical element (light emitting / receiving element) 7'three-dimensional plating pattern 8 mold resin 12 dicing line
Claims (1)
し、該立体メッキパターンに複数個の光学素子を搭載
し、その後前記各光学素子をモールドした後分割カット
してリードレスタイプの面実装型光半導体装置を製造す
る光半導体装置の製造方法において、 前記立体メッキパターンは前記複数個の光学素子を電気
的に接続するように形成されてなり、前記分割カット時
に前記複数個の光学素子を連結一体化するようカットし
てなることを特徴とする光半導体装置の製造方法。1. A leadless surface-mount type optical device in which a three-dimensional plating pattern is formed on a resin substrate, a plurality of optical elements are mounted on the three-dimensional plating pattern, and then each of the optical elements is molded and then divided and cut. In the method of manufacturing an optical semiconductor device for manufacturing a semiconductor device, the three-dimensional plating pattern is formed so as to electrically connect the plurality of optical elements, and the plurality of optical elements are connected and integrated at the time of the divided cut. A method for manufacturing an optical semiconductor device, which is characterized in that the optical semiconductor device is cut so as to be formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4233244A JPH0685327A (en) | 1992-09-01 | 1992-09-01 | Manufacture of optical semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4233244A JPH0685327A (en) | 1992-09-01 | 1992-09-01 | Manufacture of optical semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0685327A true JPH0685327A (en) | 1994-03-25 |
Family
ID=16952034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4233244A Pending JPH0685327A (en) | 1992-09-01 | 1992-09-01 | Manufacture of optical semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0685327A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001057446A (en) * | 1999-06-09 | 2001-02-27 | Sanyo Electric Co Ltd | Hybrid integrated circuit device |
| WO2003028103A2 (en) * | 2001-09-25 | 2003-04-03 | Intel Corporation | Multi-stack surface mount light emitting diodes |
| JP2005039129A (en) * | 2003-07-17 | 2005-02-10 | Sony Corp | Light source device and its manufacturing method, surface light emitting device and image information read device |
| JP2005045199A (en) * | 2003-07-25 | 2005-02-17 | Seoul Semiconductor Co Ltd | Chip light emitting diode and its manufacturing method |
| JP2007180234A (en) * | 2005-12-27 | 2007-07-12 | Matsushita Electric Ind Co Ltd | Light-emitting source, and luminaire |
| JP2007242792A (en) * | 2006-03-07 | 2007-09-20 | Avago Technologies Ecbu Ip (Singapore) Pte Ltd | Light emitting diode |
| JP2011171765A (en) * | 2011-05-24 | 2011-09-01 | Towa Corp | Optical device and method for assembling the same |
-
1992
- 1992-09-01 JP JP4233244A patent/JPH0685327A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001057446A (en) * | 1999-06-09 | 2001-02-27 | Sanyo Electric Co Ltd | Hybrid integrated circuit device |
| WO2003028103A2 (en) * | 2001-09-25 | 2003-04-03 | Intel Corporation | Multi-stack surface mount light emitting diodes |
| WO2003028103A3 (en) * | 2001-09-25 | 2003-12-18 | Intel Corp | Multi-stack surface mount light emitting diodes |
| US6833563B2 (en) | 2001-09-25 | 2004-12-21 | Intel Corporation | Multi-stack surface mount light emitting diodes |
| JP2005039129A (en) * | 2003-07-17 | 2005-02-10 | Sony Corp | Light source device and its manufacturing method, surface light emitting device and image information read device |
| JP4561056B2 (en) * | 2003-07-17 | 2010-10-13 | ソニー株式会社 | Manufacturing method of light source device |
| JP2005045199A (en) * | 2003-07-25 | 2005-02-17 | Seoul Semiconductor Co Ltd | Chip light emitting diode and its manufacturing method |
| JP2007180234A (en) * | 2005-12-27 | 2007-07-12 | Matsushita Electric Ind Co Ltd | Light-emitting source, and luminaire |
| JP2007242792A (en) * | 2006-03-07 | 2007-09-20 | Avago Technologies Ecbu Ip (Singapore) Pte Ltd | Light emitting diode |
| JP2011171765A (en) * | 2011-05-24 | 2011-09-01 | Towa Corp | Optical device and method for assembling the same |
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