JPH0685158A - Electric transmission line and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide an electric transmission line which is capable of minimizing an occupied area compared with the prior one by forming a grounding line on the sides of a groove formed on a semiconductor board. CONSTITUTION:A grounding conductor 12 formed in a side-wall part of a groove and a signal conductor formed on the bottom of the groove constitute an electric transmission line. This construction makes it possible reduce a lateral occupied area in order to form the grounding conductor 12, at the side wall part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric transmission line for propagating a high speed signal on a semiconductor surface and a method for manufacturing the electric transmission line.

[0002]

2. Description of the Related Art Today, semiconductor devices are becoming faster and higher in frequency.
Highly integrated technology has advanced remarkably. Microwave,
Even in the millimeter wave band, circuits that have been conventionally composed of individual elements have been integrated, and downsizing and low power consumption of the device have been realized. In addition, the importance of signal transmission paths between elements is increasing with the speeding up of elements. Conventionally, as a method for transmitting a high-speed signal on a semiconductor surface, a microstrip line and a coplanar line which are widely used for a signal transmission line of an analog high-speed element are used. A typical microstrip line is shown in FIG. Reference numeral 41 is an insulator having a high dielectric constant and serves as a semiconductor substrate in a semiconductor element. 42 is a strip conductor and 43 is a ground conductor.
The microstrip line is a modification of the parallel plate waveguide, and applies an electric field between the ground conductor 43 and the strip conductor 42 to propagate electromagnetic waves. The dotted line simply shows the electromagnetic field generated at this time.

A typical coplanar line is shown in FIG. The ground conductor of the micro strip line is arranged on the surface. Reference numeral 51 in FIG. 5 is a slit conductor. Similarly to the microstrip line, an electric field is applied between the ground conductor 43 and the strip conductor 51 formed on the surface to propagate electromagnetic waves. The dotted line simply shows the electromagnetic field generated at this time.

[0004]

However, in the microstrip line shown in FIG. 4, a connection process from the back surface such as a via hole is required to ground the semiconductor element formed on the surface, and the size of the via hole is large. Due to this limitation, integration is difficult. Further, since the signal lines have to be widened in order to reduce the interference between the signals, the proportion occupied by the transmission line becomes large, which is unsuitable for the integration of semiconductor elements.

The coplanar line shown in FIG. 5 has a simple structure because it is not necessary to deposit a metal for grounding on the back surface and is widely used as a transmission line between semiconductor ultra-high speed devices. It has a drawback that the area occupied by is large. Furthermore, when a plurality of signal lines are wired in parallel, a ground conductor is required between each signal line, and the proportion occupied by the wiring becomes large.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a good signal transmission line even in a highly integrated circuit and a manufacturing method thereof.

[0007]

In order to achieve this object, the present invention provides a conductor formed on a side surface, a conductor formed on a bottom surface, and a bottom portion of a conductor on a bottom surface in a groove formed on a semiconductor substrate. In addition, an insulating layer other than the semiconductor substrate and an insulating layer other than the semiconductor substrate are provided above the conductor on the bottom surface.

Further, as a means for forming this structure, a step of forming a groove in the semiconductor substrate, a step of depositing a conductor on the surface of the groove, and a step of forming a resist on a part of the bottom surface of the groove in which the conductor is deposited. And a step of etching in the direction perpendicular to the substrate to remove conductors other than the lower portion of the resist and side surfaces of the groove, a step of removing the resist, and a step of depositing an insulator. Further, a step of forming a groove in the semiconductor substrate, a step of depositing a conductor on the surface of the groove, a step of etching in a direction perpendicular to the substrate to remove a conductor other than the groove side surface, and an insulator are deposited. A step of depositing a conductor on the surface, a step of forming a resist on a part of the bottom surface of the groove, a step of etching to remove the conductor other than the lower part of the resist, and a step of depositing an insulator. ing.

[0009]

With this structure, the transmission line of the present invention can have a smaller occupied area than the ground conductor of the conventional coplanar line by forming the ground conductor on the side surface of the groove, which facilitates high integration. Further, the side grounding conductor can reduce the electromagnetic field leaking to the outside as compared with the conventional strip line or coplanar line. As a result, it is possible to reduce the coupling between the wirings that occurs when the wirings are close to each other, and it is possible to bring the plurality of wirings closer to each other than in the conventional case. Further, the transmission line manufacturing method of the present invention can be easily manufactured by using the conventionally used semiconductor process as it is.

[0010]

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 is a semiconductor substrate, 12 is a grounding conductor formed on the side surface, 13 is a signal conductor formed on the bottom surface, 14 is an upper insulator, and 15 is a lower insulator.
(A) shows a case where a groove is formed vertically in the semiconductor substrate 21, and the ground conductors 12 are formed on the side surfaces at both ends of the groove.
The signal conductor 13 is formed on the flat portion of the groove. With such a configuration, the side surface can be effectively used, so that the area occupied by the signal line can be made smaller than that of the conventional coplanar line. Further, since the grounding conductor is formed substantially perpendicular to the signal conductor, the amount of electromagnetic field leakage to the outside can be made smaller than in the conventional coplanar line, and the wiring can be made closer than in the conventional case. (B) is a structure when a groove is formed in the reverse mesa on the semiconductor substrate. (C) shows a structure in which an insulator is formed below the signal conductor. By changing the film thickness of the lower insulator, the relative positional relationship with the grounding conductor formed on the side surface can be controlled. Has become.

FIG. 2 shows an embodiment of the method of forming the line of the present invention. In FIG. 2, 21 is a GaAs semi-insulating substrate, 22 is Au deposited on the entire surface, 23 is a resist, and 24 is a resist.
Is a grounding conductor Au formed on the side surface, 25 is a signal conductor Au22, 26 formed on the bottom surface, and is a SiN film. The forming method will be described below in the order of FIGS. 2A, 2B, 2C, 2D, and 2E.

First, a groove of 5 μm is vertically formed on the GaAs semi-insulating substrate 21 by reactive ion etching using a gas such as CF ₄ or SF ₆ (a). Au on the entire surface
Is deposited by 1 μm plating (b). After applying the resist, the resist 23 is left on the bottom surface of the groove by photolithography (c). GaAs semi-insulating substrate 2 by reactive ion etching using a gas such as CF ₄ or SF ₆
Etching is performed in the direction perpendicular to 1 to remove Au in the flat portion. At this time, the Au 24 on the side surface is not etched because the Au on the upper surface serves as a mask. A on the side when the resist is removed
u24 and Au25 in the flat portion remain (d). Next, a SiN film 26 is deposited on the entire surface by plasma chemical vapor deposition using SiH ₃ and NH ₃ to a thickness of 1 μm (e). In this way, the structure of the present invention is formed.

In the present invention, since the semiconductor manufacturing apparatus which has been conventionally used is used as it is for each step, the manufacturing can be easily carried out. The groove can be easily formed by wet etching using tartaric acid: hydrogen peroxide to form forward mesas and reverse mesas in the same process as above.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

In FIG. 3, 21 is a GaAs semi-insulating substrate, 22 is Au deposited on the entire surface, 24 is a grounding conductor Au formed on the side surface, 31 is a lower SiN film, and 32 is an upper S.
The iN film, 25 is a signal conductor Au formed on the lower SiN film 32, and 23 is a resist for forming a signal conductor. 3 (a), (b), (c), (d),
The forming method will be described in the order of (e) and (f).

First, a groove of 5 μm is vertically formed on the GaAs semi-insulating substrate 21 by reactive ion etching using a gas such as CF ₄ or SF ₆ (a). A on the whole surface
u22 is deposited by 1 μm plating (b). C
Etching is performed in the vertical direction on the GaAs semi-insulating substrate 21 by reactive ion etching using a gas such as F ₄ or SF ₆ to remove Au in the flat portion. At this time, Au2 on the side
In No. 4, Au on the upper surface is used as a mask and is not etched, and a ground conductor on the side surface is formed (c). SiH ₃ , NH _{3 on the} entire surface
SiN by plasma chemical vapor deposition using
nm to form a lower SiN film 31. Further, Au25 is deposited on the entire surface by 1 μm plating. After applying the resist, the resist 23 is left on the bottom surface of the groove by photolithography (d). Au other than under the resist 23
Are removed by etching to remove the resist (e). Finally, an upper SiN film is deposited to a thickness of 1 μm by plasma chemical vapor deposition using SiH ₃ and NH ₃ (f). In this way, the structure of the present invention is formed.

By forming the lower SiN film 31 between the signal conductor Au 25 and the GaAs semi-insulating substrate 21, the positional relationship between Au of the signal conductor 25 and Au of the grounding conductor 24 is determined. It can be arbitrarily set by changing the deposited film thickness of 31.

[0019]

As described above, according to the present invention, by forming the grounding conductor on the side surface of the groove formed on the semiconductor, the high frequency transmission line occupying a much smaller area than the conventional line such as the coplanar type. I will provide a.

Further, the present invention provides a method for forming the line of the present invention by utilizing a conventionally used semiconductor manufacturing method.

[Brief description of drawings]

FIG. 1 is a sectional view of a transmission line according to an embodiment of the present invention.

FIG. 2 is a process sectional view showing a method of manufacturing a transmission line according to an embodiment of the present invention.

FIG. 3 is a process sectional view showing a method of manufacturing a transmission line according to an embodiment of the present invention.

FIG. 4 is a sectional view of a conventional microstrip line.

FIG. 5 is a sectional view of a conventional coplanar line.

[Explanation of symbols]

 11 semiconductor substrate 12 grounding conductor 13 signal conductor 14 upper insulator 15 lower insulator 21 GaAs semi-insulating substrate 22 Au 23 deposited on the entire surface resist 24 grounding conductor Au 25 formed on the side surface Au 26 of signal conductor 26 SiN film 31 Lower SiN film 32 Upper SiN film 41 High dielectric constant insulator 42 Strip conductor 43 Ground conductor 51 Slit conductor

Claims (5)

[Claims] 1. A semiconductor substrate, a groove formed on the semiconductor substrate, a conductor formed on a side surface of the groove, and a conductor formed on a bottom surface of the groove, and formed on a side surface of the groove. An electric transmission line for transmitting an electric signal by the formed conductor and the conductor formed on the bottom surface. 2. The electric transmission line according to claim 1, further comprising an insulating layer below the conductor on the bottom surface. 3. The electric transmission line according to claim 1, further comprising an insulating layer above the conductor on the bottom surface. 4. A step of forming a groove in a semiconductor substrate, a step of depositing a conductor on the surface of the groove, a step of forming a resist on a part of the bottom surface of the groove where the conductor is deposited, and A method of manufacturing an electric transmission line, comprising: a step of etching in a vertical direction to remove conductors other than the lower part of the resist and side surfaces of the groove; and a step of removing the resist. 5. A step of forming a groove in a semiconductor substrate, a step of depositing a conductor on the surface of the groove, a step of etching in the direction perpendicular to the substrate to remove a conductor other than a side surface of the groove, and an insulating step. A step of depositing a body, a step of depositing a conductor on the surface, a step of forming a resist on a part of the bottom surface of the groove,
A method of manufacturing an electric transmission line, comprising a step of etching to remove a conductor other than the lower portion of the resist.