JPH0684998A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0684998A
JPH0684998A JP4233734A JP23373492A JPH0684998A JP H0684998 A JPH0684998 A JP H0684998A JP 4233734 A JP4233734 A JP 4233734A JP 23373492 A JP23373492 A JP 23373492A JP H0684998 A JPH0684998 A JP H0684998A
Authority
JP
Japan
Prior art keywords
electrodes
semiconductor chip
leads
electrode
inner leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4233734A
Other languages
Japanese (ja)
Inventor
Nobuaki Oya
宣昭 大家
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4233734A priority Critical patent/JPH0684998A/en
Publication of JPH0684998A publication Critical patent/JPH0684998A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor device which easily realizes connection between electrodes and inner leads even when the number of electrodes on the semiconductor chip increases. CONSTITUTION:External electrodes 11 and internal electrodes 12 are formed in zig-zag on the circumferencial region of a semiconductor chip 10. On a film carrier 18 having an aperture in the region where a semiconductor chip 10 is arranged, there are formed an inner lead 14 with its internal end protruding into the aperture and an inner lead 15 with its internal end kept out of the aperture. The internal end of the inner lead 14 is connected to the electrode 11 through a bump 13, and the internal end of the inner lead 15 is connected to the electrode 12 through a metal fine lead 16.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】半導体チップ上の電極とインナー
リードとの接続方法に係り、特に電極が半導体チップ上
の周縁部に２列に配列されているものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting an electrode on a semiconductor chip and an inner lead, and more particularly to a method in which electrodes are arranged in two rows at a peripheral portion of a semiconductor chip.

【０００２】[0002]

【従来の技術】半導体チップ上に形成される電極の数
は、半導体チップに形成される集積回路が多機能化する
に伴い増加する傾向にある。この結果、半導体チップ上
の電極の間隔は狭まっている。このため、電極とインナ
ーリードの接続にはワイヤボンディングよりも電極間隔
が狭いものに対応できるＴＡＢ（Tape Automated Bondi
ng）技術が用いられている。2. Description of the Related Art The number of electrodes formed on a semiconductor chip tends to increase as the integrated circuit formed on the semiconductor chip becomes multifunctional. As a result, the distance between the electrodes on the semiconductor chip is narrowed. For this reason, the TAB (Tape Automated Bondi) can be used to connect the electrode and the inner lead when the electrode interval is narrower than the wire bonding.
ng) technology is used.

【０００３】図２はＴＡＢ技術により半導体チップ上に
形成された電極とインナーリードとの接続部を示す平面
図である。図において、20は半導体チップであり、21，
21，…は半導体チップ上に形成された電極、22，22，…
はバンプ、23，23，…はインナーリード、24，24，…は
アウターリード、25はフィルムキャリヤである。FIG. 2 is a plan view showing a connecting portion between an electrode and an inner lead formed on a semiconductor chip by the TAB technique. In the figure, 20 is a semiconductor chip, 21,
21, ... Electrodes formed on the semiconductor chip, 22, 22, ...
Are bumps, 23, 23, ... are inner leads, 24, 24, ... are outer leads, and 25 is a film carrier.

【０００４】上記インナーリード23，23，…の内側端部
はフィルムキャリヤ25上に写真蝕刻技術により形成さ
れ、バンプ22，22，…を介して電極21，21，…に接続さ
れる。インナーリード23，23，…の外側端部はアウター
リード24，24，…に熱圧着される。この場合、インナー
リード23，23，…はＡｕメッキ処理が施されており、ア
ウターリード24，24，…はＳｎメッキ処理が施されてい
るので、インナーリード23，23，…とアウターリード2
4，24，…とはＡｕ・Ｓｎ共晶合金により接続される。
そして、上記半導体チップ20の封止は図示していない
が、上型および下型からなる一対の樹脂封止用金型にア
ウターリード24，24，…を残して挟み込み、金型の空洞
部に硬化前の樹脂を圧入することにより行われる。The inner ends of the inner leads 23, 23, ... Are formed on the film carrier 25 by a photo-etching technique and are connected to the electrodes 21, 21 ,. The outer ends of the inner leads 23, 23, ... Are thermocompression bonded to the outer leads 24, 24 ,. In this case, since the inner leads 23, 23, ... Are plated with Au, and the outer leads 24, 24, ... Are plated with Sn, the inner leads 23, 23 ,.
4, 24, ... Are connected by an Au.Sn eutectic alloy.
Although not shown, the semiconductor chip 20 is sealed by sandwiching the outer leads 24, 24, ... In a pair of resin-sealing molds, which are an upper mold and a lower mold, to leave a cavity in the mold. It is performed by press-fitting the resin before curing.

【０００５】[0005]

【発明が解決しようとする課題】従来の半導体チップ上
の電極ピッチは約１５０μｍであり、電極の幅が約１０
０μｍであることから、電極の間隔は約５０μｍとなっ
ている。したがって、今後さらに電極を増やす場合に
は、電極を２列に配列しなければならない。しかし、イ
ンナーリードと電極との接続をＴＡＢ技術により行う場
合、フィルムキャリヤ上に２列分のインナーリードを引
き回すことは困難である。また、電極を２列化すること
により、インナーリードのピッチを狭める必要がある。
このために、ワイヤボンディングによる接続を行った場
合には、ワイヤ同士の接触による不良が発生する。The electrode pitch on the conventional semiconductor chip is about 150 μm, and the width of the electrode is about 10 μm.
Since it is 0 μm, the interval between the electrodes is about 50 μm. Therefore, if the number of electrodes is increased in the future, the electrodes must be arranged in two rows. However, when the inner leads and the electrodes are connected by the TAB technique, it is difficult to lay out two rows of the inner leads on the film carrier. Further, it is necessary to narrow the pitch of the inner leads by arranging the electrodes in two rows.
Therefore, when the connection is performed by wire bonding, a defect occurs due to the contact between the wires.

【０００６】この発明は上記のような事情を考慮してな
されたものであり、その目的は半導体チップ上の電極が
増加しても、電極とインナーリードとの接続が容易に行
える半導体装置を提供することである。The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor device in which the electrode and the inner lead can be easily connected even if the number of electrodes on the semiconductor chip is increased. It is to be.

【０００７】[0007]

【課題を解決するための手段】この発明による半導体装
置は半導体チップと、半導体チップ上の周縁付近に２列
に設けられた電極と、上記一方の列の電極に直接接続さ
れたインナーリードと、上記他方の列の電極とインナー
リードとを接続する金属細線とを具備することを特徴と
する。A semiconductor device according to the present invention comprises a semiconductor chip, electrodes provided in two rows near the periphery of the semiconductor chip, and inner leads directly connected to the electrodes in one row. It is characterized in that it is provided with a thin metal wire connecting the electrode of the other row and the inner lead.

【０００８】[0008]

【作用】上記手段においては、他方の列の電極とインナ
ーリードとを接続する金属細線は一方の列の電極に直接
接続されるインナーリードの上に隙間を持って配線され
るのため、内側電極と外側電極との短絡不良の発生を防
ぐように作用する。In the above means, since the thin metal wires connecting the electrodes in the other row and the inner leads are wired with a gap above the inner leads directly connected to the electrodes in the one row, the inner electrode And acts to prevent the occurrence of a short circuit between the outer electrode and the outer electrode.

【０００９】[0009]

【実施例】以下、この発明を図面を参照して実施例によ
り説明する。図１はこの発明の一実施例に係る半導体チ
ップ上に形成された電極とインナーリードとの接続部を
示す平面図である。図において、10は半導体チップであ
り、11，11，…は半導体チップ上の周縁部に形成された
電極であり、電極の幅は約１００μｍ、電極のピッチは
約１５０μｍである。また、12，12，…は電極11，11，
…の内側に11，11，…と千鳥状に配列されるように形成
された電極であり、電極の幅とピッチは電極11，11，…
と同じである。また、13，13，…はバンプ、14，14，…
は幅約５０μｍのインナーリード、15，15，…は幅約１
００μｍのインナーリード、16，16，…は金属細線、1
7，17，…はアウターリード、18はフィルムキャリヤで
ある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a plan view showing a connecting portion between an electrode and an inner lead formed on a semiconductor chip according to an embodiment of the present invention. In the figure, 10 is a semiconductor chip, 11, 11, ... Are electrodes formed on the peripheral edge of the semiconductor chip, the width of the electrodes is about 100 μm, and the pitch of the electrodes is about 150 μm. Also, 12, 12, ... Are electrodes 11, 11,
The electrodes are formed so as to be arranged in a zigzag pattern on the inside of the electrodes 11, 11, ..., The width and pitch of the electrodes are the electrodes 11, 11 ,.
Is the same as. Also, 13, 13, ... Are bumps, 14, 14 ,.
Is an inner lead with a width of about 50 μm, 15, 15, ...
00μm inner leads, 16, 16, ... are fine metal wires, 1
7, 17, ... Are outer leads, and 18 is a film carrier.

【００１０】図１の状態にするための製造工程を説明す
る。まず、半導体チップ10上にＡｌで電極11，11，…お
よび12，12，…を形成する。そして、インナーリードと
アウターリードとの接続部になる領域と半導体チップ10
が配置される領域が開孔されたポリミド等により形成さ
れたフィルムキャリヤ18上に接着剤により銅箔を貼り付
ける。そして、フィルムキャリヤ18の裏面と上記銅箔上
にフォトレジストを塗布し、写真蝕刻技術によりインナ
ーリード14，14，…および15，15，…を形成する。そし
て、インナーリード14，14，…および15，15，…にはＳ
ｎメッキ処理が施される。A manufacturing process for achieving the state of FIG. 1 will be described. First, electrodes 11, 11, ... And 12, 12, ... Are formed of Al on the semiconductor chip 10. Then, the semiconductor chip 10 and the area that becomes the connection portion between the inner lead and the outer lead
A copper foil is attached by an adhesive onto a film carrier 18 formed of a polyimide or the like in which a region where is disposed is opened. Then, a photoresist is applied on the back surface of the film carrier 18 and the copper foil, and the inner leads 14, 14, ... And 15, 15 ,. The inner leads 14, 14, ... And 15, 15 ,.
n-plating is performed.

【００１１】続いて、インナーリード14，14，…の内側
端部の下側にＡｕで形成されたバンプ13，13，…を熱圧
着により接合する。このバンプ13，13，…が電極11，1
1，…上になるようにフィルムキャリヤ18の位置合わせ
をし、熱を加えながらインナーリード14，14，…の内側
端部の上側から圧力を加える。この結果、電極11，11，
…とバンプ13，13，…とはＡｕ・Ａｌ合金により、バン
プ13，13，…とインナーリード14，14，…とはＡｕ・Ｓ
ｎ共晶合金により接合される。Next, the bumps 13, 13, ... Made of Au are bonded to the lower side of the inner end portions of the inner leads 14, 14 ,. The bumps 13, 13, ... Are electrodes 11, 1
The film carrier 18 is positioned so that it is on the upper side, and pressure is applied from above the inner end portions of the inner leads 14, 14, while applying heat. As a result, the electrodes 11, 11,
, And the bumps 13, 13, ... are made of Au / Al alloy, and the bumps 13, 13, ... and the inner leads 14, 14, ... are made of Au / S.
It is joined by an n-eutectic alloy.

【００１２】続いて、電極12，12，…とインナーリード
15，15，…とを金属細線16，16，…により接続する。こ
の場合、径が３０μｍ程度の金属細線16，16，…を使用
するが、両端の接続部はキャピラリにより押し潰される
ために径はかなり広がる。このため、インナーリード1
5，15，…の幅は電極12，12，…と同じ１００μｍとイ
ンナーリード14，14，…の径よりも広くしてある。Next, the electrodes 12, 12, ... And the inner leads
15 and 15 are connected by thin metal wires 16, 16. In this case, the fine metal wires 16, 16, ... Having a diameter of about 30 μm are used, but the diameter is considerably widened because the connecting portions at both ends are crushed by the capillaries. Therefore, the inner lead 1
The width of 5, 15, ... Is 100 .mu.m, which is the same as that of the electrodes 12, 12, ..., and is wider than the diameter of the inner leads 14, 14 ,.

【００１３】続いて、Ｎｉ・Ｆｅ合金により形成された
アウターリード17，17，…の内側端部の上にインナーリ
ード14，14，…および15，15，…の外側端部が来るよう
にフィルムキャリヤ18を位置させる。そして、このアウ
ターリードの内側端部とインナーリードの外側端部とを
熱圧着させる。このアウターリードはＡｕメッキ処理が
施され、インナーリードにはＳｎメッキ処理が施されて
いるので、アウターリードとインナーリードとはＡｕ・
Ｓｎ共晶合金で接続される。Next, the film is formed so that the outer ends of the inner leads 14, 14, ... and 15, 15, ... Are placed on the inner ends of the outer leads 17, 17 ,. Position the carrier 18. Then, the inner end portion of the outer lead and the outer end portion of the inner lead are thermocompression bonded. Since the outer lead is plated with Au and the inner lead is plated with Sn, the outer lead and the inner lead are Au.
Connected by Sn eutectic alloy.

【００１４】そして、図１に示す状態からアウターリー
ド17，17，…だけを残して樹脂により封止し、アウター
リード17，17，…と図示していないリードフレームとを
切り離すことによりＱＦＰ等の半導体装置が完成する。From the state shown in FIG. 1, only the outer leads 17, 17, ... Are left and sealed with a resin, and the outer leads 17, 17 ,. The semiconductor device is completed.

【００１５】上記実施例半導体装置においては電極周縁
部の２列の電極11，11，…および12，12，…はそれぞれ
従来と同じ電極ピッチで配列されており、従来よりも多
くの電極が半導体チップ10上に形成されている。そし
て、内側に配線された電極12，12，…とインナーリード
15，15，…との接続は金属細線16，16，…によるワイヤ
ボンディングであり、外側に配列された電極11，11，…
とインナーリード14，14，…との接続はインナーリード
14，14，…を電極11，11，…上にまで引き回しバンプ1
3，13，…によるＴＡＢである。したがって、金属細線1
6，16，…相互間のピッチおよびＴＡＢ用のインナーリ
ード14，14，…相互間のピッチは従来と同様であり、金
属細線16，16，…はインナーリード14，14，…の上に隙
間を持って配線されるので容易に２列化した電極11，1
1，…および12，12，…とインナーリード14，14，…お
よび15，15，…を容易に接続することが可能となった。In the semiconductor device of the above-described embodiment, the two rows of electrodes 11, 11, ... And 12, 12, ... At the periphery of the electrodes are arranged at the same electrode pitch as the conventional one, and more electrodes than the conventional one are semiconductors. It is formed on the chip 10. Then, the electrodes 12, 12, ... Wired inside and the inner leads
The connection with 15, 15, ... Is by wire bonding with thin metal wires 16, 16 ,, and the electrodes 11, 11 ,.
Is connected to the inner leads 14, 14, ...
14 and 14, ... are drawn up to the electrodes 11, 11, ...
It is TAB by 3, 13, .... Therefore, the thin metal wire 1
The pitch between 6, 16 ..., and the inner leads 14, 14 for TAB, and the pitch between them are the same as before, and the thin metal wires 16, 16, ... Are spaced above the inner leads 14, 14 ,. The electrodes 11 and 1 are easily arranged in two rows because they are wired together
It became possible to easily connect 1, ... and 12,12, ... and the inner leads 14,14, ... and 15,15, ....

【００１６】なお、上記実施例においてはインナーリー
ド14，14，…および15，15，…にＳｎメッキ処理を、ア
ウターリード17，17，…にＡｕメッキ処理を施している
が、メッキ処理を逆にしてもよい。この場合、バンプ1
3，13，…とインナーリード14，14，…とはＡｕ・Ａｕ
熱圧着により接合され、インナーリード14，14，…およ
び15，15，…とアウターリード17，17，…とはＡｕ・Ｓ
ｎ共晶合金により接続される。In the above embodiment, the inner leads 14, 14, ... And 15, 15, ... Are Sn-plated and the outer leads 17, 17, ... Are Au-plated. You may In this case, bump 1
3, 13, ... and the inner leads 14, 14, ... are Au and Au.
The inner leads 14, 14, ... And 15, 15, ... And the outer leads 17, 17 ,.
Connected by n eutectic alloy.

【００１７】[0017]

【発明の効果】以上説明したようにこの発明によれば半
導体チップ上の電極が増加しても、電極とインナーリー
ドとの接続が容易に行える半導体装置を提供できる。As described above, according to the present invention, it is possible to provide a semiconductor device in which the electrodes can be easily connected to the inner leads even if the number of electrodes on the semiconductor chip is increased.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明の一実施例に係る半導体チップ上に形
成された電極とインナーリードとの接続部を示す平面
図。FIG. 1 is a plan view showing a connecting portion between an electrode and an inner lead formed on a semiconductor chip according to an embodiment of the present invention.

【図２】ＴＡＢ技術により半導体チップ上に形成された
電極とインナーリードとの接続部を示す平面図。FIG. 2 is a plan view showing a connection portion between an electrode and an inner lead formed on a semiconductor chip by a TAB technique.

【符号の説明】[Explanation of symbols]

10…半導体チップ、11，12…電極、13…バンプ、14，15
…インナーリード、16…金属細線、17…アウターリー
ド、18…フィルムキャリヤ。10 ... Semiconductor chip, 11, 12 ... Electrode, 13 ... Bump, 14, 15
… Inner leads, 16… metal wires, 17… outer leads, 18… film carriers.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップと、 半導体チップ上の周縁付近に２列に設けられた電極と、 上記一方の列の電極に直接接続されたインナーリード
と、 上記他方の列の電極とインナーリードとを接続する金属
細線とを具備することを特徴とする半導体装置。1. A semiconductor chip, electrodes provided in two rows near the periphery of the semiconductor chip, inner leads directly connected to the electrodes of the one row, and electrodes and inner leads of the other row. And a thin metal wire for connecting the semiconductor devices. 【請求項２】 上記内側と外側の電極が千鳥状に配列さ
れていることを特徴とする請求項１に記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the inner and outer electrodes are arranged in a staggered pattern.
JP4233734A 1992-09-01 1992-09-01 Semiconductor device Pending JPH0684998A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4233734A JPH0684998A (en) 1992-09-01 1992-09-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4233734A JPH0684998A (en) 1992-09-01 1992-09-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0684998A true JPH0684998A (en) 1994-03-25

Family

ID=16959740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4233734A Pending JPH0684998A (en) 1992-09-01 1992-09-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0684998A (en)

Similar Documents

Publication Publication Date Title
JP4917112B2 (en) Semiconductor device
US7397113B2 (en) Semiconductor device
US5530282A (en) Semiconductor device having a multilayer interconnection structure
JPH0794553A (en) Semiconductor device and fabrication thereof
JPH04233244A (en) Integrated-circuit assembly
JPH0722454A (en) Semiconductor integrated circuit device
US6353259B1 (en) Process for producing BGA type semiconductor device, TAB tape for BGA type semiconductor device, and BGA type semiconductor device
JP2569400B2 (en) Method for manufacturing resin-encapsulated semiconductor device
US6258622B1 (en) Flip clip bonding leadframe-type packaging method for integrated circuit device and a device formed by the packaging method
JPH0684998A (en) Semiconductor device
JPH0357248A (en) Resin-sealed semiconductor device according to tape carrier system
JP2697743B2 (en) Resin-sealed semiconductor device
JP4764608B2 (en) Semiconductor device
JPH0525236Y2 (en)
JPH01231333A (en) Manufacture of semiconductor device
JPH05283473A (en) Film carrier semiconductor device and manufacture thereof
JPS63160262A (en) Lead frame and semiconductor device using the same
JP2536439B2 (en) Lead frame for semiconductor device and resin-sealed semiconductor device using the same
JPH04278548A (en) Resin sealed semiconductor device
JPS63114241A (en) Semiconductor device
JPH0936295A (en) Lead frame, manufacture thereof, resin-sealed semiconductor device and manufacture thereof
JPH02185060A (en) Lead frame for semiconductor device
JPH02298044A (en) Manufacture of lead frame
JPH10270601A (en) Semiconductor device
KR20010001689A (en) A flip chip bonding leadframe-type packaging method for integrated circuit device and a device formed by the packaging method