JPH0684992A - Mounting of semiconductor chip - Google Patents

Mounting of semiconductor chip

Info

Publication number
JPH0684992A
JPH0684992A JP4257367A JP25736792A JPH0684992A JP H0684992 A JPH0684992 A JP H0684992A JP 4257367 A JP4257367 A JP 4257367A JP 25736792 A JP25736792 A JP 25736792A JP H0684992 A JPH0684992 A JP H0684992A
Authority
JP
Japan
Prior art keywords
wire bonding
semiconductor chip
pads
substrate
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4257367A
Other languages
Japanese (ja)
Inventor
Yasushi Matsumura
靖 松村
Shinji Asakura
信次 朝倉
Masahito Aritome
雅人 有留
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4257367A priority Critical patent/JPH0684992A/en
Publication of JPH0684992A publication Critical patent/JPH0684992A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body

Abstract

PURPOSE:To easily realize high density packing of an electronic apparatus utilizing a semiconductor chip. CONSTITUTION:The wire bonding pads are arranged in three lines along the side edge 4a of a semiconductor chip 4 through repetition of the arrangement that the first and third pads are provided in the first line, the second pad in the second line and the fourth pad in the third line, with the continuous four wire bonding pads 2a, 2b, 2c on a substrate 1 formed as a pair. Thereby, the minimum interval between the adjacent circuits can be made wider to lower the generation rate of short-circuit of wiring in the wire bonding process and to reduce the man-hours and improve the yield. Moreover, such arrangement can respond to further high density packing and higher precision of electronic apparatus utilizing a semiconductor chip.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、基板上に搭載された
半導体チップの実装方法、特にその際の基板上のワイヤ
ボンディングパッドの配列構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a semiconductor chip mounted on a substrate, and more particularly to an arrangement structure of wire bonding pads on the substrate at that time.

【０００２】[0002]

【従来の技術】ＩＣ等の半導体チップを基板に形成され
た配線パターンに接続する方法としては、半導体チップ
側と基板側の互いに対応するワイヤボンディングパッド
間をワイヤボンディングによって接続する方法が一般的
である。しかしながら、近年電子機器の高密度化と高精
細化の進展により配線パターンのピッチが狭くなり、ボ
ンディング工程での配線短絡の発生率が高くなりつつあ
る。この対策として、基板側のワイヤボンディングパッ
ドを２列の千鳥配列にすることが提案されている(例え
ば、実開平３−４８２３０号公報参照)。図２はこれの
説明図であり、(a)は改善前の１列配列の場合、(b)(c)
は改善後の２列配列の場合をそれぞれ示している。１１
はワイヤボンディングパッド、１２は配線パターンのパ
ス部であり、基本ピッチＰ1が同一の場合の隣接回路間
の最小間隔は、(a)ではパッド１１，１１間の間隔Ｐ2と
なるのに対して、(b)ではパッド１１とパス部１２間の
間隔Ｐ3となり、Ｐ3＞Ｐ2であって間隔が広くなる。従
って、破線で示したようなボンディング位置１３のずれ
による短絡は(a)よりも(b)の方が生じにくくなり、配線
短絡の発生率を低下させることができる。2. Description of the Related Art As a method for connecting a semiconductor chip such as an IC to a wiring pattern formed on a substrate, a method is generally used in which wire bonding pads between corresponding semiconductor chip side and substrate side wire bonding pads are connected. is there. However, in recent years, with the progress of higher density and higher definition of electronic devices, the pitch of wiring patterns has become narrower, and the occurrence rate of wiring short circuits in the bonding process has been increasing. As a countermeasure against this, it has been proposed that the wire bonding pads on the substrate side are arranged in two rows in a staggered arrangement (for example, see Japanese Utility Model Laid-Open No. 48230/1993). Figure 2 is an explanatory diagram of this, (a) is the case of the one-row array before improvement, (b) (c)
Indicates the case of the two-row arrangement after improvement. 11
Is a wire bonding pad, 12 is a path portion of the wiring pattern, and the minimum distance between adjacent circuits when the basic pitch P 1 is the same is the distance P 2 between the pads 11 and 11 in (a). Thus, in (b), the space P 3 between the pad 11 and the pass portion 12 becomes P 3 , and the space becomes wide because P 3 > P 2 . Therefore, the short circuit due to the displacement of the bonding position 13 as shown by the broken line is less likely to occur in (b) than in (a), and the occurrence rate of wiring short circuit can be reduced.

【０００３】[0003]

【発明が解決しようとする課題】しかし、このようなパ
ッド配列であっても、更に高密度化が進んで配線間ピッ
チが小さくなるとやはり配線短絡の発生頻度が高くな
り、高密度化を妨げる要因となる。すなわち、図２の
(c)は基本ピッチＰ1を後述の実施例と同一にした場合を
示しており、この場合は隣接回路間の最小間隔Ｐ3はＰ3
＜Ｐ2となり、ボンディング位置１３のずれによる短絡
が発生しやすくなるのである。この発明はこの点に着目
し、高密度化を容易にすることを課題としてなされたも
のである。However, even with such a pad arrangement, if the density is further increased and the pitch between the wirings is reduced, the frequency of occurrence of wiring short-circuiting is also increased, which is a factor that prevents the density from being increased. Becomes That is, in FIG.
(c) shows the case where the basic pitch P 1 is the same as that of the embodiment described later, and in this case, the minimum interval P 3 between adjacent circuits is P 3
<P 2 , and a short circuit due to the displacement of the bonding position 13 is likely to occur. The present invention has been made in view of this point, and has been made as a subject to facilitate high density.

【０００４】[0004]

【課題を解決するための手段】上述の課題を解決するた
めに、この発明では、基板上の連続した４個のワイヤボ
ンディングパッドを一組みとして、第１番目と第３番目
は１列目に、第２番目は２列目に、第４番目は３列目に
位置するという順序の繰り返しで半導体チップの周辺に
沿って３列に配列し、対応するチップのワイヤボンディ
ングパッドと基板上のワイヤボンディングパッドとの間
をワイヤボンディングによって接続するようにしてい
る。In order to solve the above-mentioned problems, in the present invention, a continuous four wire bonding pads on a substrate are set as a set, and the first and third wires are in the first column. , The second is located in the second row, and the fourth is located in the third row. The semiconductor chips are arranged in three rows along the periphery of the semiconductor chip, and the wire bonding pads of the corresponding chips and the wires on the substrate are arranged. The bonding pads are connected by wire bonding.

【０００５】[0005]

【作用】上記の方法によれば、基板上のワイヤボンディ
ングパッドの２列目と３列目には４つ目ごとのパッドが
それぞれ配列され、隣接するパッド間には２列目におい
てはパス部が２本、３列目においては３本存在すること
になる。そしてパス部の幅はパッドよりも狭いので、図
２の(b)あるいは(c)のように千鳥配列された２列目のパ
ッドの間にパス部が１本ずつ存在する場合よりも、隣接
回路間の最小間隔は基本ピッチが同一であれば広くな
り、また最小間隔が同一でよければ、基本ピッチを更に
小さくすることが可能となる。According to the above method, every fourth pad is arranged in the second and third rows of the wire bonding pads on the substrate, and the pass portion is formed between the adjacent pads in the second row. There are two lines and three lines in the third column. Since the width of the pass portion is narrower than that of the pad, the pass portion is adjacent to each other as compared to the case where one pass portion exists between the pads in the second row in the staggered arrangement as shown in FIG. 2B or 2C. If the basic pitch is the same, the minimum interval between the circuits becomes wider, and if the minimum interval is the same, the basic pitch can be made smaller.

【０００６】[0006]

【実施例】次に、この発明の一実施例について説明す
る。図１において、１は基板、２ａ，２ｂ，２ｃは基板
１上に形成されているワイヤボンディングパッド、３
ａ，３ｂ，３ｃはそのパス部、４は基板１上に搭載され
ている半導体チップ、５は半導体チップ４の上面端部に
形成されているチップ側のワイヤボンディングパッド、
６は対応する各パッド間をワイヤボンディングによって
接続しているワイヤである。各パッド２ａ，２ｂ，２ｃ
の幅Ｗ1と各パス部３ａ，３ｂ，３ｃの幅Ｗ2とはＷ1＞
Ｗ2の関係となっている。Next, an embodiment of the present invention will be described. In FIG. 1, 1 is a substrate, 2a, 2b and 2c are wire bonding pads formed on the substrate 1, 3
a, 3b and 3c are path portions thereof, 4 is a semiconductor chip mounted on the substrate 1, 5 is a wire bonding pad on the chip side formed at the upper end of the semiconductor chip 4,
Reference numeral 6 is a wire connecting the corresponding pads by wire bonding. Each pad 2a, 2b, 2c
The width W 1 of each path section 3a, 3b, and the width W 2 of 3c W 1>
It has a relationship of W 2 .

【０００７】基板側のワイヤボンディングパッド２ａ，
２ｂ，２ｃは図のように側縁４ａに沿って変則的な３列
の千鳥に配列されている。すなわち、連続した４個のパ
ッドを一組みとして、その第１番目と第３番目が１列目
に配列されたパッド２ａ、第２番目が２列目に配列され
たパッド２ｂ、第４番目が３列目に配列されたパッド２
ａとなっている。一方、チップ側のパッド５は図のよう
に千鳥状に交互に配列されており、これらの基板側とチ
ップ側の互いに対応する各パッド間がワイヤボンディン
グによるワイヤ６でそれぞれ接続されている。また、パ
ス部３ａ，３ｂ，３ｃは基本ピッチＰ1で形成されてい
るが、パッド２ａ，２ａは等間隔に配置されてそのパス
部３ａは図のように２列目のパッド２ｂから遠い側に偏
って形成されており、更にパス部３ａがパッド２ｃの横
を通過する部分はパッド２ｃから離れる側に湾曲した迂
回部３ａ´となっている。The wire bonding pad 2a on the substrate side,
2b and 2c are arranged in an irregular three-row staggered pattern along the side edge 4a as shown in the figure. That is, as a set of four consecutive pads, the first and third pads 2a arranged in the first row, the second pad 2b arranged in the second row, and the fourth pad Pads 2 arranged in the third row
It is a. On the other hand, the pads 5 on the chip side are alternately arranged in a zigzag pattern as shown in the drawing, and the corresponding pads on the substrate side and the chip side are connected by wires 6 by wire bonding. Further, although the pass portions 3a, 3b, 3c are formed with the basic pitch P 1 , the pads 2a, 2a are arranged at equal intervals, and the pass portions 3a are on the side farther from the pad 2b in the second row as shown in the figure. The portion where the path portion 3a passes along the side of the pad 2c is a detour portion 3a 'which is curved toward the side away from the pad 2c.

【０００８】この実施例は上述のような構成であり、２
列目のパッド２ｂ，２ｂ間には２本のパス部２ａが、ま
た３列目のパッド２ｃ，２ｃ間には２本のパス部２ａと
１本のパス部２ｂがそれぞれ通っている。そして、上述
のような形状と配置で各パッド２ａ，２ｂ，２ｃ及びパ
ス部３ａ，３ｂ，３ｃを形成し、またＷ1＞Ｗ2としてあ
るから、基本ピッチＰ1が図２の(c)と同一であれば、パ
ッド２ｂまたは２ｃとこれに隣接するパス部３ａとの間
隔Ｐ3は図２の(c)における間隔Ｐ3よりも明らかに広く
なり、ボンディング位置のずれによる短絡の発生率を低
下させることができる。また仮にこの間隔Ｐ3を図２の
(c)の間隔Ｐ3と同一とすれば、基本ピッチＰ1を更に小
さくすることができる。This embodiment has the structure as described above, and
Two pass portions 2a pass between the pads 2b and 2b in the row, and two pass portions 2a and one pass portion 2b pass between the pads 2c and 2c in the third row. Then, the pads 2a, 2b, 2c and the pass portions 3a, 3b, 3c are formed in the shape and arrangement as described above, and since W 1 > W 2 , the basic pitch P 1 is shown in FIG. if the same as the spacing P 3 between the pad 2b or 2c and the path portion 3a adjacent thereto becomes clearly wider than the interval P 3 in the (c) 2, the incidence of short-circuiting due to displacement of the bonding position Can be reduced. Further, suppose that this interval P 3 is
If it is the same as the interval P 3 in (c), the basic pitch P 1 can be further reduced.

【０００９】次の表１は、ＣＯＧ方式により半導体チッ
プを搭載した液晶表示装置の配線において、基板側のワ
イヤボンディングパッドを図２の(b)及び(c)のように２
列配置にしたものと、実施例のように３列配置にしたも
のとの短絡発生率を基本ピッチ１２０μｍ及び１００μ
ｍのものについて評価した結果である。この発明によれ
ば従来よりも短絡発生率を低下させ、あるいはパッドの
ピッチを更に小さくできることをこの表は明確に示して
いる。なお、パッド幅Ｗ1は１２０μｍ、パス部幅Ｗ2は
５０μｍ、３列配置における間隔Ｐ3は各ピッチにおい
て６０及び４０μｍである。The following Table 1 shows the wire bonding pads on the substrate side in the wiring of the liquid crystal display device mounted with the semiconductor chip by the COG method as shown in FIGS. 2 (b) and 2 (c).
The short circuit occurrence rates of the one arranged in rows and the one arranged in three rows as in the embodiment are determined by the basic pitches of 120 μm and 100 μm.
It is the result of evaluation for m. This table clearly shows that according to the present invention, the occurrence rate of short circuits can be reduced or the pitch of pads can be made smaller than ever. The pad width W 1 is 120 μm, the pass portion width W 2 is 50 μm, and the interval P 3 in the three-row arrangement is 60 and 40 μm at each pitch.

【００１０】[0010]

【表１】 [Table 1]

【００１１】[0011]

【発明の効果】上述の実施例から明らかなように、この
発明は、基板上の連続した４個のワイヤボンディングパ
ッドを一組みとして、第１番目と第３番目は１列目に、
第２番目は２列目に、第４番目は３列目に位置するとい
う順序の繰り返しで半導体チップの周辺に沿って３列に
配列し、対応する半導体チップのワイヤボンディングパ
ッドと基板上のワイヤボンディングパッドとの間をワイ
ヤボンディングによって接続するようにしたものであ
る。従って、隣接回路間の最小間隔を広くしてワイヤボ
ンディング工程での配線短絡の発生率を低下させ、工数
の低減や歩留りの向上を図ることができ、あるいは隣接
回路間の間隔を更に小さくすることにより半導体チップ
を用いた電子機器の一層の高密度化や高精細化に対応す
ることが容易となる。As is apparent from the above-described embodiments, the present invention is a set of four continuous wire bonding pads on the substrate, and the first and third lines are arranged in the first row.
The second is located in the second row, and the fourth is located in the third row, and the rows are arranged in three rows along the periphery of the semiconductor chip. The wire bonding pads of the corresponding semiconductor chip and the wires on the substrate are arranged. The bonding pad is connected by wire bonding. Therefore, it is possible to increase the minimum distance between adjacent circuits to reduce the occurrence rate of wiring short circuit in the wire bonding process, reduce the man-hours and improve the yield, or further reduce the distance between adjacent circuits. As a result, it becomes easy to cope with higher density and higher definition of electronic equipment using a semiconductor chip.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明の一実施例の要部の平面図である。FIG. 1 is a plan view of a main part of an embodiment of the present invention.

【図２】従来例の要部の平面図である。FIG. 2 is a plan view of a main part of a conventional example.

【符号の説明】[Explanation of symbols]

１ 基板 ２ａ，２ｂ，２ｃ 基板側のワイヤボンディングパッド ３ａ，３ｂ，３ｃ パス部 ４ 半導体チップ ５ チップ側のワイヤボンディングパッド ６ ワイヤ 1 Substrate 2a, 2b, 2c Substrate side wire bonding pad 3a, 3b, 3c Pass part 4 Semiconductor chip 5 Chip side wire bonding pad 6 Wire

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップを基板上に搭載し、半導体
チップの上面端部に形成されているワイヤボンディング
パッドと、半導体チップ周辺の基板上に形成されている
ワイヤボンディングパッドとの間をワイヤボンディング
によって接続する方法であって、基板上の連続した４個
のワイヤボンディングパッドを一組みとして、第１番目
と第３番目は１列目に、第２番目は２列目に、第４番目
は３列目に位置するという順序の繰り返しで半導体チッ
プの周辺に沿って３列に配列し、対応するチップのワイ
ヤボンディングパッドと基板上のワイヤボンディングパ
ッドとの間をワイヤボンディングによって接続すること
を特徴とする半導体チップの実装方法。1. A semiconductor chip is mounted on a substrate, and wire bonding is performed between a wire bonding pad formed on an upper end of the semiconductor chip and a wire bonding pad formed on the substrate around the semiconductor chip. A method of connecting by means of four continuous wire bonding pads on the substrate as a set, the first and the third are in the first row, the second is in the second row, and the fourth is The semiconductor device is arranged in three rows along the periphery of the semiconductor chip by repeating the order of being located in the third row, and the wire bonding pads of the corresponding chip and the wire bonding pads on the substrate are connected by wire bonding. Semiconductor chip mounting method.
JP4257367A 1992-08-31 1992-08-31 Mounting of semiconductor chip Pending JPH0684992A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4257367A JPH0684992A (en) 1992-08-31 1992-08-31 Mounting of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4257367A JPH0684992A (en) 1992-08-31 1992-08-31 Mounting of semiconductor chip

Publications (1)

Publication Number Publication Date
JPH0684992A true JPH0684992A (en) 1994-03-25

Family

ID=17305406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4257367A Pending JPH0684992A (en) 1992-08-31 1992-08-31 Mounting of semiconductor chip

Country Status (1)

Country Link
JP (1) JPH0684992A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
US7042069B2 (en) * 2003-11-28 2006-05-09 Seiko Epson Corporation Semiconductor device and method of manufacturing same, wiring board, electronic module, and electronic instrument
JP2007103423A (en) * 2005-09-30 2007-04-19 Renesas Technology Corp Semiconductor device and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
US7042069B2 (en) * 2003-11-28 2006-05-09 Seiko Epson Corporation Semiconductor device and method of manufacturing same, wiring board, electronic module, and electronic instrument
JP2007103423A (en) * 2005-09-30 2007-04-19 Renesas Technology Corp Semiconductor device and its manufacturing method

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