JPH0684905A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To simplify a forming step of a close adhered layer using so as to enhance the close adhesion between a gold wire and an upper insulation film of a semiconductor device. CONSTITUTION:After a silicon film 15 having a thin film thickness is coated on gold wirings 14a, 14b, alloy films 16a, 16b composed of gold and silicon are formed by applying a plasma CVD method or a heat treatment thereto. In the case of using the plasma CVD method, the silicon film 15 which does not react to gold is oxidized by supplying oxidizing gas to successively form an insulation film 17. Also, in the case of applying the heat treatment thereto, the silicon film 15 which does not react to gold is selectively removed with silicon etching liquid containing hydrofluoric acid and nitric acid. Thus, an insulation film 18 can be formed on gold wirings 14a, 14b without using a photolithography art.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for forming an insulating film on gold wiring.

[0002]

2. Description of the Related Art In recent years, gold is increasingly used as a wiring material for semiconductor integrated circuit devices. This is because the gold wiring has excellent electromigration resistance and stress migration resistance as compared with the conventionally used aluminum wiring, and the wiring resistance can be reduced due to its low resistivity. Further, since the gold wiring can be formed by using a plating technique, there is also an advantage that a highly reliable wiring having good step coverage can be formed as compared with an aluminum wiring formed by a sputtering method. Due to these advantages, the gold wiring technique is the most useful wiring technique in order to cope with the miniaturization of the wiring due to the high integration of the semiconductor integrated circuit device in the future and the increase in the underlying step due to the multilayered wiring.

However, gold has a poor adhesion to a silicon oxide film, a silicon nitride film or the like which is generally used as an insulating film, and when forming an insulating film, an adhesion layer having good adhesiveness to the insulating film on the gold wiring. If not provided, there is a problem that the insulating film peels off.

Here, FIG. 3 shows a method of forming an insulating film on a gold wiring in a conventional method of manufacturing a semiconductor integrated circuit device.

First, as shown in FIG. 3A, the semiconductor substrate 3
1. The gold wiring 34 is formed on the titanium-tungsten films 33a and 33b which are formed by patterning on the silicon oxide film 32 on the substrate 1.
a and 34b are formed.

Next, as a method of forming an insulating film on the gold wirings 34a and 34b, as shown in FIG. 3B, first, a titanium tungsten film 35 is deposited by a sputtering method, and then a photolithography technique is used. Gold wiring 34a, 3
The titanium tungsten film 35 is etched using the photoresists 36a and 36b as a mask, leaving the photoresists 36a and 36b only on the surface 4b.

Next, as shown in FIG. 3C, a pattern 35 of the titanium-tungsten film obtained by the above etching.
After removing the photoresists 36a and 36b on a and 35b, a silicon oxide film 37 is formed by plasma CVD.

[0008]

In this conventional method for manufacturing a semiconductor integrated circuit device, a titanium tungsten film patterned by a photolithography technique is formed as an adhesion layer between a gold wiring and an insulating film on the wiring. By doing so, the adhesiveness between the gold wiring and the insulating film is secured. At present, it has been confirmed that if the adhesion layer is omitted, the insulating film peeling failure occurs. However, in order to form the adhesion layer, the steps of sputtering the titanium-tungsten film, photolithography, and etching are required, which increases the number of steps and the construction period.
There was the problem of increased costs. Even in the case of multi-layer wiring, these steps are required for each wiring layer, and it is clear that this problem will become more serious as the number of wiring layers increases.

[0009]

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, after wiring having gold as a main material is formed on a semiconductor substrate on which a desired semiconductor element is formed, silicon is formed on the entire surface of the semiconductor wafer. Film deposition, plasma CVD
The method further comprises the step of forming an insulating film after forming an alloy layer of gold and silicon on the surface of the wiring by a method or heat treatment.

This silicon film can be formed by a sputtering method, a vapor deposition method or a CVD method.

Further, the above plasma CVD for forming an alloy layer.
The process may include a step of initially flowing an oxidizing gas such as N ₂ O or O ₂ and a step of oxidizing the silicon film that has not reacted with the gold of the wiring.

Alternatively, there may be a step of performing a heat treatment at a temperature of 150 ° C. to 400 ° C., and then removing the silicon film which has not reacted with the gold of the wiring with a fluorinated nitric acid-based silicon etching solution.

[0013]

The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a main part of a semiconductor chip showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.

First, FIG. 1A shows a state in which the gold wirings 14a and 14b are formed. The gold wirings 14a and 14b are formed on the titanium-tungsten films 13a and 13b patterned on the silicon oxide film 12 on the semiconductor substrate 11.

Next, as shown in FIG. 1B, a silicon film 15 is deposited on the entire surface of the semiconductor wafer by a sputtering method so as to have a thickness of 5 to 6 nm (nanometer).

After that, as shown in FIG. 1C, the silicon oxide film 12 is formed by using the plasma CVD method. When the semiconductor wafer is put into the reaction furnace of the plasma CVD and the reaction is started, first of all. An oxidizing gas such as N ₂ O gas is flowed. As the temperature of the semiconductor substrate rises, silicon that is in contact with gold forms an alloy of gold and silicon, and silicon that is not in contact with gold has a very thin film thickness of 5 to 6 nm and is oxidized to form a silicon oxide film 17. . After this, silane and T
A gas such as EOS is passed to form a silicon oxide film 18 by ordinary plasma CVD. Thus gold wiring 14a, 1
Alloy layers 16a, 16b of gold and silicon only on the surface of 4b
Is formed, and this alloy layer functions as an adhesion layer between the gold wirings 14a and 14b and the silicon oxide film 18.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a cross-sectional view of essential parts of a semiconductor chip showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.

As shown in FIG. 2A, the gold wiring 24 is formed on the silicon oxide film 22 on the semiconductor substrate 21 as in FIG. 1A.
a and 24b are underlying titanium tungsten films 23a and 23a
The state in which patterning is formed on b is shown.

Next, as shown in FIG. 2B, a silicon film 25 is formed by a sputtering method, and the silicon film 25 is formed in a nitrogen atmosphere.
When heat-treated at about 00 ° C., silicon in contact with gold forms alloy layers 26a and 26b of gold and silicon. After that, the silicon film that has not become an alloy is etched with a fluorine-nitric acid-based silicon etching solution.

Then, as shown in FIG. 2C, plasma C
A silicon oxide film 28 is formed using VD.

[0023]

As described above, according to the present invention, by depositing a silicon film on the gold wiring of the semiconductor integrated circuit device, only the surface of the gold wiring can be selectively selected in the subsequent plasma CVD process or heat treatment process. An alloy layer of gold and silicon is formed on. This has the effect that the adhesion between the gold wiring and the insulating film can be improved, and the step of forming an adhesion layer, which conventionally requires a photolithography step, can be greatly simplified.

In order to completely oxidize the silicon film deposited on the wiring other than the money wiring in the plasma CVD process, the silicon film must be sufficiently thin, and the film thickness is preferably about 10 nm or less.

[Brief description of drawings]

FIG. 1 is a sectional view showing a main part of a first embodiment of the present invention.

FIG. 2 is a sectional view showing a main part of a second embodiment of the present invention.

FIG. 3 is a sectional view showing a main part of a conventional technique.

[Explanation of symbols]

11, 21, 31 Semiconductor substrate 12, 22, 32, 17, 18, 28, 37 Silicon oxide film 13, 23, 33, 35 Titanium tungsten film 14, 24, 34 Gold wiring 15, 25 Silicon film 16, 26 Gold- Silicon alloy film 36 Photoresist

Claims (4)

[Claims] 1. After forming a wiring containing gold as a main material on a semiconductor substrate on which a desired semiconductor element is formed, a silicon film is deposited on the entire surface of the semiconductor wafer, and the wiring surface is formed by plasma CVD or heat treatment. 1. A method of manufacturing a semiconductor integrated circuit device, comprising: forming an alloy layer of gold and silicon on a substrate, and then forming an insulating film thereon. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the silicon film is formed by using a sputtering method, an evaporation method or a CVD method. 3. The plasma CV forming the alloy layer
In step D, nitric oxide (N ₂ O) or oxygen (O 2
_2. The semiconductor integrated circuit according to claim 1, further comprising a step of initially flowing an oxidizing gas such as ₂ ) and a step of oxidizing a portion of the silicon film that has not reacted with gold of the wiring. Device manufacturing method. 4. The heat treatment for forming the alloy layer is performed 15 times.
2. The method according to claim 1, further comprising a step of performing the etching at a temperature of 0 ° C. to 400 ° C., and then removing a portion of the silicon film that has not reacted with gold of the wiring with a silicon fluoride etching solution. Of manufacturing a semiconductor integrated circuit device of.