JPH0684732A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent wrong discrimination of unacceptable chips from acceptable chips at the time of inspecting chips on a wafer and physical damage of chips at the time of splitting the chips by arranging in advance simulated semiconductor devices at parts where defects are expected. CONSTITUTION:Desired semiconductor devices 2 are arranged on a semiconductor substrate 1 and simulated semiconductor devices 3 are arranged at parts around the devices 2 where defects are expected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a circular material,
The present invention relates to a method for manufacturing a semiconductor manufacturing apparatus that manufactures a rectangular product.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, a semiconductor device (hereinafter referred to as a chip) 2 is formed on an entire surface of a semiconductor substrate (hereinafter referred to as a wafer) 1. Incompletely shaped chips 2a, 2b, 2c, ...
・ There was a problem. Alternatively, as shown in FIG. 3, only the chips 2 having a perfect shape were arranged on the wafer 1, and the chips 2 having an imperfect shape were not formed on the outermost peripheral portion of the wafer 1.

[0003]

However, the conventional semiconductor device arraying method has the following problems. First, FIG.
In the conventional example shown in (1), among imperfectly shaped chips, there are some chips such as imperfect chips 2a which include the majority of elements and have a slightly imperfect shape. There is a risk that it will be a non-defective product in the electrical inspection, and may be overlooked in a visual inspection or the like due to a minute shape defect, and may be erroneously determined as a non-defective product.

In the conventional example shown in FIG. 3, since there is no scribe line for cutting out the chip on the outer peripheral portion, there is a risk that the chip 2 will not be cut well and the chip 2 may be cracked or chipped when the chip is cut out. In addition, since the outer peripheral portion does not consider electrical structures such as grooves and insulation, when the quality of the chip 2 is inspected in a wafer state before cutting the chip, the outermost peripheral chip is exposed to, for example, light irradiation. There is also a possibility that the quality may be electrically erroneously determined due to the influence of the outer periphery such as the flow of the optical carrier into the chip 2 due to the above.

[0005]

In order to solve the above problems, according to the present invention, when arranging chips on a wafer, the semiconductor device 2 is preliminarily formed in a portion having a complete shape, and the other areas are electrically pre-formed. The chips 3 are arranged up to the outermost periphery of the wafer, the circuit 3 being designed so as to be defective and not adversely affecting the surrounding good chips 2.

That is, the simulated chip 3 is arranged on the outermost peripheral portion of the wafer 1.

[0007]

As described above, in the arrayed wafers, the circuit 3 is designed in advance so that the defective chips 3 at the outermost periphery are electrically defective, so that there is no erroneous determination as a non-defective chip 2. Also, since it does not affect the surrounding area,
The electrical misjudgment of the non-defective chip 2 can be prevented, and since the scribe line is arranged on the entire surface, cracking or chipping of the chip can be prevented when the wafer 1 is scribed.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, a desired semiconductor device (chip) 2 is arranged on a wafer 1 on a chip portion having a complete shape. The chip 3 is arranged on the outer periphery of the chip 3 so as to be electrically defective but not adversely affected.

It should be noted that all the chips 2 and 3 are scribed around them. The chip 3 which is defective but does not have an adverse effect is designed to have no opening except for the scribe line in the final protective film process, for example. After completing this protective film process, when the electrical characteristics of the chips 2 and 3 are inspected, only the chip 2 can be inspected, but the entire surface of the chip 3 except the scribe line is covered with the protective film. Therefore, the electrical characteristics will always be defective.

Further, since the scribe lines are provided on all of the chips 2 and 3, even if the wafer 1 is scribed, the chips 2 are not cracked at all.

[0011]

As described above, the present invention has the following effects by arranging an imperfect simulated chip in a portion where a defect is predicted in advance. It is possible to prevent erroneous determination of the defective chip 3 as the non-defective chip 2. It is possible to prevent the non-defective chip 2 from being erroneously determined to be defective. It is possible to prevent physical damage to the chip 2 when the wafer 1 is scribed.

[Brief description of drawings]

FIG. 1 is a layout of a semiconductor device on a semiconductor substrate according to the present invention.

FIG. 2 is a layout example (1) of a semiconductor device on a conventional semiconductor substrate.

FIG. 3 is a layout example (2) of semiconductor devices on a conventional semiconductor substrate.

[Explanation of symbols]

1 Semiconductor Substrate 2 Semiconductor Devices 2a, 2b, 2c Semiconductor Device Having Incomplete Chip Shape 3 Simulated Semiconductor Device

Claims (1)

[Claims] 1. In a method of arranging a large number of semiconductor devices on a semiconductor substrate and processing / manufacturing the semiconductor device, a simulated semiconductor device is arranged in advance in a portion where a defect is expected. Manufacturing method.