JPH0683672A - Alarm signal processing circuit - Google Patents

Abstract

PURPOSE:To provide an alarm signal processing circuit which reduces the input frequency of the alarm signals ALM produced intermittently to a CPU control circuit. CONSTITUTION:The alarm signals are inputted to an AND circuit 1 and a mask signal generating part 2 which outputs a mask signal with input of the alarm signal and discontinues the output of the mask signal with input of a reset signal. The output of the part 2 is also inputted to the circuit 1 and the alarm signal is outputted by the output of the circuit 1. Then the alarm signal is inputted to a timer 3 which starts with the output of the alarm signal used as a start signal and then outputs a reset signal after a prescribed time. Then the output of the timer 3 is inputted to the part 2 as a reset signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU for controlling an alarm signal (hereinafter referred to as ALM) which is generated intermittently by a CPU.
The present invention relates to an alarm signal processing circuit that reduces the number of inputs to a control circuit.

[0002]

2. Description of the Related Art Conventionally, an ALM that occurs intermittently is a CP.
When inputting to the CPU control circuit controlled by U, no special measures are taken and the input is to the CPU of the CPU control circuit.
Is performing ALM processing.

[0003]

However, when an ALM that occurs intermittently is input to the CPU control circuit, CP
U is almost exclusively used for ALM processing, and there is a problem that other controls can hardly be performed.

The present invention is an ALM CPU that occurs intermittently.
An object is to provide an alarm signal processing circuit that reduces the number of inputs to the control circuit.

[0005]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, an alarm signal is input to an AND circuit 1 and a mask signal generator 2 which outputs a mask signal when an alarm signal is input and cuts off a mask signal output when a reset signal is input. The output is also input to the AND circuit 1, an alarm signal is output from the output of the AND circuit 1, and the output is input as a start signal to a timer 3 that outputs a reset signal after a predetermined time has elapsed, and The output of the timer 3 is input to the mask signal generator 2 as a reset signal.

[0006]

According to the present invention, when the ALM is input intermittently, as shown in a, b, c, and d of FIG.
M is input to the AND circuit 1 and the mask signal generation unit 2.

The mask signal generator 2 is activated by the ALM (1) and outputs the L level from the output as shown in FIG. 1b.
Then, the AND circuit 1 outputs the generated ALM as shown in FIG. 1C, the timer 3 is activated by this ALM, and after a predetermined time t, it is input as a reset signal to the mask signal generation unit 2 to generate the mask signal. The output of the generation unit 2 is set to the original H level.

The intermittent ALM shown in FIG. 1a input while the output of the mask signal generator 2 shown in FIG. 1b is L level.
(B) and (c) are not output from the AND circuit 1, and when the output of the mask signal generation unit 2 becomes H level and ALM 2 shown in FIG. 1a is input, the mask signal generation unit 2 is activated again and L as shown in FIG. Output level.

Then, the AND circuit 1 outputs the ALM generated as shown in FIG. 1C, the timer 3 is activated by this ALM, and is input as a reset signal to the mask signal generation unit 2 after a predetermined time t. The output of the mask signal generator 2 is set to the original H level.

That is, by causing the mask signal generation unit 2 to output a mask signal of L level, the CP of intermittent ALM
Since the number of inputs to the U control circuit is reduced, the CPU can perform other control accordingly.

[0011]

2 is a block diagram of an alarm signal processing circuit according to an embodiment of the present invention, and FIG. 3 is a time chart of each part of FIG.

2-1 in FIG. 2 is a flip-flop (hereinafter referred to as F
2) is a shift register, 3-1 is a counter, 4 is an alarm number counter, 5 is a t ₀ time timer,
Reference numeral 6 denotes a ROM, which constitutes the mask signal generation unit 2 and the timer 3 shown in FIG.

In the case of FIG. 2, as the number of ALMs increases, the mask time is t ₁ = 10 ms, t ₂ =
50 ms, t ₃ = 100 ms, so that it is long, for example, when ALM is input three times, it returns to the beginning again and inputs A again.
As the number of LMs increases, the masking time is made longer, and the generated ALM is output from the AND circuit 1 and, for example, t
_{If the} ALM does not input to the AND circuit 1 even after ₀ = 200 ms, the alarm number counter 4 is reset and returned to the beginning, and the mask time is lengthened as the number of input ALM increases.

When the ALM as shown in FIG. 3 (a) is input, it is input to the clock terminals of the AND circuit 1 and FF2-1, the output of FF2-1 is input to the shift register 2-2, and the shift register 2-2. Then, without delaying, the L level shown in FIG. 3B is output to the AND circuit 1 rather than the output of the shift register 2-2.

Then, the AND circuit 1 outputs the generated ALM as shown in FIG. 3C, and inputs it to the load terminal of the counter 3-1, the clock terminal of the alarm number counter 4, and the timer 5.

The alarm number counter 4 counts the number of input alarms, and when the count value reaches 3, it carries out a carry-out, and sends the addresses corresponding to the count values 1, 2, and 3 to the ROM 6.

At the address sent to the ROM 6, a set value which becomes a carry-out when the counter 3-1 counts 10 ms, 50 ms and 100 ms is written as shown in FIG. 3 (d). Counter 3-1
It is designed to be input as the load value of.

Therefore, when the generated ALM is input from the carry-out output of the counter 3-1, 10 ms, 50 ms, 100 ms elapses depending on the input order of 1, 2, 3 and L
A level reset signal is input to the reset terminal of FF2-1.

From the AND circuit 1, as described above, FIG.
When the generated ALM shown in G of (c) is output, the counter 3
Input to the -1 and the carryout output inverted by the knot circuit 7 becomes an L level pulse delayed by 10 ms from the generated ALM output and input to the reset terminal of FF2-1 as shown in FIG. Then, the L level output from the shift register 2-2 is stopped and the H level is output.

Therefore, the second ALM shown in FIG.
Is masked even if is input, and is not output from AND circuit 1. Next, when the output of the shift register 2-2 is at the H level and the third ALM shown in FIG. 3 (a) is input, it is input to the AND circuit 1 and FF2-1, and the output of the shift register 2-2 is shown in FIG. As shown in (b), it becomes L level.

Therefore, rather than the output of the AND circuit 1, FIG.
The generated ALM shown in (c) is output. Then, this generated ALM is input to the load terminal of the counter 3-1, the clock terminal of the alarm number counter 4, and the timer 5.

2 counts from the alarm count counter 4
The address of the ROM 6 corresponding to the above is output, the set value corresponding to the time t ₂ = 50 ms is sent from the ROM 6 to the counter 3-1, and the output obtained by inverting the output Q of the counter 3-1 by the knot circuit is shown in FIG. It becomes an L level pulse as shown in (e) and is input to the reset terminal of FF2-1.

Then, the output of the shift register 2-2 is as shown in FIG.
The H level as shown in (b) is output. In the case of FIG.
As shown in FIG. 3, since the ALM is not input thereafter, the output of the shift register 2-2 is at the H level.

The timer 5 is shown in FIG. 3 (c) by the AND circuit 1.
It is activated each time the generated ALM shown in No.
Since the output of the AND circuit 1 is less than 200 ms between “to” and “h”, it returns to the initial state when the “AL” is input.
When 0 ms has elapsed, a reset signal is sent to the alarm number counter 4 to reset the alarm number counter 4 and generate ALM.
When is input, it counts from 1.

In the case of FIG. 3, when the ALM is intermittently input three times as shown in FIG. 3A, the second ALM is masked, and the number of generated ALMs input to the CPU control circuit is reduced to 2 Will be able to perform other control by the reduced amount.

The alarm number counter 4, timer 5, R
Of course, the operation of the OM 6 may be processed by the CPU using software.

[0027]

As described in detail above, according to the present invention, the number of times of intermittently input ALM to the circuit for controlling the CPU is reduced, so that the CPU can perform other control by the reduced amount. It has the effect of being able to do it.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention,

FIG. 2 is a block diagram of an alarm signal processing circuit according to an embodiment of the present invention,

FIG. 3 is a time chart of each part of FIG.

[Explanation of symbols]

 Reference numeral 1 is an AND circuit, 2 is a mask signal generator, 2-1 is a flip-flop, 2-2 is a shift register, 3 and 5 are timers, 3-1 is a counter, 4 is an alarm number counter, and 6 is a ROM.

Claims (1)

[Claims] 1. An alarm signal is input to an AND circuit (1) and a mask signal generator (2) that outputs a mask signal when an alarm signal is input and cuts off a mask signal output when a reset signal is input, and generates the mask signal. The output of the section (2) is also input to the AND circuit (1), an alarm signal is output from the output of the AND circuit (1), and the output is used as a start signal, and a reset signal is output after a predetermined time has elapsed. An alarm signal processing circuit, characterized in that it is input to an output timer (3), and the output of the timer (3) is input to the mask signal generation unit (2) as a reset signal.