JPH0683457B2 - Digital chroma signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention corrects the demodulation axis of a chrominance signal (hereinafter referred to as a color difference signal) that has been converted into a digital signal to provide a hue and saturation suitable for a color picture tube. The present invention relates to a digital chroma signal processing circuit capable of obtaining a color signal having a degree.

[Outline of Invention]

According to the present invention, in a circuit for changing the hue by shifting the demodulation axes of two color difference signals (RY, BY), for example, both the color difference signals (RY) and (BY) are used. With a digital multiplier that can change the phase between both signals while shifting the phase by a predetermined angle α,
The IC circuit is designed to obtain a color signal having a desired hue and saturation.

[Conventional technology]

A carrier color signal component is separated from a composite color television signal converted into a digital signal to obtain a color difference signal (RY).
A color signal processing circuit is known in which a desired color signal is obtained after extracting the (BY) signal and the (BY) signal.

FIG. 4 shows an example of a circuit for correcting both demodulation axes so that a color signal having a desired hue and saturation can be obtained from the color difference signals (RY) and (BY). Stuff, 2
Reference numerals 0 and 21 denote color difference signals (RY) 'and (BY)' having different hues (where (RY) '= (RY) _s ).
-Cos α- (BY) _s -sin α, (BY) '= (R
-Y) _s · sin α + (BY) _s · cos α] is converted to an analog signal (D / A) converter, 22 is an adder, 23, 24, 25
Is an attenuator, and these are, for example, one-chip analog IC circuits
It is composed of 26.

According to such a circuit, as shown in FIG. 5, the orthogonal color difference signal (BY) 'is divided by the attenuator 23 at a predetermined ratio and added to the adder 22 to add the original signal. It is possible to obtain a demodulation axis that differs from the color difference signal (RY) 'axis of the above by an angle β, and further, if level adjustment is performed by the attenuators 24 and 25, it is well known that any hue and saturation can be obtained. A color signal of degree can be formed.

In this case, the chromaticity can be adjusted by adjusting the attenuation amount of the attenuators 23, 24, 25, etc. to match the color characteristics of the fluorescent film of the color CRT, and in consideration of the user's preference. You can also change it.

[Problems to be solved by the invention]

However, the method of changing the axis and gain of the color difference signal by such a method is an integrated circuit that forms an analog circuit when the hue and saturation are changed according to the model of the television receiver or the request of the destination. It is necessary to change the circuit, which causes cost up.

The present invention has been made to solve such problems, and provides a processing circuit for a digital chroma signal capable of forming a desired hue and saturation by a digital arithmetic circuit.

[Means for solving problems]

In FIG. 1, a color difference signal (R-
Y) and (B-Y) signals have multiplication coefficients of A, B, C, and
After being input to the digital multipliers 1, 2, 3, and 4 set to D, and being added in adders 5 and 6, respectively, D
The / A converters 7 and 8 convert the analog signals whose hue and saturation are corrected.

[Action]

Multiplication coefficients A, B, C, D and _{A = s · cosα, B =} - s (x 1 cosα + x 0 sinα) C = - s · sinα, is set to _{D = s (x 0 cosα-} x 1 sinα) ( However, _s is a color level, x ₀ and x ₁ are coefficients, α is a phase angle, and the color difference signal (R−Y) ″ output from the D / A converter 8 is (R−Y) ″ = _s {( RY) (x ₀ cos α-x ₁ sin α)
− (B−Y) (x ₁ cos α + x ₀ sin α)} (1), and (B−Y) ″ = _s {(B−Y) cos α− (R−Y) sin
α} ... (2) By changing the coefficients x ₀ and x ₁ with respect to the axis, a color difference signal (R-
Y) ″ can be obtained.

〔Example〕

FIG. 2 is a block diagram of the digital chroma signal processing circuit of the present invention, in which 10 is an A / D converter for converting a carrier color signal into a digital signal, for example, four times the color sub-sending frequency _sc . The frequency 4 _sc is converted into a digital signal with the sampling frequency.

11 is a digital band pass filter, 12 is an ACC (Automatic
For example, the color control circuit sets a color level to a predetermined level corresponding to the level of a burst signal (not shown).

Reference numeral 13 denotes a digital multiplier, and the above-mentioned multiplication coefficients A, B, C, D are sent from the microprocessor (CPU) 14 to the digital multiplier 13 in a time division manner, It is working in succession.

15a, 15b, 15c are , 16a and 16b are adders, and 17a and 17b are latch circuits capable of latching the color difference signals (RY) "and (BY)" respectively for a predetermined time.

Further, 18a and 18b are D / A converters for converting digital color difference signals into analog signals, and 19 is a matrix circuit for forming primary color signals from the color difference signals.

The input carrier color signal is input to the A / D converter 10. When converted to a digital signal at a sampling rate of (B-
Y), (RY),-(BY), and-(RY) signals are repeatedly output. This signal is shaped into a predetermined digital chroma signal with a predetermined band width via the band pass filter 11 and the ACC circuit 12, and is input to the digital multiplier 13. Digital multiplier 13
Input to (BY), (RY),-(BY),
-(RY) signal is the multiplication number set by CPU14
A, B, C, D are sequentially calculated in a time division manner (BY)
XA, (RY) xC,-(BY) xB,-(RY) x D
Signal Is output to the successive delay circuits 15a, 15b, 15c in the cycle. Therefore, the input and output signals of the delay circuit 15a When taken out at each time, the outputs of the adders 16a and 16b are (BY) * A + (RY) * C, and-(BY) *, respectively.
Since an addition signal component of B- (RY) × D is obtained, the addition signal is controlled so as to be held in the next latch circuits 17a and 17b. Therefore, from the latch circuit 17a, the corrected color difference signal (R-
Y) "signal from the latch circuit 17b (B-
Y) ″ signal is output.

This color difference signal can be set to a predetermined color phase and saturation by converting the input data α, _s , x ₀ , x ₁ of the CPU 14.

Next, the corrected color difference signals (RY) ", (BY)"
Is converted into an analog signal by the D / A converters 18a and 18b, and then converted into a three primary color signal via the matrix circuit 19.

FIG. 3 shows the order [I] of the color difference signals output from the A / D converter 10, the signal [II] obtained by calculating the color difference signal [I] by the digital multiplier 13, and the adders 16a and 16b.
Is a waveform diagram of the operation output [III] output from Indicates the period.

In this embodiment, since a high-speed multiplier can be realized by one digital multiplier 13, the cost up of the IC circuit can be suppressed.

〔The invention's effect〕

As described above, the digital chroma signal processing circuit of the present invention is configured such that the first and second digital color difference signals sampled at a predetermined cycle and the first digital color difference signal are phase-shifted by a predetermined angle. (Α) and the second data (x ₀ , x ₁ ) for correcting the phase shift difference of the digital color difference signal phase-shifted by the first data are provided in the digital multiplier, Hue, saturation, etc. can be freely adjusted by synthesizing the output signals obtained by multiplying the first and second digital color difference signals by the predetermined synchronization with the coefficient value using the first data and the second data as parameters. Since it is possible to do all the corrections related to color signals with the digital IC circuit of the same configuration, it is possible to reduce the cost of video equipment and by using a microcomputer etc. There is an effect that it is possible to facilitate settling.

[Brief description of drawings]

1 is a basic block diagram of a digital chroma signal processing circuit according to the present invention, FIG. 2 is a block diagram of a digital chroma signal processing circuit showing an embodiment of the present invention, and FIG.
FIG. 4 is a block diagram showing an example of a conventional color signal processing circuit, and FIG. 5 is an explanatory diagram of a phase angle of the color difference signal in the figure. In the figure, 1, 2, 3, 4, 13 are digital multipliers, 14 is a CPU that outputs color correction data, 15a to 15b are delay circuits, and 16a and 16b.
Is an adder, 17a and 17b are latch circuits, and 18a and 18b are D / A converters.

Front Page Continuation (72) Inventor Masayuki Motomiya 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (56) References JP-A-59-207792 (JP, A) JP-A-60-197087 (JP, A) JP 61-20482 (JP, A) JP 60-31389 (JP, A)

Claims (1)

[Claims] 1. A first and a second signal which are sampled at a cycle four times as high as the carrier color signal frequency and converted into digital signals.
Color difference signal, first data (α) for phase-shifting both the first and second color difference signals by a predetermined angle, and the first and second color differences phase-shifted by the first data. The second data (x ₀ , for adjusting the phase difference between the signals,
x ₁ ) is input to the multiplier circuit, and the multiplier circuit outputs four coefficient values having the first data (α) and the second data (x ₀ , x ₁ ) as parameters. A multiplication circuit that sequentially multiplies the first and second color difference signals, and a combination circuit that combines the first and second color difference signal data obtained from the multiplication circuit with each other at a predetermined timing, A digital chroma signal processing circuit characterized in that a color difference signal whose hue demodulation axis and saturation are corrected is obtained from a synthesizing circuit.