JPS60260282A - Chrominance signal processing circuit - Google Patents

Abstract

PURPOSE:To save a high-speed multiplier required for chrominance signal processing by inputting an output signal of a multiplier and adding/subtracting the said signal and the resulting signal applied with a prescribed time delay to the said signal thereby extracting the result in a prescribed timing. CONSTITUTION:A chrominance signal C is inputted to a signal conversion circuit 401, where the signal is converted into a chrominance signal C10. Further, a data selecting circuit 500 gives a multiplier and a multiplicand to a multiplier 403. A multiplexer 402 processes selectively an ACC signal A0 and the C10, its output signal C11 is inputted to the multiplier 403 and multiplied with an output signal K10 from a multiplexer 427. An output signal C12 of the multiplier 403 is subjected to ACC control, color saturation adjustment and hue adjustment, matrix arithmetic is given at a delay circuit 430, an adder 431, and registers 432-434 and the signal is separated into R-Y, G-Y and B-Y signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital television device that performs signal processing after digitizing a video signal, and particularly to a color signal processing circuit thereof.

[Technical background of the invention]

Due to remarkable advances in digital IC technology, television receivers that were previously analog
It has become possible to digitally process signals at the terminal. The advantages of digitizing the signal processing circuit are, in terms of performance, the ability to perform high-precision, distortion-free processing unique to digital technology, improved resistance to temperature changes, changes over time, and noise resistance; and in terms of functionality, It is possible to connect with memory and computers, making it easy to perform multi-screen televisions, scanning speed conversion, still images, special effects processing, etc., and also making it easy to connect with various new media signals that are digital signals. etc.

FIG. 4 shows a general configuration of a digital video processing section. The analog video signal AV is subjected to sampling and digitization by an analog-to-digital converter 102,
It is converted into a digital video signal DV. Sampling is performed using a voltage controlled crystal excavator (hereinafter referred to as VCXO) 1o3
The row is determined by the sample/mother pulse φS outputted from the . The frequency of the sample 9 pulses φS is four times the color subcarrier frequency fBc, and the phase is synchronized with the demodulation axis of the color signal. The following explanation will take I,Q demodulation as an example. Therefore, the sample phases are ±I and ±Q phases in this case. The sample phase control' q control is phase-locked f (P
LL) circuit 106. The PLL circuit 106 calculates the sample phase in the color burst section of the input digital video signal D/V, and calculates the sample phase between this and I.

A phase error signal s1 corresponding to the difference from the Q phase is output.

The phase error signal S1 controls the oscillation frequency of the vcxo i o s, and closed loop control is performed so that the phase of the phase error signal φS is synchronized with the I and Q phases. Note that the sample/mother signal φS is supplied to each circuit as a reference clock in digital processing.

The digital video signal DV is separated into a luminance signal Y and a chrominance signal C by a luminance/chromaticity separation circuit (hereinafter referred to as a Y/C separation circuit) 1o8. The brightness signal Y is sent to the brightness processing circuit 1.
At step 12, contour, contrast, and brightness adjustments are performed, and then a new luminance signal Y2 is output.

The color signal C is subjected to automatic color saturation control (ACC), color saturation adjustment, hue adjustment, color demodulation, and matrix calculation in the color signal processing circuit 113, and is converted into three color difference signals R-Y.
, G-Y, and B-Y color signals and output. Note that the timing signal S2 necessary for this processing is input from the PLL circuit 106.

The color difference signals (R-Y), (G-Y), and (B-Y) are added to the luminance signal Y2 in adders 121, 122, and 123, and are output as color signals (R), (G), and (B). Output. After these signals are digital-to-analog converted, they drive a color cathode ray tube through an output circuit. The controller 124 also receives an image quality adjustment signal 125 controlled by the viewer, and a signal 126 necessary for various automatic controls and sent from the digital processing section to the controller 124. In controller 124, input signal 125.12
6 is processed based on a predetermined program and output as signal processing parameters 127 to each circuit of the digital processing section.

The above is an outline of the entire digital processing section. Next, the color signal processing circuit 113 related to the present invention will be explained.

FIG. 5 is a circuit diagram showing a conventional color signal processing circuit 113. The color signal (C) from the Y/C separation circuit ios is multiplied by the ACC signal A in a multiplier 201. multiplier, 2
The output signal C1 of 01 is input to the ACC circuit 203. Here, the amplitude of the color burst is detected, and the magnitude of the ACC signal A2 is controlled so that the amplitude approaches a predetermined target value. This corrects the amplitude change in the color signal (C) caused by the characteristics of the transmission path from the transmitting station to the receiver. A burst flag pulse (RFP) indicating the position of the color strike is input to the ACC circuit 203.
C operation timing is set. The output of multiplier 201 is input to data latch circuits 205 and 206.

In the data latch circuit 205, from the input signal C1! Phase data is extracted and the I signal (ID) is demodulated. The timing of data extraction is given by the noggle φI. Similarly, in the data latch circuit 206, Q-phase data is extracted by the pulse φQ, and the Q signal (QD) is demodulated. Pulses φI and φQ are color demodulation pulses (φC)
It will be built at 207 Iminda Road based on . Color demodulation, Luss (φC'), Hurst Fragno mother Luss (RFP)
) is output from the PLL circuit 106, and is a normal pulse that always provides constant phase timing (for example, Q phase).

Demodulated! The signal (ID) and Q signal (QD) are input to the color adjustment circuit 217. Here, the controller 12
Color saturation adjustment and hue adjustment are performed using a sine signal (A1stf+θ) and a cosine signal (Aliθ) input from 4. Signal (A1aθ)+(Asall!+θ
) are calculated by the controller 124 based on the color saturation signal AI+hue signal θ which are controlled by the viewer, and each has a value of As5h+θ+A1cXEθ.

The color adjustment circuit 217 performs gain adjustment and coordinate rotation calculations as shown in the following equation on the input I and Q signals, and outputs an output signal (
I'D) and Q' multiplied signal Q'D) are obtained.

In contrast, compared to the input, the output color will be A1 times more intense and the hue will change by 0.

The I/, Q/ signals (I'D') (Q'D) are processed by the matrix operation shown by the following formula in the multipliers 221 to 226 and adders 227 to 229, and the color difference signal (R-Y),
(G-Y), (B-Y).

Matrix coefficients (R1, RQ, G1.GQ, BI.

BQ) is given from the controller 124.

This value is not always a fixed theoretical value, but must be changed depending on the characteristics of the color cathode ray tube used.

[Problems with background technology]

In the conventional color signal processing method described above, at least nine multipliers are required for ACC processing, color saturation/hue adjustment, and matrix calculation. As is well known, the circuit scale of a multiplier is large; for example, an 8×8 bit multiplier has about 1000 gates. This becomes a serious problem when converting the system to t-IC. Matrix operations in particular require a large number of circuits. However, by digitizing this, it becomes easier to connect with externally input digital RGB signals, and many external components required for analog matrix circuits can be reduced, which is a great advantage. Therefore, there has been a strong desire to reduce the amount of circuitry in matrix circuits.

[Purpose of the invention]

This invention was made in view of the above circumstances, and is based on color signal processing (ACC, color saturation/hue adjustment).

The object of the present invention is to provide a color signal processing circuit that can significantly reduce the number of high-speed multipliers required for IJ wax calculation (IJ wax calculation), and specifically, can be realized with one multiplier.

[Summary of the invention]

This invention multiplies a color signal in a time-division manner by a matrix coefficient that has been multiplied by a color saturation signal and has also undergone a hue adjustment calculation in a controller, and adds the multiplication result and a value delayed by one sample time. By extracting the addition results at a predetermined timing, R-Y, G-Y, B-
This is to obtain the Y signal. This is done by leaving the computation of the user-adjusted signal, which can be considered not to change over time, to software processing in the controller, and by combining time-sharing multiplication), and by combining the multiplier as hardware with one
It can be done with just one piece.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention), the color signal (C) from the Y/C separation circuit is input to a signal conversion circuit 40,
-Q phase data is converted to +Q, -1 phase data is converted to +1, and so on...Q.

It is converted into a color signal 010 having a data format of I, Q, I, Q, I, . . . . This is a temporary operation to facilitate subsequent processing. The color signal CIO is ACC
It is input to multiplexer 402 together with ACC signal AQ output from circuit 405 . The output of multiplexer 402 is input to multiplier 403.

In the ACC circuit 405, the amplitude of the color burst is detected, and the ACC circuit 405 detects the amplitude of the color burst.
The magnitude of the signal AD is controlled by φ.

In the multiplexer 4θ2, selection processing is performed between the ice signal A and the color signal CIO, and the output signal ci
i becomes as shown in FIG. 2 (2b). This signal C1
1 is input to the multiplier 403 and the multiplexer 427
A multiplication process is performed with the output signal KJO (matrix coefficient, ACC signal) from . The output signal C12 of the multiplier 403 has been subjected to ACC control, color saturation adjustment, and hue adjustment, and is subjected to matrix calculation in a delay circuit 430, an adder 43J, registers 432 to 434, etc., and R-Y , G-Y, and IB-Y signals.

Next, multiplexers 402, 427, 421 to 426
Data select circuit 500 and register 411 configured by
416 will be explained with reference to FIGS. 2 and 3.

Data select circuit 5θ0- provides a multiplier and a multiplicand to multiplier 403. This data selection circuit 500
The carrier color signal CIO, color dyne control (ACC)
The first matrix coefficients RQI to B11 are given to the signal 0, and the second matrix coefficients RQ2 to BI2, which are 1 to 6, are given to the outputs of the registers 411 to 416.

FIG. 2 (2a) shows the color signal Cl0 output from the signal conversion circuit 401; FIG. 2 (2b) shows the output signal C1 of the multiplexer 4θ2; and FIG.
The multiplier or multiplicand signal KIO from .

1 horizontal period, periods other than images and color bursts (
In the diagram (To), the multiplexer 402 outputs the AC
C signal AO is output from multiplexer 427,
Matrix coefficients RQJ-B11 are sequentially output as signal KIO, and their products are stored in registers 411-416. As a result, 1 to 1 in the outputs of registers 411 to 416 correspond to matrix coefficients RQJ to BII and ACC.
Matrix coefficients RQ2 to BI2 which are products of CC signal colors
is obtained.

Next, during the burst period (T1 in the figure) of the color signal CIO, the multiplexer 402 selects and outputs the signal C1o from the signal conversion circuit 401, and the multiplexer 427 selects and outputs the ACC signal AO from the ACC circuit 405. I will. As a result, the color burst and the ACCCC signal color are multiplied by 6 in the multiplier 403, and in this case, the result) (is input to the ACC circuit 405. As a result,
ACC circuit 4θ5 obtains a new ACC signal AO.

Next, during the image period of the color signal cio (T omitted in the figure), the multiplexer 402 selectively derives the signal from the signal conversion circuit 401, and the multiplexer 427 and the multiplexer 42
1 to 426 are the output Kl-% of registers 411 to 416
- Matrix coefficients RQ2 to BI2 of 6 are sequentially selected and derived.

Figure 3 shows the period T! The relationship between the signal C1l input to the multiplier 403 and KIO in FIG. The calculation of the color difference signal is as follows. Therefore, when the sum of the output signal C12 of the multiplier 403 and the signal delayed by one sample is calculated, R- is calculated every other sample as shown in FIG. Y, G-Y, B-Y
Hail! Therefore, this signal is input to each register 4.
If extracted at 32.433°434, R-Y signal, G-
Y signal.

It can be used as a BY signal.

Next, matrix coefficients RQI to Bll sent from the controller 440 will be explained. The matrix coefficients RQI to Bll are matrix coefficients RQO and RIO according to the cathode ray tube characteristics programmed in advance.
, GQO, GIO, BQO.

BI (7) and the color saturation signal AI adjusted by the planner are calculated using the hue (θ). Therefore, the matrix coefficients RQ7 to BII are the saturation and hue adjustment information that are calculated by the controller 440. Including by the processing of micro-zorosescer.

The timing signal (tn) required for the above operation is the burst flag signal (BFP). A Hals (
It is made by the timing circuit 441 using φC).

〔Effect of the invention〕

According to the above-mentioned present invention, the number of hardware multipliers that were conventionally required for color signal processing, about nine, can be reduced to one by combining software processing and time-sharing matrix coefficient multiplication. only one multiplier is required.

Further, the multiplication of the ACC signal A, which changes every horizontal period, is performed by hardware using the no-signal period To, thereby significantly reducing the burden on the software. Furthermore, software calculations are completed using only fixed values and control signals from the user, further reducing the burden on software processing. As described above, the present invention provides a color signal processing circuit that can reduce the processing load caused by software, has a significantly reduced hardware configuration compared to the conventional technology, and is effective for integrated circuit implementation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the operation of the circuit in FIG. 1, FIG. 4 is a diagram for explaining the overall configuration of the digital video signal processing section, and FIG. The figure is a circuit diagram showing a conventional color signal processing circuit. 402.421 to 426.427...Multiple flexor, 403...Multiplier, 405...ACC circuit, 41
1-416, 432-434...Register, 4.90
...Delay circuit, 43...Adder, 440...Controller, 500...Data select circuit.

Claims (2)

[Claims] (1) In a digital television device that performs signal processing after digitizing an analog video signal, a plurality of first channels are used to calculate a carrier color signal separated from the digital video signal, a color dyne control signal, and a color difference signal. and a plurality of second matrix coefficients that are the product of the first matrix coefficients and the ColorDyne control signal.
a data select circuit which inputs matrix coefficients of 1 and outputs a multiplier and a multiplicand by selecting them; a multiplier to which the multiplier and multiplicand are input; an automatic color saturation control circuit that outputs the color dyne control signal according to the color burst width button; and an automatic color saturation control circuit that receives the output signal of the multiplier and extracts the second matrix coefficient contained in this signal A register that holds this signal and supplies it to the data selector circuit, and the output signal of the multiplier are input, this signal is added or subtracted from this signal delayed by a predetermined time, and the result of this addition or subtraction is converted to a predetermined value. 1. A color signal processing circuit comprising means for outputting a color difference signal (by extracting the color difference signal at a timing). (2) The data selection circuit outputs the carrier color signal and the color gain control signal as the multiplier or the multiplicand during the color burst period (T1) of the carrier color signal, and outputs the carrier color signal and the color gain control signal as the multiplier or the multiplicand during the image period (T2) of the carrier color signal. ) outputs the carrier color signal and the second matrix coefficient as the multiplier or the multiplicand, and outputs the carrier color signal as the multiplier or the multiplicand in a period (To) other than the period (T1) and (Tx) of the carrier color signal. The register outputs the first matrix coefficient and the ColorDyne control signal, and the register outputs the first matrix coefficient and the ColorDyne control signal output from the multiplier during the period (To). 2. The color signal processing circuit according to claim 1, wherein the color signal processing circuit holds a product and outputs the product as the second matrix coefficient.