JPH0682714B2 - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH0682714B2 JPH0682714B2 JP11521787A JP11521787A JPH0682714B2 JP H0682714 B2 JPH0682714 B2 JP H0682714B2 JP 11521787 A JP11521787 A JP 11521787A JP 11521787 A JP11521787 A JP 11521787A JP H0682714 B2 JPH0682714 B2 JP H0682714B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- lead frame
- film
- semiconductor chip
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はリードフレームに関し、特にテープ・キャリヤ
方式によって製造される半導体集積回路装置に用いるリ
ードフレームに関する。The present invention relates to a lead frame, and more particularly to a lead frame used in a semiconductor integrated circuit device manufactured by a tape carrier method.
従来、この種のリードフレームは、第３図に示すよう
に、均質の長尺状のポリイミド等の絶縁性のフィルム１
の両側に等間隔のスプロケット穴２を設け、中央部の半
導体チップ搭載領域にデバイス穴４をあけてデバイス穴
４の周囲に放射状に電極リード３を金属腐蝕法又は電気
めっき法等によって連続的に形成している。Conventionally, as shown in FIG. 3, a lead frame of this type has a uniform long insulating film 1 such as polyimide.
Sprocket holes 2 at equal intervals are provided on both sides of the device, and device holes 4 are formed in the semiconductor chip mounting area in the central portion, and electrode leads 3 are radially provided around the device holes 4 continuously by a metal corrosion method or an electroplating method. Is forming.
各電極リード３の半導体チップ搭載側はデバイス穴４に
突出していて、リード３の先端部3aにおいて半導体チッ
プ５の電極に熱圧着され、電極リード３の他端の電極部
3cに深針を接触させて半導体チップ５の回路の電気的特
性を測定している。The semiconductor chip mounting side of each electrode lead 3 projects into the device hole 4, and is thermocompression bonded to the electrode of the semiconductor chip 5 at the tip 3a of the lead 3, and the electrode portion at the other end of the electrode lead 3
A deep needle is brought into contact with 3c to measure the electrical characteristics of the circuit of the semiconductor chip 5.
このように、長尺状のフィルムに同一の電極リードパタ
ーンを連続して形成して、半導体チップを接続した後は
その電気的試験を自動的に行っている。In this way, the same electrode lead pattern is continuously formed on the long film, and after connecting the semiconductor chips, the electrical test is automatically performed.
上述した従来のリードフレームは、電極リードのパター
ンが絶縁性のフィルム上に等間隔に形成されているの
で、フィルム両側に打抜かれたスプロケット穴のピッチ
に等しい間隔の突起をもった歯車等によりスプロケット
穴を使ってフィルムを搬送することにより連続して自動
的に作業を行えるが、それぞれの電極リード間のフィル
ム上に導電性のパターンがないので、隣合った信号用電
極と電源用電極との電位的相違による電気的相互干渉が
起り、電気特性上の不良ないしは発振等の不具合を発生
させ歩留りを低下させるという問題点がある。In the conventional lead frame described above, since the electrode lead pattern is formed on the insulating film at equal intervals, the sprocket is formed by gears having protrusions at intervals equal to the pitch of the sprocket holes punched on both sides of the film. Although it is possible to continuously and automatically work by transporting the film through the holes, since there is no conductive pattern on the film between each electrode lead, there is no need to connect the adjacent signal and power electrodes. There is a problem in that electrical mutual interference occurs due to potential difference, which causes a defect in electrical characteristics or a defect such as oscillation, which lowers the yield.
本発明のリードフレームは、長尺状の絶縁性のフィルム
と、半導体チップ搭載領域の周囲の前記フィルム上に放
射状に形成した複数の電極リードとを備えるリードフレ
ームにおいて、前記電極リード間の前記フィルム上に形
成する導電部を有している。The lead frame of the present invention is a lead frame comprising a long insulating film and a plurality of electrode leads radially formed on the film around a semiconductor chip mounting area, wherein the film between the electrode leads is a film. It has a conductive part formed on it.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の平面図である。FIG. 1 is a plan view of the first embodiment of the present invention.
第１図に示すように均質のテープ状のポリイミド等の絶
縁性のフィルム１の両側に等間隔のスプロケット穴２を
設け、中央部に等間隔でデバイス穴４をあけてデバイス
穴４の周囲に放射状に電極リード３を金属腐蝕法又は電
気めっき法等によって連続的に形成する。As shown in FIG. 1, sprocket holes 2 are formed at equal intervals on both sides of a uniform tape-shaped insulating film 1 such as polyimide, and device holes 4 are formed at equal intervals in the central portion to surround the device holes 4. The electrode leads 3 are radially formed continuously by a metal corrosion method or an electroplating method.
更に、電極リード３の外周を囲って電気的に接続された
導電部としての干渉防止パターン６を形成し接地電位電
極７に接続してそれぞれの電極リード３を電気的に遮蔽
する。Further, an interference prevention pattern 6 is formed as a conductive portion that is electrically connected to surround the outer circumference of the electrode lead 3 and is connected to the ground potential electrode 7 to electrically shield each electrode lead 3.
電極リード３の先端部3aにおいて電極リード３は半導体
チップ５の電極に熱圧着され、電極リード３の他端の電
極部3cに深針を接触させて半導体チップ５の回路の電気
的特性を測定する。At the tip portion 3a of the electrode lead 3, the electrode lead 3 is thermocompression bonded to the electrode of the semiconductor chip 5, and a deep needle is brought into contact with the electrode portion 3c at the other end of the electrode lead 3 to measure the electrical characteristics of the circuit of the semiconductor chip 5. To do.
干渉防止パターン６は、通常は、接地電位電極７に接続
されているが、必要に応じて任意の電位を与えてもよ
い。The interference prevention pattern 6 is normally connected to the ground potential electrode 7, but any potential may be applied if necessary.
第２図は本発明の第２の実施例の平面図である。FIG. 2 is a plan view of the second embodiment of the present invention.
第２図に示すように、第２の実施例では、干渉防止パタ
ーン6aは電極リード３の周辺及びフィルム１の両側部を
除くフィルム１上をすべて覆うように形成される。As shown in FIG. 2, in the second embodiment, the interference prevention pattern 6a is formed so as to cover the entire area of the film 1 except the periphery of the electrode lead 3 and both side portions of the film 1.
第２の実施例によれば、干渉防止パターンの形状が単純
になるので、製造工数が短縮できる利点がある。According to the second embodiment, since the shape of the interference prevention pattern is simple, there is an advantage that the number of manufacturing steps can be shortened.
以上説明したように本発明は、電極リードの周囲を囲っ
て導電部を設けることにより、電極リード間の電気的相
互干渉を皆無とすることができるので、相互干渉による
電気特性上の不良及び発振等の不具合の発生を防止して
歩留りを向上できるという効果がある。As described above, according to the present invention, by providing the conductive portion around the electrode leads, it is possible to eliminate the electrical mutual interference between the electrode leads. This has the effect of preventing the occurrence of problems such as the above and improving the yield.
第１図は本発明の第１の実施例の平面図、第２図は本発
明の第２の実施例の平面図、第３図は従来のリードフレ
ームの一例の平面図である。 １……フィルム、２……スプロケット穴、３……電極リ
ード、3a……先端部、3c……電極部、４……デバイス
穴、５……半導体チップ、6,6a……干渉防止パターン、
７……接地電位電極。1 is a plan view of a first embodiment of the present invention, FIG. 2 is a plan view of a second embodiment of the present invention, and FIG. 3 is a plan view of an example of a conventional lead frame. 1 ... Film, 2 ... Sprocket hole, 3 ... Electrode lead, 3a ... Tip part, 3c ... Electrode part, 4 ... Device hole, 5 ... Semiconductor chip, 6,6a ... Interference prevention pattern,
7 ... Ground potential electrode.
Claims (1)
プ搭載領域の周囲の前記フィルム上に放射状に形成した
複数の電極リードとを備えるリードフレームにおいて、
前記電極リード間の前記フィルム上に形成する導電部を
有することを特徴とするリードフレーム。1. A lead frame comprising a long insulating film and a plurality of electrode leads radially formed on the film around the semiconductor chip mounting region,
A lead frame having a conductive portion formed on the film between the electrode leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11521787A JPH0682714B2 (en) | 1987-05-11 | 1987-05-11 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11521787A JPH0682714B2 (en) | 1987-05-11 | 1987-05-11 | Lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63278359A JPS63278359A (en) | 1988-11-16 |
| JPH0682714B2 true JPH0682714B2 (en) | 1994-10-19 |
Family
ID=14657262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11521787A Expired - Lifetime JPH0682714B2 (en) | 1987-05-11 | 1987-05-11 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682714B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940008342B1 (en) * | 1990-06-01 | 1994-09-12 | 가부시키가이샤 도시바 | Semiconductor device using film carrier |
| DE10142483B4 (en) * | 2001-08-31 | 2006-12-14 | Infineon Technologies Ag | Electronic component with external flat conductors and a method for its production |
-
1987
- 1987-05-11 JP JP11521787A patent/JPH0682714B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63278359A (en) | 1988-11-16 |
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