JPH0682532A - Cpu - Google Patents

Abstract

PURPOSE:To obtain a CPU having such a structure that a debug apparatus can be connected while being fixed directly to a printed board. CONSTITUTION:An internal chip (CPU chip) is contained in a case 1, debug sockets 3a are formed at the same pitch as that of terminal pins 4 while conducting therewith, and a switch 2 for electrically connecting or disconnecting the signal lines between I/O part of the internal chip and the terminal pins 4 is also provided. When debug is performed, the switch 2 is switched from normal operation side to interruption side, with the CPU being fixed directly to a printed board, thus interrupting the I/O part of the internal chip from the terminal pins 4 and then probes of the debug apparatus 6 are loaded into the sockets 3a made in the cover part 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU used in an information processing apparatus, and more particularly to a CPU having a structure in which a debugging device is electrically connected to its terminal pin.

[0002]

2. Description of the Related Art In order to confirm or correct the operation of an information processing apparatus, especially the operation of a program, it is widely practiced to connect a debug device to a printed circuit board in the apparatus. In this case, a means for removing the CPU on the IC socket mounted on the printed board and mounting the probe of the debug device on the IC socket has been adopted.

[0003]

Therefore, the CPU is an IC
There is no problem when it is held in the socket and mounted on the printed circuit board, but there is a drawback that the debug device cannot be used when it is directly mounted on the printed circuit board.

Further, in a conventional CPU mounted on a printed circuit board via an IC socket, a contact failure may suddenly occur between the input / output unit and the IC socket, which is problematic in terms of reliability. was there.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a highly reliable CPU which enables the use of a debug device directly attached to a printed circuit board.

[0006]

A CPU according to the present invention is a CPU mounted on a printed circuit board, comprising an internal chip,
A case for accommodating the internal chip, a means for guiding a predetermined voltage supplied from the outside to the internal chip, a plurality of terminal pins formed on the bottom of the case, the terminal pins and the input / output section of the internal chip. And an energizing switching means for electrically connecting or disconnecting each of the terminals and a lid portion for covering the case, the lid portion forming a debugging socket electrically connected to the terminal pin and having the same pitch interval as the terminal pin. .

The energization switching means is provided, for example, between an output driver provided between the output section of the internal chip and the terminal pin, and between the input section of the internal chip and the corresponding terminal pin. And an input receiver and a switch for turning on and off the power supply to the output driver and the input receiver.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is an external perspective view of a CPU according to an embodiment of the present invention, in which 1 is a case for accommodating an internal chip (CPU chip), 2 is a switch, 3 is a cover, and 4 is a terminal pin. . Further, 5 is a printed circuit board to be mounted. Debug sockets 3a are formed on the lid 3 so as to be electrically connected to the terminal pins 4 and at the same pitch intervals as the terminal pins 4.
It has a structure capable of accommodating the probe of the debug device 6. The switch 2 electrically connects or disconnects the signal line between the input / output portion of the internal chip housed in the case 1 and the terminal pin 4, respectively.

When performing debugging, as shown in FIG. 1, with the CPU mounted on the printed circuit board 5,
The debugging device 6 is provided with an energization switching means including the switch 2 to interrupt the signal line between the input / output portion of the internal chip and the terminal pin 4.
The probe is attached to the debugging socket 3a of the lid 3. However, the power of the CPU must be supplied from the printed circuit board 5 and the probe of the debug device 6.

FIG. 2 is an internal block diagram of the CPU according to the present embodiment, in which the corresponding portion is surrounded by a chain line. In FIG. 2, 2 is the switch, 21 is an internal chip, 22 is an external power supply terminal, 23 is an output driver, 24 is an input receiver,
25 is an output terminal pin, 26 is an input terminal pin, 27 is an output socket, 28 is an input socket, and a to d are lead wires. In this figure, for the sake of convenience of description, the number of signal lines extending from the input / output unit of the internal chip 21 is one.

In such a structure, the switch 2 is turned off.
In the FF state, a voltage (for example, 5V) supplied from the external power supply terminal 22 causes a current to flow through the lead wire b, and the output driver 23 is enabled. At this time, when the output signal A becomes active, it is output from the output driver 23 to the outside through the lead wire c and the output terminal pin 25. Similarly, the input signal B is input terminal pin 26,
The internal chip 21 passes through the lead wire d and the input receiver 24.
To enter. As a result, the CPU operates normally.

On the other hand, when the switch 2 is on, the voltage supplied from the external power supply terminal 22 flows to the lead wire a side and is guided to the ground wire. As a result, the output driver 23
Is disabled and the output driver 23 does not output even if the output signal A becomes active. Similarly, the input signal B is also input to the input receiver 24 through the input terminal pin 26 and the lead wire d.
Is not output to. As a result, the output socket 27 and the input socket 28 are electrically cut off from the internal chip 21, so that a probe of a debug device can be connected to the sockets 27 and 28 for debugging.

FIG. 3 is an internal configuration diagram of a CPU according to another embodiment of the present invention, in which the configuration of the energization switching means is changed. That is, the input / output section of the internal chip 21 and each terminal pin 2
Internal relays 31 and 32 are inserted and connected between 5 and 26, respectively, and energization to these internal relays is switched by a switch 2.

In such a configuration, when the switch 2 is in the ON state, the voltage from the external power supply terminal 22 causes a current to flow through the coils of the internal relays 31 and 32 to be in the ON state, and the output signal A becomes active. This is output to the outside from the output terminal pin 25 through the first internal relay 31. Similarly, the input signal B is input from the input terminal pin 26 and is guided to the internal chip 21 through the second internal relay 32. As a result, the CPU operates normally.

On the other hand, when the switch 2 is off,
Since the internal relays 31 and 32 are turned off and the internal chip 21 and the terminal pins 25 and 26 are cut off, it is possible to connect a probe of a debug device to the input / output sockets 27 and 28 for debugging. Become.

FIG. 4 is also an internal configuration diagram of a CPU according to another embodiment of the present invention, in which the energization switching means is replaced with another configuration. That is, the secondary side terminals of the photocouplers 41 and 42 are connected between the input / output section of the internal chip 21 and the terminal pins 25 and 26, respectively, and the switch 2 is energized to the primary side of these photocouplers 41 and 42. It is designed to be switched by.

In such a configuration, when the switch 2 is in the ON state, the voltage from the external power supply terminal 22 causes a current to flow in the primary side of each of the photocouplers 41 and 42 to be in the ON state, and the output signal A is active. Then, this passes through the secondary side of the first photo coupler 41 and the output terminal pin 25
Is output to the outside. Similarly, the input signal B is input from the input terminal pin 26 and is guided to the internal chip 21 through the secondary side of the second photocoupler 42. This makes the CPU
Performs normal operation.

On the other hand, when the switch 2 is in the OFF state,
Since the photocouplers 41 and 42 are turned off and the internal chip 21 and the terminal pins 25 and 26 are cut off,
It is possible to connect a probe of a debug device to the input / output sockets 27 and 28 for debugging.

[0020]

As is apparent from the above description, according to the present invention, the state in which the CPU is removed from the printed circuit board is formed by disconnecting the internal chip and the terminal pin by the energization switching means. can do. Therefore, by mounting the probe of the debug device on the debug socket formed on the lid, the debug work can be easily performed while directly attached to the printed circuit board.

Further, since the conventional CPU IC socket is not required, the number of parts can be reduced, which is advantageous in cost. Further, it is possible to avoid a failure due to poor contact due to the IC socket, and it is possible to improve reliability.

[Brief description of drawings]

FIG. 1 is an external perspective view of a CPU according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a CPU according to an embodiment of the present invention.

FIG. 3 is an internal configuration diagram of a CPU according to another embodiment of the present invention.

FIG. 4 is an internal configuration diagram of a CPU according to another embodiment of the present invention.

[Explanation of symbols]

 1 ... Case 2 ... Switch 3 ... Lid 3a ... Debug Socket 4 ... Terminal Pin 5 ... Printed Circuit Board 6 ... Debugging Device (Probe) 21 ... Internal Chip 22 ... External Power Supply Terminal 23 ... Output Driver 24 ... Input Receiver 25 ... Input Terminal pin 26 ... Output terminal pin 27 ... Input socket 28 ... Output socket 31, 32 ... Internal relay 41, 42 ... Photocoupler a ... d ... Lead wire A ... Output signal B ... Input signal

Claims (4)

[Claims] 1. A CPU mounted on a printed circuit board, comprising: an internal chip; and a case for housing the internal chip.
Means for guiding a predetermined voltage supplied from the outside to the internal chip, a plurality of terminal pins formed on the bottom of the case, and electrically connecting or disconnecting these terminal pins and the input / output section of the internal chip. A CPU comprising an energization switching means and a lid portion that covers the case, wherein the lid portion forms a debugging socket that is electrically connected to the terminal pin and has the same pitch interval as the terminal pin. 2. The energization switching means includes an output driver provided between the output section of the internal chip and the terminal pin, and an input provided between the input section of the internal chip and the corresponding terminal pin. 2. The CPU according to claim 1, comprising a receiver and a switch for turning on and off the power supply to the output driver and the input receiver. 3. The energization switching means comprises an internal relay inserted and connected between the input / output unit of the internal chip and the terminal pin, and a switch for turning on / off the energization of these internal relays. And C according to claim 1.
PU. 4. The energization switching means is a photocoupler whose secondary side terminals are connected between the input / output section of the internal chip and the terminal pin, and energization of the photocoupler to the primary side is turned on / off. 2. The CPU according to claim 1, wherein the CPU comprises a switch.