JPS62169204A - Sequence controller - Google Patents

Abstract

PURPOSE:To simplify a program by providing a stepping counter circuit corresponding to each process in case of the process stepping control of a sequence controller and operating this counter when the stepping condition is satisfied. CONSTITUTION:The sequence controller consists of an input part 2 connected to a contact group 1 as an external input signal source, a CPU 3 as a logic decision part, an output part 6, a program part 7, etc. In this case, a stepping counter circuit 8 corresponding to each process is provided as the means which holds a pertinent process in the turn-on state until the stepping condition of the process stepping control is satisfied. When a specific instruction is called from a user RAM 4, the CPU 3 decides which process the counter 8 indicates; and if this process coincides with the process called from the user program, it is checked whether the stepping condition of the external input is turned on or not. As the result, the counter 8 is stepped if it is turned on, but otherwise, no processings are performed.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a sequence control device used in a system in which condition control and process step control are mixed, and particularly relates to a sequence control device suitable for simplifying program creation. .

[Prior art]

FIG. 9 shows the system configuration of a conventional stored program type sequence control device.

In the figure, 1 is a contact group that is an external input signal source, and 2 is a contact group 1.
Human power s, which receives external input signals from.

3 is a central processing unit (hereinafter referred to as CP) which is a logic judgment section.
(referred to as U), 4 is a sequence program storage unit Nizar AM, 5 is a system ROM that stores processing procedures and program procedures of sequence 70 grams, 6 is a CP
An output unit outputs the result of the output processing of U3 to the outside, and 7 is a program unit, which is an instruction loading means for storing sequence instructions as a program in the user RAM 4.The CPU 3 sequentially calls the sequence program from the user kLAM 4, Input signal I00 read through two human power sections. IOI,...Im determines whether or not it satisfies the logical state set in the program, and the output processing result is output #6 (1) Output 050,051
, . . . is given to the external device as On.

A method for programming a process step control as shown in FIG. 10 using this conventional sequence control device will be explained.

In FIG. 10, when the sequence control device is started, the process goes to step 200, and when the external input signal 0 is turned ON, the process goes to step 200.
Indicates that the process advances from 0 to step 201. Similarly, when the external human power 1 is turned on in step 201, the process advances to step 202, and when the external human power 2 is turned on, the process advances to step 203.

In the process step control shown in FIG. 10, the process always proceeds in order.

For example, in process 200, external human power 2 is ONL, even if process 20
3. There is no hesitation.

i! The method shown in Figs. 11 and 12 was studied as a method for creating a flow diagram for step-by-step process control.
No. 127426, i.e. No. 11
The figure shows a program using only sequence instructions without using application instructions. To explain the operation in FIG. 11, when the sequence system # apparatus ill' starts, each process
, 201, 202, and 203 are OFF, the process 200 becomes UNvc, and the self-holding circuit shown by the broken line in the figure operates to maintain the ON state of the process 200. When the external human power O is turned on in this state, the process 201 is changed to the UNL pre-process 200.
The self-retention is lost, and step 200 is OF')'.

From then on, the process step control shown in Figure 5g10 can be realized with the same operation as F, but a self-holding circuit is required.

This self-maintaining (applied instruction FUNO2 that performs the same operation as the gl path) makes the program complicated and not intuitive.
is being considered and can be programmed as shown in Figure 12. However, an output negation is required to reset the previous process.

For that purpose, the latch circuit and latch circuit edge set signal, fM of reset No. 1g! There is a problem in that a generation source is required, which complicates the hardware configuration.

[Purpose of the invention]

An object of the present invention is to provide a sequence control I41 device that can be used for both condition control and process step control, and when a process step control trap is applied, it can easily perform programming without requiring complicated intercooking between processes. [Summary of the Invention] The present invention periodically repeats an operation of calling and processing a tourogram from a sequence program storage part and the above storage part, so that an external input signal is set to a logic state set by the program. The sequence control fctIIL includes a logic determining section that performs a specific output process when the logic determining section is satisfied, and an output section that outputs the result of the output process of the logic determining section to the outside.

The storage section is equipped with a command writing means for storing a process step control dedicated I/,) counter command, and a stepping counter circuit corresponding to each process, and the stepping counter circuit is controlled by a signal from the logic judgment section. and when a stepping condition of the program is satisfied when the specific instruction is processed by the logic determining unit, the corresponding output state of the stepping counter is held until the next stepping condition is satisfied;
This is characterized by the fact that it is configured to automatically release the holding of the previous output state when the next step condition is satisfied.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 1 to 8.

An Uninvented Embodiment YMI This will be explained with reference to FIGS. 1 to 3. Part 1 (2) shows the system configuration of this embodiment.

The sequence control device in this embodiment includes an input section 2 connected to a contact group 1 which is an external input signal source, a CPU 3 which is a logic judgment section, a user (user) f, AM 4, and a sequence program storage section which is a sequence program storage section. System RUM5, CPU3 that stores processing procedures and program procedures
The CPU 3 has a basic configuration consisting of an output s6 for outputting the output processing result to the outside, and a program s7 which is an instruction writing means. The operation to be processed is periodically VC-operated, and when the external input (H9) read through the input section 2 satisfies the logic state set by the cough program, a specific output filling is performed.

The difference of this embodiment from the conventional example is that 8 stepping counter circuits corresponding to each process are provided as a means for maintaining the ON state of the process σ] in order to determine the step condition of the work type step control. There is K. For this stepping counter circuit 8.

A step signal is sent to C1'U3 as a processing result of the process step control program, and the stepping counter circuit 8 is set to 1.
Only the process progresses. The state of the stepping counter circuit 8 is taken into the CPU 3, and the configuration is such that it can be determined which step it is in.

Next, we will explain the operation of a program example not shown in Fig. 3. PUNloo in the same figure is a specific command dedicated to process step control, and like other It is something that will be remembered. If the user stores the flocram in the same figure in RAM4 and runs it continuously,
When the specific command FUN 100 is called from the user KAM4, the CPU 3 +1 step pink counter 8 is set to 44j, and the step called from the user program and the step counter 80 are determined. If they do not match ("J is also not processed,
If the processes match, the step condition of external input is (JN(,
Check to see if the one-step advance condition is ON (, -(If not, do nothing as above and turn the one-step advance condition ON ().

If so, the CPU 3 sends an increment signal to the stepping counter 8 to cause the stepping counter 8 to increment.

Therefore, in order to perform the second worst operation, it is necessary to create a program as shown in FIG. 3 (there is no need to create a self-holding circuit as shown in FIG. 11 or a pre-process reset program as shown in FIG. 12).

In addition, condition control programs such as those for the third and third plans can be processed as before, and condition control programs and process step control programs can coexist.

Next, the implementation of the memory of the sequence control device will be explained.

Traditionally, sequence control uses switches and relays.

It consists of dedicated hardware logic using timers, etc., and is interconnected with each other, so it lacks versatility and cannot readily respond to modifications and changes. When it comes to slightly complex control circuits, there are many problems, such as long circuit design delays, and there has been rapid progress recently.

These controllers mainly store control information in a memory element (storage element), and are equipped with a microcontroller (central processing element)
This is a so-called stored film method in which processing is carried out using a computer, and its special feature is that the sequence control contents can be changed freely and easily.

Is 1R131A a σ semiconductor? Internal implementation of a conventional example of a programmable controller based on the main body! 1, and 21 is centered around the CPU3.

The system 1 (,0M5) stores control procedures so that the device itself can operate as a programmable controller.It is a control board in which various other semiconductors are mounted on a printed circuit board, and 22 is an external input No. III J5 or This is an I10 board for outputting a small signal to the outside.4
vZ scene program'lt memorize user nine AM
It is mounted on the socket 28 for easy replacement and attachment/detachment, and is placed on the front surface of the board 10.

Also, 24 is a relay for driving an external load and is connected to the internal weak current circuit. It also serves as the third edge. Also.

26.27 is the control 9A1 board 21 and I10 described above.
The old line to the user memory 4 described above, which is a connector for electrically connecting the board and kvL, is arranged in many ridges.

Yota 3 is the control board 1. This is a case that accommodates the L10 board 22"k, and although there is no word of mouth, there are other parts that are accommodated in the L10 board. Although not shown, the above-mentioned L10
A cover corresponding to the case 23 is provided on the ζ surface of the Ts plate V) to cover internally mounted components.

Now, in implementing such a programmable controller, the external S load is electrically connected to the relay 24 via the terminal block 30.

Some types of external loads generate noise of several thousand volts, and although the relay 24 is electrically isolated from the internal low-power circuit, the semi-reflective components mounted around the relay 240, especially the user memory 4, may generate noise of several thousand volts. A major drawback is that it is susceptible to this influence. In addition, as shown in Figure 14, there are noise infiltration routes that are caused by airborne M■, that are transmitted through the surface of the printed circuit board, which is an electrical body, and are harmed by the signal line ■, and also for the CPU 3 and other live conductor parts. It is a bad example of giving.

Intrusion route ■The space between vehicles is a problem, but
This capacity is extremely small.

It is known that induced noise decreases in inverse proportion to the square of the distance, so it is not a particular problem.
3 and the user memory 4 must be transmitted via the connectors 26 and 27, the signal line length is inevitably long, and there is a disadvantage that it is susceptible to the influence of noise V.

In the example shown in FIG. 13, the I/(J board 22 is placed on top.

The control board 21 is placed at the bottom, but in order to avoid noise induction, it is placed in front of the control board 1.
When the Nisa memory 4 is mounted on the top and the I10 board 22 is placed on the bottom, there is a maintenance problem in that it is inconvenient to convert the relay 24, which has a short contact life.

This embodiment blocks out the effects of noise from the outside while maintaining maintenance functions such as attaching and detaching the user memory 5 and relays described above, and is highly reliable.

The following 1 will provide the grammar pull controller
This embodiment will be explained in detail with reference to FIGS. 4 to 8.

FIG. 4 shows the state in which the control board 21 and the I10 board 22 are mounted. The difference from FIG. 13 is that (1) the user memory is removably mounted on the control board 21 via the 4t socket 11; .

(2) A hole B having a predetermined gap around the socket 11 is provided in the I10 board so that the user memory 4 is exposed on the I10 board.

(3) The connectors 26 and 27 for signals between the eP03 and the user memory 4 have been eliminated.

It is.

In other words, (1) is that although the printed circuit board of the I/O board 22 is a visiting body and has a dielectric constant peculiar to a printed circuit board, there is a 3 vc in the hole between the I10 board 22 and the user memory 4.
Because of this gap, it is independent of the dielectric constant specific to the printed circuit board, and noise induction from the surface of the printed circuit board is eliminated. In addition, (2) allows the user to easily attach and detach from the front, and the CPU 3 to user memory 4.
The length of the signal line between the two is minimized to ensure that K<K is less affected by noise. (3) can be made unnecessary as a result of (1) and (2) above.

Now, FIG. 5 is a detailed sectional view taken along the line A--A in FIG. 4, and shows how the socket 11 is mounted and arranged. That is, in the conventional example described above, the socket 11 is mounted on the I10 board 22, so one leg of the board contact portion is
is short, but in the present invention, it is made longer by one foot by the necessary dimension between the control board 21 and the I10 board 22.

It also shows that the CPU 3 and user memory 4 can be placed very close to each other.

Now, in FIG. 5, the legs of the socket 11 are made long enough to be visible on the surface of the I10 board 22, or as shown in FIG. maintainability can be improved.

That is, in the above-mentioned embodiment, the cover 32 is removed for maintenance, but if the cover 33 is
By removing the trap, the user memory 4 can be converted. This is effective when the sequence control contents change frequently.

Next, another example regarding the position of the hole in the I10 substrate will be described with reference to FIG.

Although FIG. 7a shows a plan view and FIG. 7b shows a cross-sectional view, it is also possible to have one notch as shown in FIG.

That is, depending on the arrangement of internal parts, 41. If it is necessary to provide a socket at the end, cut out the I10 board 22 and place a socket with long legs in this part.

Alternatively, the two holes formed in the I10 substrate 22 may be cutouts.

Next, another embodiment in which the distance between the user memory 4 and the CPU 3 described above is shortened will be described with reference to FIG. 8 rc.

In the example shown in FIG. 7, a general socket 11 is used, but the
Figure a shows an example using a Z socket 110 whose leg width is wider than that of C)'U3.

The CPU 3 is arranged between 110 sockets. If K is set in this manner, the leg pitch of a typical CPU3σ is about 15 degrees, so if it is done as shown in FIG. 8a, it can be shortened by a maximum of 15 degrees.

In other words, the noise resistance performance is greatly increased.

Now, the arrangement shown in FIG. 8 is opposite to the mounting surface of the CPU 3ft socket 11. That is, it is effective when all other components on the CPU board 21 are also mounted on the opposite side of the socket 11. This piece is CPLJ board 2
Not only does the distance between the 1 to I10 boards 22 become shorter,
The distance between the ePU 3 and the sockets 1-11 is also significantly shortened, and the noise resistance performance is further improved.

According to the above, the CPU 3 to CPU 3 is not affected by external noise induced from the surface of the printed circuit board, and is not influenced by a single electric current. It is possible to eliminate the influence of noise induced in the 4N line between the memory 4 and the memory 4, and it is highly reliable with high noise resistance and does not damage the maintenance function such as attaching and detaching the user memory by a person. In this embodiment, a user RAM is used as the user memory, but there is no need for this (ROM may also be used).

It also eliminates the need for traditional connectors, so
This has the effect of eliminating the problem of poor connector contact.

In addition, since the connectors described above are for weak MJK, the internal contacts are gold-plated, which makes them very expensive. Economical.

Rough (when combined with a C board and a board connector,
It is effective when the size JM is able to retain water or the hole is made slightly thicker (if it is 4L, there will be no problem due to dimensional accuracy and the combination is easy. Also, as shown in Fig. 13) In the case of the conventional example, the connector 7 is mounted on the printed circuit board, so that there is no problem of undesirable soldering dust.

〔Effect of the invention〕

According to the present invention, when process step control is performed by a sequence control device, by processing a specific command stored in a sequence program storage unit, when a small progress step (F) of the program is established, the stepping counter circuit Since the process state is held until the next step condition is met, programs can be easily programmed without the need for complex interlocks.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram showing one embodiment of the present invention, 1t
The KZ diagram is a ladder diagram showing a program example when this embodiment is applied to process step control, Fig. 3 is a ladder diagram when applied to condition control, and Fig. 4 is an example of an implementation configuration in this embodiment. Perspective view Figure 5 is a cross-sectional view taken along A-A @ of Figure 4.
FIG. 6 is a sectional view showing an example of application of the socket 11 shown in FIG. 5. Figure 7a is a plan view showing an example of hole application, b ij Y -
Ys sectional view, Fig. 8 shows a sectional view of another application example of the socket 11, and Fig. 9 shows conventional sequence manufacturing! ! 2 Rainbow system configuration diagram, εi! , ' 10 (9) is a flowchart of process step control, and Figures 11 and 12 are respectively diagrams showing examples of programs using conventional σ) sequence control devices. FIG. 14 is a perspective view showing a configuration example, and FIG. 14 is a side view illustrating the propagation of external noise. Go\3.

Claims (1)

[Claims] a sequence program storage section, a logic determination section that periodically repeats the operation of calling and processing a program from the storage section and performs a specific output process when an external input signal satisfies a logic state set in the program; A sequence control device comprising an output section for outputting the result of the output processing of the determination section to the outside, including an instruction writing means for storing a specific instruction dedicated to process step control in the storage section, and a stepping device corresponding to each process. and a counter circuit, the stepping counter circuit is controlled by a signal from the logic determining section, and if a stepping condition of the program is satisfied when the specific instruction is processed by the logic determining section, the state of the process corresponding to the step condition is satisfied. 1. A sequence control device characterized in that the sequence control device is configured to hold the previous process state until the next step condition is satisfied, and release the holding of the previous process state when the next step condition is satisfied.