JPH0680856B2 - Semiconductor laser - Google Patents
Semiconductor laserInfo
- Publication number
- JPH0680856B2 JPH0680856B2 JP59206237A JP20623784A JPH0680856B2 JP H0680856 B2 JPH0680856 B2 JP H0680856B2 JP 59206237 A JP59206237 A JP 59206237A JP 20623784 A JP20623784 A JP 20623784A JP H0680856 B2 JPH0680856 B2 JP H0680856B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- main surface
- semiconductor laser
- active region
- semiconductor crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/12—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Semiconductor Lasers (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体レーザの電極構造に関する。The present invention relates to an electrode structure of a semiconductor laser.
第１図は、従来の電極構造をもつ半導体レーザチツプの
斜視図である。通常、半導体結晶４に設けた二つの電極
の内、一方の電極（例えば、本例の下部電極３）を放熱
体に接続し、他方の電極（例えば、本例の上部電極２）
には、リードワイヤ５をワイヤボンデイングにより接続
していた。FIG. 1 is a perspective view of a semiconductor laser chip having a conventional electrode structure. Usually, of the two electrodes provided on the semiconductor crystal 4, one electrode (for example, the lower electrode 3 in this example) is connected to a heat radiator, and the other electrode (for example, the upper electrode 2 in this example).
The lead wire 5 was connected to the wire by wire bonding.
また、通常、同図に示すように、レーザ発振の生じる活
性領域１に近い主面側には、ウエーハからチツプに分割
する際の切断位置合わせや、切断時の加工性の向上、発
光スポツト位置を示し目安とする、などの目的で、部分
的に電極を設けていた。このような手法は既によく知ら
れているが、例えば特開昭59−23576号公報にも、類似
の記載がみられる。Further, as shown in the figure, usually, on the main surface side near the active region 1 where the laser oscillation occurs, the cutting position is aligned when the wafer is divided into chips, the workability at the time of cutting is improved, and the light emitting spot position. The electrodes were partially provided for the purpose of indicating and indicating. Such a method is already well known, but similar description is found, for example, in Japanese Patent Laid-Open No. 59-23576.
一方、半導体レーザでは、駆動電流を変化させることに
より、レーザ出力光の直接変調を行うことが可能であ
る。高速変調のためには、電極面積をできる限り狭くし
て、素子の静電容量を減少させることが必要である。し
かし、部分的に設けた電極であつても、前記のようにワ
イヤボンデイングを行うための面積が必要であり、大幅
に電極面積を低減することは不可能であつた。On the other hand, in the semiconductor laser, it is possible to directly modulate the laser output light by changing the drive current. For high speed modulation, it is necessary to reduce the capacitance of the device by making the electrode area as narrow as possible. However, even with partially provided electrodes, the area for wire bonding is required as described above, and it has been impossible to significantly reduce the electrode area.
本発明の目的は、ワイヤボンデイングのための電極領域
を失なうことなく、素子の静電容量の低下を図り、超高
速度調に適した半導体レーザを提供することにある。An object of the present invention is to provide a semiconductor laser suitable for ultra-high speed adjustment, in which the capacitance of the device is reduced without losing the electrode region for wire bonding.
第２図は、本発明の構成を示す斜視図である。半導体結
晶14の主面側には、活性領域11を励起するための電極層
の幅を活性領域幅の15倍以下に抑えた上部電極12を設
け、素子の静電容量を大幅に低減した。FIG. 2 is a perspective view showing the structure of the present invention. On the main surface side of the semiconductor crystal 14, an upper electrode 12 in which the width of an electrode layer for exciting the active region 11 was suppressed to 15 times or less the active region width was provided, and the capacitance of the device was significantly reduced.
また、上部電極12からリードを取出すためのリード電極
16と、ワイヤボンディング専用の領域となるボンディン
グパッド17を設け、リードワイヤ15をボンディングして
いる。Also, a lead electrode for extracting the lead from the upper electrode 12.
16 and a bonding pad 17 which is a dedicated area for wire bonding are provided to bond the lead wire 15.
さらに半導体結晶11の主面側に部分的に設けられた絶縁
膜層20上に、リード電極16とボンディングパッド17が設
けられている。したがつて、リード電極とボンディング
パッドに起因する静電容量は、結晶内部に存在するpn接
合容量と絶縁膜の部分に形成される静電容量の直列接続
となる。このため、半導体結晶11上に直接リード電極と
ボンディングパッドを形成した場合に比較して、これら
の電極に起因する静電容量を数分の１に低減することが
できる。Furthermore, the lead electrode 16 and the bonding pad 17 are provided on the insulating film layer 20 partially provided on the main surface side of the semiconductor crystal 11. Therefore, the capacitance caused by the lead electrode and the bonding pad is a series connection of the pn junction capacitance existing inside the crystal and the capacitance formed in the insulating film portion. Therefore, as compared with the case where the lead electrode and the bonding pad are directly formed on the semiconductor crystal 11, the capacitance caused by these electrodes can be reduced to a fraction.
以上のような電極構成を採ることにより、主面側に設け
られた電極による静電容量を、従来の数分の１に低減す
ることができる。By adopting the electrode configuration as described above, it is possible to reduce the electrostatic capacitance due to the electrodes provided on the main surface side to a fraction of the conventional value.
以下、本発明の実施例を第３図，第４図，第５図，第６
図，第７図により説明する。Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3, 4, 5, and 6.
This will be described with reference to FIGS.
実施例１ 第３図は、本発明の一実施例を示す平面図、第４図は第
３図のＡ−Ａ′断面図、第５図は第３図のＢ−Ｂ′断面
図である。Embodiment 1 FIG. 3 is a plan view showing an embodiment of the present invention, FIG. 4 is a sectional view taken along the line AA ′ in FIG. 3, and FIG. 5 is a sectional view taken along the line BB ′ in FIG. .
第３図に、InP系ダブルヘテロBH構造を有する分布帰還
型半導体レーザ（以下DFG型レーザと略称する）の主面
側に、本発明による電極構造を適用した一例を示す。結
晶の主面上には、SiO2からなる絶縁膜層30を全面に被着
したのち、活性層領域42の直上部に幅約10μｍの溝状窓
31が設けられている。次に、全面にCr,Auを連続蒸着し
て電極層を形成し、ついで、ホトレジスト技術を用いて
金属層を選択的にエツチング除去し、小面積のストライ
プ状（幅15μｍ）オーミツク電極32,リード電極33,34,
ボンディングパッド（80μｍ×80μｍ）35,36を形成し
た。FIG. 3 shows an example in which the electrode structure according to the present invention is applied to the main surface side of a distributed feedback semiconductor laser (hereinafter abbreviated as DFG type laser) having an InP-based double hetero BH structure. An insulating film layer 30 made of SiO 2 is deposited on the entire main surface of the crystal, and then a groove-shaped window having a width of about 10 μm is formed immediately above the active layer region 42.
31 is provided. Next, Cr and Au are continuously vapor-deposited on the entire surface to form an electrode layer, and then the metal layer is selectively etched and removed by using a photoresist technique to form a striped (15 μm wide) ohmic electrode 32 with a small area and a lead. Electrodes 33, 34,
Bonding pads (80 μm × 80 μm) 35 and 36 were formed.
次に、第４図，第５図により、素子のＡ−Ａ′断面,B−
Ｂ′断面の構造を説明する。ｎ型InP基板40の表面にピ
ツチ2300Å，深さ800Åの回折格子を形成し、その上
に、InGaAsPガイド層41（厚さ0.2〜0.4μｍ）、InGaAsP
活性層42（厚さ0.1〜0.2μｍ）、InGaAsPアンチメルト
バック層43（厚さ約0.1μｍ）、ｐ型InPクラツド層44
（厚さ３〜４μｍ）、ｐ−InGaAsP表面層45（厚さ約0.2
μｍ）が順次液相エピタキシヤル成長法により積層され
ている。ガイド層，活性層，アンチメルトバツク層，ク
ラツド層，表面層は、選択エツチングによるストライプ
状に構成されており、活性層の幅は約６μｍに調整され
ている。活性層42を含むストライプ状のメサ部分は、ｐ
−InP層46（厚さ0.8μｍ）,n−InP層47（厚さ２〜３μ
ｍ）,InGaAsP表面層48（厚さ0.2〜0.3μｍ）の液相エピ
タキシヤル成長層により埋込まれ、BH構造のDFB型レー
ザが構成されている。ｎ型InP基板には、AuGe−Ni−Au
からなるオーミツク電極49が形成されている。Next, referring to FIG. 4 and FIG.
The structure of the B ′ cross section will be described. A diffraction grating having a pitch of 2300Å and a depth of 800Å is formed on the surface of the n-type InP substrate 40, and an InGaAsP guide layer 41 (thickness 0.2 to 0.4 μm) and InGaAsP are formed on the diffraction grating.
Active layer 42 (thickness 0.1 to 0.2 μm), InGaAsP anti-melt back layer 43 (thickness about 0.1 μm), p-type InP cladding layer 44
(Thickness 3 to 4 μm), p-InGaAsP surface layer 45 (thickness about 0.2
μm) are sequentially laminated by the liquid phase epitaxial growth method. The guide layer, the active layer, the anti-melt back layer, the cladding layer, and the surface layer are formed in stripes by selective etching, and the width of the active layer is adjusted to about 6 μm. The stripe-shaped mesa portion including the active layer 42 is p
-InP layer 46 (thickness 0.8 μm), n-InP layer 47 (thickness 2-3 μm)
m), the InGaAsP surface layer 48 (having a thickness of 0.2 to 0.3 μm) is buried by a liquid phase epitaxial growth layer to construct a BH structure DFB type laser. AuGe-Ni-Au for n-type InP substrate
An ohmic electrode 49 composed of is formed.
以上述べたように、本実施例では、主面側のオーミツク
電極面積は、15μｍ×300μｍと大幅に減少しており、
ボンディングパッド部分を含む総合の静電容量は、従来
の電極構造に比べて約1/3に減少し、周波数特性が格段
に向上した。As described above, in this embodiment, the ohmic electrode area on the main surface side is significantly reduced to 15 μm × 300 μm,
The total capacitance, including the bonding pad, has been reduced to about 1/3 of the conventional electrode structure, and the frequency characteristics have been dramatically improved.
また、本実施例では、ボンディングパッドを２個設けて
あるので、一方を直流バイアス用、他方を高周波変調用
として用いることができる。Further, in this embodiment, since two bonding pads are provided, one can be used for DC bias and the other for high frequency modulation.
実施例２ 本発明の他の実施例を示すDFBレーザチツプの平面図を
第６図に示す。電極の製作方法は、実施例１と全く同様
であり、主面上の絶縁膜層60の活性領域直上部に溝状電
極窓61をあけ、この部分を包含するようにストライプ状
（幅15μｍ×長さ300μｍ）オーミツク電極62が設けら
ている。ストライプ状オーミツク電極62の中央部分から
は左右に２本のリード電極63,64が引出され、ボンディ
ングパッド65,66と接続している。リード電極64は、、
高周波に対してインダクタンスとして機能しするよう
に、蛇行パターンにしてある。ボンディングパッド66を
直流バイアス用、ボンディングパッド65を高周波変調用
として使用する。Embodiment 2 FIG. 6 is a plan view of a DFB laser chip showing another embodiment of the present invention. The method of manufacturing the electrodes is exactly the same as in Example 1, except that a groove-shaped electrode window 61 is opened in the insulating film layer 60 on the main surface immediately above the active region, and a stripe shape (width 15 μm × An ohmic electrode 62 having a length of 300 μm is provided. Two lead electrodes 63 and 64 are drawn out from the central portion of the striped ohmic electrode 62 to the left and right, and are connected to the bonding pads 65 and 66. The lead electrode 64 is
It has a meandering pattern so as to function as an inductance for high frequencies. The bonding pad 66 is used for DC bias, and the bonding pad 65 is used for high frequency modulation.
本実施例では、直流バイアス用リード電極がインダクタ
ンスとなるので、外部バイアス回路が従来方式に比較し
て簡単になる。In this embodiment, since the DC bias lead electrode serves as an inductance, the external bias circuit is simpler than the conventional method.
実施例３ 第７図は、本発明の第３の実施例である、DFB型レーザ
チツプの平面図を示す。第７図に示すDFB型レーザは、
活性領域を４個有するアレイ構造となつている。各々の
活性領域の直上部には、これを励起するためのストライ
プ状オーミツク電極72a,72b,72c,72dが形成されてい
る。（溝状電極窓の表示は省略した。）なお、電極など
の詳細な製作方法は、実施1,2と全く同様である。Embodiment 3 FIG. 7 shows a plan view of a DFB type laser chip which is a third embodiment of the present invention. The DFB type laser shown in FIG.
It has an array structure having four active regions. Striped ohmic electrodes 72a, 72b, 72c, 72d for exciting the active regions are formed immediately above the respective active regions. (The display of the groove-shaped electrode window is omitted.) The detailed manufacturing method of the electrodes and the like is exactly the same as in Embodiments 1 and 2.
また、オーミツク電極72a〜ｄからリード電極81,82,83,
84を引出し、各ボンディングパッドに接続した。ボンデ
ィングパッドは、各々のレーザ部分について、直流バイ
アス用、高周波変調用の各１個ずつが設けられている。In addition, the ohmic electrodes 72a to 72d to the lead electrodes 81, 82, 83,
84 was pulled out and connected to each bonding pad. For each laser portion, one bonding pad is provided for DC bias and one for high frequency modulation.
75a〜ｄは直流バイアス用のボンディングパッド、76a〜
ｄは高周波変調用のボンディングパッドである。なお、
リード電極やボンディングパッドを絶縁膜70上に設ける
方式などは実施例1,2と全く同様である。75a-d are bonding pads for DC bias, 76a-
Reference numeral d is a bonding pad for high frequency modulation. In addition,
The method of providing the lead electrode and the bonding pad on the insulating film 70 is exactly the same as in the first and second embodiments.
なお、本実施例では、ストライプ状オーミツク電極やリ
ード電極に選択的に厚さ数μｍのAuメツキを施し、直列
抵抗の低下を図つている。In this embodiment, the stripe ohmic electrode and the lead electrode are selectively plated with Au having a thickness of several μm to reduce the series resistance.
本実施例によれば、近接した複数個のストライプ状オー
ミツク電極からも容易に電極が引出され、低キヤパシタ
ンスの給電端子を設けることができる。According to this embodiment, the electrodes can be easily drawn out from a plurality of striped ohmic electrodes adjacent to each other, and a power supply terminal having a low capacitance can be provided.
本発明によれば、半導体レーザを構成するpn接合に設け
る電極面積を低減し、接合容量に起因する静電容量を大
幅に低減できるので、変調特性の改善に著しい効果があ
る。本発明による電極構造は、長距離光通用の光源とし
て最適と目されている、BH型DFBレーザ（Buried Heteco
stwctwe Type Distibuted Feedback Lasen）に適用した
場合、非常に効果的である。According to the present invention, the electrode area provided in the pn junction forming the semiconductor laser can be reduced, and the electrostatic capacitance due to the junction capacitance can be significantly reduced, so that the modulation characteristics are significantly improved. The electrode structure according to the present invention is considered to be optimal as a light source for long-distance light transmission, and is a BH type DFB laser (Buried Heteco).
It is very effective when applied to stwctwe Type Distibuted Feedback Lasen).
また、実施例では、主面上に設ける絶縁膜をSiO2で形成
した例を述べたが、誘電正接の小さい絶縁体であれば、
種々の材質が利用可能である。さらに、上記絶縁層の厚
さを増す程、ボンディングパッドやリード電極の寄生容
量を低減できるので、ポリイミド樹脂の厚膜絶縁層の利
用も可能である。In addition, in the embodiment, the example in which the insulating film provided on the main surface is formed of SiO 2 is described, but if the insulator has a small dielectric loss tangent,
Various materials are available. Further, as the thickness of the insulating layer is increased, the parasitic capacitance of the bonding pad and the lead electrode can be reduced, so that the thick film insulating layer of polyimide resin can be used.
さらに、ボンディングパッドの位置は、ストライプ状電
極の中央部に重ね合せるように配置することもできる。
また、本発明の電極構造の適用はDFBレーザに限定され
るものではない。Further, the position of the bonding pad can be arranged so as to overlap with the central portion of the striped electrode.
Further, the application of the electrode structure of the present invention is not limited to the DFB laser.
第１図は従来の半導体レーザの電極構造を示す斜視図、
第２図は本発明による電極構造の概念を示す斜視図、第
３図は本発明の一実施例を示す平面図、第４図，第５図
は、各々第３図のＡ−Ａ′,B−Ｂ′断面図、第６図は本
発明の他の実施例を示す平面図、第７図は本発明の第３
の実施例を示す平面図である。 12,32,66,72a〜ｄ……ストライプ状オーミック電極、1
6,33,34,63,64,81〜84……リード電極、17,35,36,65,6
6,75a〜d,76a〜ｄ……ボンディングパッド、20,30,60,7
0,……絶縁膜層。FIG. 1 is a perspective view showing an electrode structure of a conventional semiconductor laser,
FIG. 2 is a perspective view showing the concept of the electrode structure according to the present invention, FIG. 3 is a plan view showing an embodiment of the present invention, and FIGS. 4 and 5 are respectively AA ′ of FIG. FIG. 6 is a plan view showing another embodiment of the present invention, and FIG. 7 is a third view of the present invention.
It is a top view showing an example of. 12,32,66,72a ～ d …… Striped ohmic electrode, 1
6,33,34,63,64,81 to 84 ... Lead electrode, 17,35,36,65,6
6,75a-d, 76a-d ... Bonding pad, 20,30,60,7
0, ... Insulating film layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大石 昭夫 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 茅根 直樹 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 (56)参考文献 特開 昭59−51586（ＪＰ，Ａ) 特開 昭57−181244（ＪＰ，Ａ) 特開 昭59−151480（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akio Oishi 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Naoki Kane 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (56) Reference JP-A-59-51586 (JP, A) JP-A-57-181244 (JP, A) JP-A-59-151480 (JP, A)
Claims (4)
結晶の主面側の上記活性領域に対応した位置に設けられ
た上記活性領域幅以上で上記活性領域幅の15倍以下の範
囲の寸法幅を有するオーミック電極と、上記オーミック
電極に給電するために上記半導体結晶の主面側に設けら
れたリード電極と、上記リード電極に接続され上記半導
体結晶の主面側に設けられた外部接続用のリードワイヤ
を接続するためのボンディングパッドとを有することを
特徴とする半導体レーザ。1. A semiconductor crystal including an active region, and a size in a range not less than the active region width and not more than 15 times the active region width provided at a position corresponding to the active region on a main surface side of the semiconductor crystal. An ohmic electrode having a width, a lead electrode provided on the main surface side of the semiconductor crystal for supplying power to the ohmic electrode, and an external connection provided on the main surface side of the semiconductor crystal connected to the lead electrode. And a bonding pad for connecting the lead wire of the semiconductor laser.
少なくとも一方と上記半導体結晶の主面側との間に絶縁
膜層を有することを特徴とする特許請求の範囲第１項記
載の半導体レーザ。2. The semiconductor laser according to claim 1, further comprising an insulating film layer between at least one of the lead electrode and the bonding pad and the main surface side of the semiconductor crystal.
タンスを有するように蛇行パターンに形成されたことを
特徴とする特許請求の範囲第１項又は第２項記載の半導
体レーザ。3. The semiconductor laser according to claim 1, wherein the lead electrode is formed in a meandering pattern so as to have an inductance with respect to a high frequency.
を有する分布帰還型構造であることを特徴とする特許請
求の範囲第１項、第２項又は第３項記載の半導体レー
ザ。4. The semiconductor laser according to claim 1, 2, or 3, wherein the semiconductor crystal including the active region has a distributed feedback structure having a BH type structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59206237A JPH0680856B2 (en) | 1984-10-03 | 1984-10-03 | Semiconductor laser |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59206237A JPH0680856B2 (en) | 1984-10-03 | 1984-10-03 | Semiconductor laser |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18528495A Division JPH0851256A (en) | 1995-07-21 | 1995-07-21 | Semiconductor laser |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6184890A JPS6184890A (en) | 1986-04-30 |
| JPH0680856B2 true JPH0680856B2 (en) | 1994-10-12 |
Family
ID=16520016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59206237A Expired - Lifetime JPH0680856B2 (en) | 1984-10-03 | 1984-10-03 | Semiconductor laser |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680856B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2656490B2 (en) * | 1987-05-20 | 1997-09-24 | 株式会社日立製作所 | Semiconductor laser device |
| US4972238A (en) * | 1987-12-08 | 1990-11-20 | Kabushiki Kaisha Toshiba | Semiconductor laser device |
| JPH02164089A (en) * | 1988-12-19 | 1990-06-25 | Nec Corp | Semiconductor laser element |
| JP2819593B2 (en) * | 1989-03-10 | 1998-10-30 | 富士ゼロックス株式会社 | Multi-beam semiconductor laser device |
| JP5967749B2 (en) * | 2011-09-30 | 2016-08-10 | 国立大学法人京都大学 | Edge-emitting photonic crystal laser device |
| JP6512602B2 (en) * | 2014-06-02 | 2019-05-15 | 住友電工デバイス・イノベーション株式会社 | Semiconductor laser device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57181244A (en) * | 1981-04-30 | 1982-11-08 | Fujitsu Ltd | Semiconductor laser modulating circuit |
| JPS5951586A (en) * | 1982-09-17 | 1984-03-26 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS59151480A (en) * | 1983-02-17 | 1984-08-29 | Nec Corp | Driving circuit for laser diode |
-
1984
- 1984-10-03 JP JP59206237A patent/JPH0680856B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6184890A (en) | 1986-04-30 |
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