JPH01115174A - Light emitting diode array - Google Patents

Light emitting diode array

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Publication number
JPH01115174A
JPH01115174A JP62274048A JP27404887A JPH01115174A JP H01115174 A JPH01115174 A JP H01115174A JP 62274048 A JP62274048 A JP 62274048A JP 27404887 A JP27404887 A JP 27404887A JP H01115174 A JPH01115174 A JP H01115174A
Authority
JP
Japan
Prior art keywords
light emitting
electrodes
rows
emitting diode
diode array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62274048A
Other languages
Japanese (ja)
Inventor
Junji Hayashi
純司 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62274048A priority Critical patent/JPH01115174A/en
Publication of JPH01115174A publication Critical patent/JPH01115174A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent drop of optical output due to the heat generated during operation by plating an electrode located near the active layer which becomes a light emitting part. CONSTITUTION:The plating areas 9 of M-row are provided on the M-row electrodes 8 formed on the N-row circular MESA areas 6 of MXN circular MESA active layers 3, the MXN light guiding windows 11 are provided on a substrate 1 opposed to the active layers 3 and N-column stripe electrodes 10 are provided orthogonally crossing the M-row electrodes in the area except for the windows 11. Since the electrodes 8, 10 are striped and arranged crossing orthogonally on the (p) and (n) sides as described above, wirings to individual light emitting diodes can be eliminated and the electrodes 8, 10 are guided in the same number as the vertical and horizontal stripes. Thereby, wiring and bonding can be made easily and it becomes possible to provide a heat sink through the plated area 9, improving heat radiating effect. Accordingly, drop of light output level can be prevented.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は光通信装置、光情報処理装置等において光源と
して用いられる発光ダイオードアレイに関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a light emitting diode array used as a light source in optical communication devices, optical information processing devices, etc.

(従来の技術とその問題点) 従来の発光ダイオードアレイについては、例えばエレク
トロニクスレターズ(ELECTRONIC5LEIT
ER5) You、 23 No、 61987年28
4頁〜286頁に詳しい記述がある。
(Prior art and its problems) Regarding the conventional light emitting diode array, for example, see Electronics Letters (ELECTRONIC5LEIT).
ER5) You, 23 No. 61987 28
Detailed descriptions are available on pages 4 to 286.

一般に、発光ダイオードアレイでは数が多くなると比例
して発光時の発熱も大きくなるから、熱の放散をする必
要がある。単体の発光ダイオードではメッキやヒートシ
ンクを用いて放熱を良くしている。ところが、アレイで
は配線が複雑になり、ボンディングをとる数が多くかつ
難しくなるから、ヒートシンクをとりつける際の電極の
とり出し方が難しい6発光グイオードアレイには以上の
ような問題が本質的にある。そこで、従来の発光ダイオ
ードアレイでは放熱の対策がほとんどされておらず、動
作時に発熱のため光出力が低下する欠点があり実用上問
題となっていた。
Generally, as the number of light emitting diode arrays increases, the amount of heat generated during light emission also increases, so it is necessary to dissipate the heat. A single light emitting diode uses plating or a heat sink to improve heat dissipation. However, in an array, the wiring becomes complicated and the number of bondings to be made is large and difficult, making it difficult to take out the electrodes when attaching a heat sink.Six-emitting guide arrays inherently have the above problems. . Therefore, in conventional light emitting diode arrays, few measures have been taken to dissipate heat, and the drawback is that the light output decreases due to heat generation during operation, which has been a practical problem.

本発明の目的は、これらの欠点を除き動作時の発熱によ
る特性の劣化のない発光ダイオードアレイを提供するこ
とにある。
An object of the present invention is to eliminate these drawbacks and provide a light emitting diode array whose characteristics do not deteriorate due to heat generated during operation.

(問題点を解決するための手段) 前述の問題点を解決するために本発明が提供する発光ダ
イオードアレイは、半導体基板の第1の面に形成きれ、
MfrN列(M、Nは正の整数)に格子状に配列諮れた
、M×N個の円形メサ状の活性層を含む半導体層と、前
記M行の円形メサの上にそれぞれ形成されたM行の電極
と、これらM行の電極上に設けられたM行のメッキと、
前記半導体基板の表面であって前記第1の面に対面する
第2の面に、前記M×N個の円形メサ状の活性層に対向
して設けられたM×N個の光とり出し窓と、前記第2の
面に前記窓の部分を除いて設けられた、前記M行に直交
するN列のストライプ状電極とを有することを特徴とす
る。
(Means for Solving the Problems) In order to solve the above-mentioned problems, the light emitting diode array provided by the present invention can be formed on the first surface of a semiconductor substrate,
A semiconductor layer including M×N circular mesa-shaped active layers arranged in a lattice in MfrN columns (M and N are positive integers), and a semiconductor layer formed on the M rows of circular mesas, respectively. M rows of electrodes, M rows of plating provided on these M rows of electrodes,
M×N light extraction windows provided on a second surface of the semiconductor substrate facing the first surface, facing the M×N circular mesa-shaped active layers; and N columns of striped electrodes perpendicular to the M rows, which are provided on the second surface excluding the window portion.

(作用) 本発明の発光ダイオードアレイでは、発光部となる活性
層に近い電極部にメッキを設けることにより動作時に発
光部で発生する熱を速やかに放散させて光出力の低下を
なくした。このような放熱構造を可能にするために、本
発明においては、電極をp側とn側で直交するストライ
プ状にすることにより、個々の発光ダイオードへの配線
をなくし、電極のとり出しを縦、横のストライプの数だ
けにした。これによって配線及びボンディングが容易と
なり、実用的になった。更にこの方法によリメッキ部分
を介してヒートシンクをつけることが可能となり、放熱
の効果が一層向上した。これにより多数の発光ダイオー
ドを一度に動作させても光出力の低下がなくなった。こ
の方法では全ての発光ダイオードを独立に動作きせるこ
とはできないが必要に応じて行列(M行×N列)の数を
調節すればよい。
(Function) In the light emitting diode array of the present invention, by providing plating on the electrode portion close to the active layer serving as the light emitting portion, heat generated in the light emitting portion during operation is quickly dissipated, thereby eliminating a decrease in light output. In order to make such a heat dissipation structure possible, in the present invention, the electrodes are formed into stripes that are perpendicular to each other on the p-side and n-side, thereby eliminating the need for wiring to individual light emitting diodes and allowing the electrodes to be taken out vertically. , only the number of horizontal stripes. This makes wiring and bonding easier and more practical. Furthermore, this method made it possible to attach a heat sink through the replated part, further improving the heat dissipation effect. This eliminates the drop in light output even when a large number of light emitting diodes are operated at once. Although it is not possible to operate all the light emitting diodes independently in this method, the number of matrices (M rows×N columns) may be adjusted as necessary.

このように本発明の発光ダイオードアレイは、動作時の
発熱による光出力の低下を防ぐことができ、しかも配線
が容易にできる構造である。
As described above, the light emitting diode array of the present invention has a structure that can prevent a decrease in light output due to heat generation during operation, and can be easily wired.

(実施例) 次に本発明を、図面を参照して、より詳しく説明する。(Example) Next, the present invention will be explained in more detail with reference to the drawings.

第1図は本発明の一実施例の発光ダイオードアレイの断
面図で、同図(a)及び(b)は互いに90@の角度を
なす面における断面図である。第2図は第1図実施例の
発光ダイオードの平面図で、同図(a)は基板側からみ
た図であり、同図(b、)はメッキを形成した側からみ
た図である。
FIG. 1 is a sectional view of a light emitting diode array according to an embodiment of the present invention, and FIGS. 1(a) and 1(b) are sectional views taken along a plane making an angle of 90@ to each other. FIG. 2 is a plan view of the light emitting diode of the embodiment shown in FIG. 1, in which (a) is a view seen from the substrate side, and (b) is a view seen from the plated side.

また、第3図は第1図実施例の発光ダイオードアレイと
この発光ダイオードアレイが固M−aれるヒートシンク
との位置関係を示す平面図である。なお、第1図(a)
は第2ffl(b)のA−A’矢視断面図であり、第1
図(b)は第2図(b)のB−B゛矢視断面図である。
3 is a plan view showing the positional relationship between the light emitting diode array of the embodiment shown in FIG. 1 and a heat sink on which the light emitting diode array is fixed. In addition, Fig. 1(a)
is a sectional view taken along the line A-A' of the second ffl(b), and
FIG. 2(b) is a sectional view taken along the line B-B in FIG. 2(b).

本実施例の製作工程を第1図を参照して述べる。The manufacturing process of this example will be described with reference to FIG.

n型InPの基板1上に結晶成長によってn型InPバ
ッファ層2 、 InGaAsP活性層3(バンドギャ
ップに相当する波長1.37@) 、 p型InPクラ
ッド層4tp型InGaAsPコンタクト層5を順次に
形成する0次に通常のフォトレジスト法を用いてマスク
を形成した後、臭素メタールを含む混合液でエツチング
することにより、15行(M)XlS列(N)個の円形
メサ6を形成した0円形メサ6の直径は20PInでエ
ツチングはバッファ層2に達するまで行なった0行の間
隔および列の間隔はともに250)1fnとした6次に
窒化シリコンの絶縁膜7を形成した後、フォトレジスト
によって円形メサ6の上部のみ絶縁膜7を除去した0次
に15行(M)の幅10〇−のストライプ状のp型電極
8を円形メサ6の上部を含むように形成した。更にp型
電極8の上に約10−の厚さの金メッキ9を形成した。
An n-type InP buffer layer 2, an InGaAsP active layer 3 (wavelength 1.37 @ corresponding to the band gap), a p-type InP cladding layer, and a p-type InGaAsP contact layer 5 are sequentially formed on an n-type InP substrate 1 by crystal growth. Next, a mask is formed using a normal photoresist method, and then etched with a mixed solution containing bromine metal to form circular mesas 6 in 15 rows (M) and XlS columns (N). The diameter of the mesa 6 was 20PIn, and the etching was carried out until it reached the buffer layer 2.The spacing of the 0th row and the spacing of the columns were both 250) 1fn.6 Next, an insulating film 7 of silicon nitride was formed, and then a photoresist was used to form a circular pattern. The insulating film 7 was removed only on the upper part of the mesa 6, and a striped p-type electrode 8 of 15 rows (M) and a width of 100 was formed so as to include the upper part of the circular mesa 6. Further, on the p-type electrode 8, a gold plating 9 having a thickness of about 10 mm was formed.

このようにして第2図(b)の構造が得られた0次に基
板1側に前記15行(M)のストライプ状のp型電極8
及びメッキ9と直交する方向に15列(N)の幅150
−のストライプ状のn型電極10を形成した。
In this way, the structure shown in FIG. 2(b) was obtained.The 15 rows (M) of striped p-type electrodes 8 were formed on the substrate 1 side.
and a width of 150 in 15 rows (N) in the direction perpendicular to the plating 9.
- striped n-type electrodes 10 were formed.

n型電極10は円形メサ6に向かいあう位置に形成した
。その後、n型電極10の中に直径80Panの光とり
出し窓11を円形メサ6゛とほぼ対応する位置に形成し
た0次に光とり出し窓11の上に窒化シリコンの無反射
膜12を形成した。このようにして第1図および第2図
で示した本発明の実施例の発光ダイオードアレイが得ら
れた。
The n-type electrode 10 was formed at a position facing the circular mesa 6. After that, a light extraction window 11 with a diameter of 80 Pan was formed in the n-type electrode 10 at a position approximately corresponding to the circular mesa 6°, and a non-reflective film 12 of silicon nitride was formed on the zero-order light extraction window 11. did. In this way, the light emitting diode array of the embodiment of the present invention shown in FIGS. 1 and 2 was obtained.

次に、上述の実施例をヒートシンクに固着してなるヒー
トシンク固着発光ダイオードアレイについて第3図を参
照して説明する。第3図の発光ダイオードアレイは特許
請求範囲第2項に対応している。本図の発光ダイオード
アレイで用いる放熱用ヒートシンク31では、表面の一
部に250−の間隔で幅120−のストライプ状の融着
材32を形成し、その端部にボンディング用バッド33
を設けた。このヒートシンク31のストライプ状の融着
材32と第1図で示した発光ダイオードアレイ34のス
トライプ状のメッキ9がほぼ一致するように融着きせた
。このようにして、ヒートシンク固着発光ダイオードア
レイが得られた。
Next, a heat sink-fixed light emitting diode array formed by fixing the above-described embodiment to a heat sink will be described with reference to FIG. 3. The light emitting diode array of FIG. 3 corresponds to claim 2. In the heat sink 31 for heat dissipation used in the light emitting diode array shown in this figure, a stripe-like adhesive material 32 with a width of 120- is formed at intervals of 250- on a part of the surface, and bonding pads 33 are formed at the ends of the adhesive.
has been established. The striped welding material 32 of the heat sink 31 was fused so that the striped plating 9 of the light emitting diode array 34 shown in FIG. 1 almost coincided with each other. In this way, a heat sink-fixed light emitting diode array was obtained.

第1図に示した実施例による発光ダイオードアレイは、
発光部となる活性層3に近い電極8に金メッキ9を形成
することにより、発光ダイオードアレイの動作時に発生
する熱による光出力の低下をなくすことができた0例え
ば10行10列でなる100個の発光ダイオードを各々
100mAで直流動作させたとき光出力の低下は最も大
きいものでも1個だけ動作させた時と比べて2%以内で
あり、実用上問題はなかった。これは従来例の光出力の
低下の175と大幅な改善である。
The light emitting diode array according to the embodiment shown in FIG.
By forming gold plating 9 on the electrode 8 close to the active layer 3, which becomes the light emitting part, it is possible to eliminate the reduction in light output due to the heat generated during the operation of the light emitting diode array. When each of the light emitting diodes was operated with a direct current of 100 mA, the largest drop in optical output was within 2% compared to when only one light emitting diode was operated, and there was no problem in practical use. This is a significant improvement over the reduction in optical output of the conventional example by 175 points.

またヒートシンク31を金メッキ9に融着した第3図の
ものでは10行10列からなる100個の発光ダイオー
ドを各々1oot!IAで直流動作させたときは、1個
だけ動作許せたときと比べて光出力の低下は見られず良
好な結果が得られた。また200mAで同様の動作を行
なっても光出力の低下は見られなかった。さらにヒート
シンク31上にポンディングパッド33を形成したので
配線が容易となり歩留りも向上した。
In addition, in the one shown in FIG. 3 in which the heat sink 31 is fused to the gold plating 9, 100 light emitting diodes arranged in 10 rows and 10 columns are each 1 oot! When DC operation was performed using IA, good results were obtained with no decrease in optical output compared to when only one element was allowed to operate. Further, even when the same operation was performed at 200 mA, no decrease in optical output was observed. Furthermore, since the bonding pad 33 was formed on the heat sink 31, wiring became easy and the yield was improved.

以上に本発明について実施例を挙げて説明した。The present invention has been described above with reference to examples.

上述の実施例ではInP/ InGaAsPを材料とし
て用いたが、本発明では他のlll−4族、II−VI
族を材料として用いてもよい、また導電型のp型、n型
を実施例とは反転しても同様の効果がある。
In the above embodiment, InP/InGaAsP was used as the material, but in the present invention, other materials of Ill-4 group, II-VI
The same effect can be obtained even if the conductivity types of p-type and n-type are reversed from those in the embodiment.

(発明の効果) 以上に説明したように、本発明によれば、従来のものと
比べ発熱による光出力の低下のない良好な発光ダイオー
ドアレイが得られた。またp側とn側で直交するストラ
イプ状の電極を用いることにより、配線、ボンディング
等が容易になり実用的になった。
(Effects of the Invention) As described above, according to the present invention, a good light emitting diode array was obtained in which the light output did not decrease due to heat generation compared to the conventional one. Furthermore, by using striped electrodes that are perpendicular to each other on the p-side and n-side, wiring, bonding, etc. are made easier and more practical.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の発光ダイオードアレイの断
面図で、同図(a)及び(b)は互いに90°の角度を
なす面の構造を示す、第2図は第1図実施例の発光ダイ
オードの平面図で、同図(a)は基板側からみた図、同
図(b)はメッキ゛を形成した側からみた図である。第
3図は第1図実施例の発光ダイオードアレイとこの発光
ダイオードアレイが固着されるヒートシンクとの位置関
係を示す平面図である。 1・・・基板、2・・・バッファ層、3・・・活性層、
4・・・クラッド層゛、5・・・コンタクト層、6・・
・円形メサ、7・・・絶縁膜、8,10・・・電極、9
・・・メッキ、11・・・光とり出し窓、12・・・無
反射膜、31・・・ヒートシンク、32・・・融着材、
33・・・ポンディング用パッド、34・・・発光ダイ
オードアレイ。
FIG. 1 is a cross-sectional view of a light emitting diode array according to an embodiment of the present invention, and FIGS. These are plan views of an example light emitting diode, in which (a) is a view seen from the substrate side, and (b) is a view seen from the side on which plating is formed. FIG. 3 is a plan view showing the positional relationship between the light emitting diode array of the embodiment shown in FIG. 1 and a heat sink to which the light emitting diode array is fixed. 1... Substrate, 2... Buffer layer, 3... Active layer,
4... cladding layer, 5... contact layer, 6...
・Circular mesa, 7... Insulating film, 8, 10... Electrode, 9
... Plating, 11 ... Light extraction window, 12 ... Non-reflection film, 31 ... Heat sink, 32 ... Fusion material,
33...Pounding pad, 34...Light emitting diode array.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板の第1の面に形成され、M行N列(M
、Nは正の整数)に格子状に配列された、M×N個の円
形メサ状の活性層を含む半導体層と、 前記M行の円形メサの上にそれぞれ形成されたM行の電
極と、 これらM行の電極上に設けられたM行のメッキと、 前記半導体基板の表面であって前記第1の面に対面する
第2の面に、前記M×N個の円形メサ状の活性層に対向
して設けられたM×N個の光とり出し窓と、 前記第2の面に前記窓の部分を除いて設けられた、前記
M行に直交するN列のストライプ状電極とを有すること
を特徴とする発光ダイオードアレイ。
(1) Formed on the first surface of a semiconductor substrate, M rows and N columns (M
, N is a positive integer), a semiconductor layer including M×N circular mesa-shaped active layers arranged in a lattice pattern; and M rows of electrodes formed on the M rows of circular mesas, respectively. , M rows of plating provided on these M rows of electrodes, and the M×N circular mesa-shaped active layers on a second surface of the semiconductor substrate facing the first surface. M×N light extraction windows provided facing the layer; and N columns of striped electrodes perpendicular to the M rows provided on the second surface excluding the window portions. A light emitting diode array comprising:
(2)前記M行のメッキの部分が融着材を介して当接す
る放熱用ヒートシンクが設けられ、前記融着材は前記M
行のメッキに対応する形のM行のストライプ状であり、
前記融着材の端部にボンディングパッドが接続して設け
られていることを特徴とする特許請求の範囲第1項記載
の発光ダイオードアレイ。
(2) A heat sink for heat dissipation is provided, with which the plated portions of the M rows come into contact with each other via a fusing material, and the fusing material is
It has an M row stripe shape corresponding to the row plating,
2. The light emitting diode array according to claim 1, further comprising a bonding pad connected to an end of said fusing material.
JP62274048A 1987-10-28 1987-10-28 Light emitting diode array Pending JPH01115174A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62274048A JPH01115174A (en) 1987-10-28 1987-10-28 Light emitting diode array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62274048A JPH01115174A (en) 1987-10-28 1987-10-28 Light emitting diode array

Publications (1)

Publication Number Publication Date
JPH01115174A true JPH01115174A (en) 1989-05-08

Family

ID=17536242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62274048A Pending JPH01115174A (en) 1987-10-28 1987-10-28 Light emitting diode array

Country Status (1)

Country Link
JP (1) JPH01115174A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007019511A (en) * 2005-07-05 2007-01-25 Lg Electronics Inc Light emitting element and its manufacturing method
WO2007126093A1 (en) * 2006-05-01 2007-11-08 Mitsubishi Chemical Corporation Integrated semiconductor light-emitting device and its manufacturing method
WO2007126092A1 (en) * 2006-05-01 2007-11-08 Mitsubishi Chemical Corporation Integrated semiconductor light emitting device and method for manufacturing same
WO2007126094A1 (en) * 2006-05-02 2007-11-08 Mitsubishi Chemical Corporation Semiconductor light-emitting device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007019511A (en) * 2005-07-05 2007-01-25 Lg Electronics Inc Light emitting element and its manufacturing method
WO2007126093A1 (en) * 2006-05-01 2007-11-08 Mitsubishi Chemical Corporation Integrated semiconductor light-emitting device and its manufacturing method
WO2007126092A1 (en) * 2006-05-01 2007-11-08 Mitsubishi Chemical Corporation Integrated semiconductor light emitting device and method for manufacturing same
US8581274B2 (en) 2006-05-01 2013-11-12 Mitsubishi Chemical Corporation Integrated semiconductor light-emitting device and its manufacturing method
WO2007126094A1 (en) * 2006-05-02 2007-11-08 Mitsubishi Chemical Corporation Semiconductor light-emitting device

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