JPH0680683B2 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistorInfo
- Publication number
- JPH0680683B2 JPH0680683B2 JP26026885A JP26026885A JPH0680683B2 JP H0680683 B2 JPH0680683 B2 JP H0680683B2 JP 26026885 A JP26026885 A JP 26026885A JP 26026885 A JP26026885 A JP 26026885A JP H0680683 B2 JPH0680683 B2 JP H0680683B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- resist mask
- light
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010408 film Substances 0.000 claims description 93
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims 1
- 239000011229 interlayer Substances 0.000 description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Description
【発明の詳細な説明】 〔概要〕 ゲート領域に外乱光が入射することを防止する遮光膜を
有する逆スタガード型薄膜トランジスタの製造方法の改
良である。特に、ソース・ドレイン電極と遮光膜との間
の静電容量を減少する改良である。DETAILED DESCRIPTION OF THE INVENTION [Outline] It is an improvement of a method of manufacturing an inverted staggered thin film transistor having a light shielding film for preventing disturbance light from entering a gate region. In particular, it is an improvement to reduce the electrostatic capacitance between the source / drain electrodes and the light shielding film.
ガラス基板側からゲート電極をマスクとして露光して、
ゲート電極と反対形状のソース電極・ドレイン電極を形
成してゲート電極とソース電極・ドレイン電極との間の
静電容量を減少する利益を有する逆スタガード型薄膜ト
ランジスタの製造方法の特徴を、遮光膜の形成工程にも
拡張したものであり、その結果、ソース電極・ドレイン
電極と遮光膜との間の静電容量を減少し、動作速度を向
上したものである。Light exposure from the glass substrate side using the gate electrode as a mask,
The characteristics of the method of manufacturing an inverted staggered thin film transistor, which has the advantage of forming a source electrode / drain electrode having a shape opposite to the gate electrode to reduce the capacitance between the gate electrode and the source electrode / drain electrode, This is also an extension to the forming process, and as a result, the capacitance between the source / drain electrodes and the light shielding film is reduced, and the operating speed is improved.
本発明は、ゲート領域に外乱光が入射することを防止す
る遮光膜を有する逆スタガード型薄膜トランジスタの製
造方法の改良に関する。特に、ソース・ドレイン電極と
遮光膜との間の静電容量を減少し、動作速度を向上する
改良に関する。The present invention relates to an improvement in a method of manufacturing an inverted staggered thin film transistor having a light shielding film that prevents ambient light from entering a gate region. In particular, the present invention relates to an improvement in which the capacitance between the source / drain electrodes and the light shielding film is reduced and the operating speed is improved.
逆スタガード型薄膜トランジスタの遮光膜を形成するに
は、従来、逆スタガード型薄膜トランジスタを形成する
工程の最終段階において、マスク合わせ技術を使用して
なす通常のエッチング法またはリフトオフ法を使用し
て、ゲート電極に対応する領域に不透光性導電膜を形成
していた。In order to form a light-shielding film of an inverted staggered thin film transistor, a gate electrode is conventionally formed by using an ordinary etching method or a lift-off method using a mask alignment technique at the final stage of the step of forming the inverted staggered thin film transistor. The opaque conductive film was formed in the region corresponding to.
従来技術においては、上記せるとおり、マスク合わせ技
術を使用していたので、遮光膜とソース・ドレイン電極
との重なりが避け難く、これらの間に静電容量が発生
し、薄膜トランジスタの動作速度が遅くなるという欠点
があった。In the conventional technology, as described above, since the mask alignment technology is used, it is unavoidable that the light-shielding film and the source / drain electrodes overlap with each other, and electrostatic capacitance is generated between them, so that the operation speed of the thin film transistor is slow. There was a drawback that
本発明の目的はこの欠点を解消することにあり、遮光膜
とソース・ドレイン電極との間の静電容量が少なく、動
作速度が向上している逆スタガード型薄膜トランジスタ
の製造方法を提供することにある。An object of the present invention is to eliminate this drawback, and to provide a method for manufacturing an inverted staggered thin film transistor in which the capacitance between the light-shielding film and the source / drain electrodes is small and the operating speed is improved. is there.
上記の目的を達成するために本発明が採った手段は、 （イ）透光性絶縁物基板１上に不透光性ゲート電極２を
形成し、ゲート絶縁膜３を形成し、動作層４を形成し、
チャンネル保護用絶縁膜５を形成した後、ポジ型レジス
ト膜６を形成し、このポジ型レジスト膜６を前記の透光
性絶縁物基板１側から露光して前記のゲート電極２と同
一形状の第１のレジストマスク61を形成し、さらに、ソ
ース・ドレイン電極用透光性導電膜７を形成し、前記の
第１のレジストマスク61を除去してこのソース・ドレイ
ン電極用透光性導電膜７を前記のゲート電極２に対向す
る領域からリフトオフした後、 （ロ）層間絶縁膜用透光性絶縁膜８を形成し、ネガ型レ
ジスト膜９を形成し、このネガ型レジスト膜９を、再
び、前記の透光性絶縁物基板１側から露光して前記のゲ
ート電極２と対向する領域に開口を有する第２のレジス
トマスク91を形成した後、透光膜用不透光性導電膜10を
形成し、前記の第２のレジストマスク91を除去して前記
の遮光膜用不透光性導電膜10を前記のゲート電極２と対
向する領域のみに残留して遮光膜11を形成し、 （ハ）その後、ゲート領域とソース・ドレイン領域とを
覆う第３のレジストマスク12を形成し、この第３のレジ
ストマスク12を使用してソース・ドレイン分離をなし
て、薄膜トランジスタを製造することとしたことにあ
る。Means adopted by the present invention to achieve the above object are as follows: (a) A non-translucent gate electrode 2 is formed on a transparent insulator substrate 1, a gate insulating film 3 is formed, and an operating layer 4 is formed. To form
After forming the channel protection insulating film 5, a positive type resist film 6 is formed, and the positive type resist film 6 is exposed from the side of the transparent insulating substrate 1 to form the same shape as the gate electrode 2. The first resist mask 61 is formed, the source / drain electrode translucent conductive film 7 is further formed, and the first resist mask 61 is removed to obtain the source / drain electrode translucent conductive film. After lifting off 7 from the region facing the gate electrode 2, (b) a translucent insulating film 8 for an interlayer insulating film is formed, a negative resist film 9 is formed, and the negative resist film 9 is After exposing again from the transparent insulating substrate 1 side to form a second resist mask 91 having an opening in a region facing the gate electrode 2, a non-transparent conductive film for a transparent film is formed. 10 is formed, and the second resist mask 91 is removed. To form the light-shielding film 11 by leaving the non-transparent conductive film for light-shielding film 10 only in a region facing the gate electrode 2, and (c) thereafter, covering the gate region and the source / drain regions. The third resist mask 12 is formed, and the third resist mask 12 is used to perform source / drain separation to manufacture a thin film transistor.
逆スタガード型薄膜トランジスタの製造方法の特徴は、
ガラス基板側からゲート電極をマスクとして露光して、
ゲート電極と反対形状のソース電極・ドレイン電極を形
成してゲート電極とソース電極・ドレイン電極との間の
静電容量を減少することにある。The features of the manufacturing method of the inverted staggered thin film transistor are:
Light exposure from the glass substrate side using the gate electrode as a mask,
The purpose is to reduce the capacitance between the gate electrode and the source / drain electrode by forming a source / drain electrode having a shape opposite to the gate electrode.
もし、ソース電極・ドレイン電極をITO等透光性導電膜
をもって形成すれば、上記の技術を遮光膜の形成にも拡
張しうる。If the source electrode / drain electrode is formed of a transparent conductive film such as ITO, the above technique can be extended to the formation of a light shielding film.
本発明は、この着想を具体化して完成したものであり、
逆スタガード型薄膜トランジスタの技術を使用して、ソ
ース・ドレイン電極用透光性導電膜７をゲート電極２に
対向する領域からリフトオフした後、層間絶縁膜８を介
してネガ型レジスト９を形成し、これを上記と同様に、
基板側から露光したゲート電極２に対向する領域に開口
を有するレジストマスク91（第２のレジストマスク）を
形成し、この上に遮光膜用不透光性導電膜10を形成し、
上記の第２のレジストマスク91を使用して遮光膜用不透
光性導電膜10をゲート電極に対向する領域以外から除去
すると、ゲート電極２・ソース電極13・ドレイン電極14
・遮光膜11が自己整合的に形成され、相互の重なりがな
く、静電容量が減少し、薄膜トランジスタの動作特性が
向上する。その後、従来技術と同様にしてソース・ドレ
イン分離をなす。The present invention has been completed by embodying this idea,
Using the technique of the inverted staggered thin film transistor, the light-transmissive conductive film 7 for source / drain electrodes is lifted off from the region facing the gate electrode 2, and then the negative resist 9 is formed via the interlayer insulating film 8. This is the same as above,
A resist mask 91 (second resist mask) having an opening in a region facing the gate electrode 2 exposed from the substrate side is formed, and a non-translucent conductive film 10 for a light shielding film is formed thereon.
When the light-shielding non-transmissive conductive film 10 is removed from a region other than the region facing the gate electrode using the second resist mask 91, the gate electrode 2, the source electrode 13, and the drain electrode 14 are removed.
The light-shielding film 11 is formed in a self-aligned manner, does not overlap each other, the capacitance is reduced, and the operating characteristics of the thin film transistor are improved. After that, the source and drain are separated in the same manner as in the prior art.
以下、図面を参照しつゝ、本発明の一実施例に係る薄膜
トランジスタの製造方法についてさらに説明する。Hereinafter, a method of manufacturing a thin film transistor according to an embodiment of the present invention will be further described with reference to the drawings.
第２図参照 ガラス板等透光性絶縁物基板１上にクロム膜等を形成
し、これをパターニングしてゲート電極２を形成する。See FIG. 2. A chrome film or the like is formed on a transparent insulating substrate 1 such as a glass plate, and this is patterned to form a gate electrode 2.
つゞいて、プラズマCVD法を使用して、窒化シリコン膜
等よりなるゲート絶縁膜３と水素化アモルファスシリコ
ン等よりなる動作層４と二酸化シリコン等よりなるチャ
ンネル保護用絶縁膜５とをつゞけて形成する。Then, using the plasma CVD method, the gate insulating film 3 made of a silicon nitride film and the like, the operating layer 4 made of hydrogenated amorphous silicon and the like and the channel protection insulating film 5 made of silicon dioxide and the like are attached. To form.
その上にポジ型レジスト膜６を形成する。A positive resist film 6 is formed thereon.
第３図参照 透光性絶縁物基板１の側から、ゲート電極２をマスクと
して露光した後現像して、ゲート電極２と同一形状の第
１のレジストマスク61を形成する。See FIG. 3. From the side of the transparent insulating substrate 1, the gate electrode 2 is used as a mask for exposure and then development is performed to form a first resist mask 61 having the same shape as the gate electrode 2.
第４図参照 第１のレジストマスク61を使用して、チャンネル保護用
絶縁膜５をソース・ドレイン領域から除去する。See FIG. 4. Using the first resist mask 61, the channel protection insulating film 5 is removed from the source / drain regions.
つゞいて、ｎ型水素化アモルファスシリコン膜71とソー
ス電極・ドレイン電極用ITO膜７とをつゞけて形成す
る。Then, the n-type hydrogenated amorphous silicon film 71 and the ITO film 7 for source / drain electrodes are formed together.
第５図参照 第１のレジストマスク61を除去して、上記のｎ型水素化
アモルファスシリコン膜71とソース電極・ドレイン電極
用ITO膜７とをゲート電極２に対応する領域から除去す
る。See FIG. 5. The first resist mask 61 is removed, and the n-type hydrogenated amorphous silicon film 71 and the source / drain electrode ITO film 7 are removed from the region corresponding to the gate electrode 2.
第６図参照 層間絶縁膜用の透光性絶縁膜としてのポリイミド膜８を
厚さ１μｍに形成する。See FIG. 6. A polyimide film 8 as a translucent insulating film for an interlayer insulating film is formed to a thickness of 1 μm.
ネガ型レジスト膜を形成し、基板１側から露光して、ゲ
ート電極２と対向する領域に開口を有する第２のレジス
トマスク91を形成する。A negative resist film is formed and exposed from the substrate 1 side to form a second resist mask 91 having an opening in a region facing the gate electrode 2.
遮光膜用の不透光性導電膜としてクローム膜10を形成す
る。A chrome film 10 is formed as an opaque conductive film for a light shielding film.
第７図参照 第２のレジストマスク91を除去して、遮光膜用の不透光
性導電膜としてのクローム膜10をゲート電極２と対応す
る領域のみに残留してこれを遮光膜11とする。Referring to FIG. 7, the second resist mask 91 is removed, and the chrome film 10 as an opaque conductive film for the light-shielding film remains only in the region corresponding to the gate electrode 2 and is used as the light-shielding film 11. .
第８図参照 ゲート領域とソース・ドレイン領域とを覆う第３のレジ
ストマスク12を形成し、これを使用して、ポリイミド膜
８、ITO膜７、ｎ型水素化アモルファスシリコン膜71、
動作層４、所望によってはゲート絶縁膜３を除去して、
ソース・ドレイン分離をなし、ソース電極13とドレイン
電極14とを形成する。See FIG. 8. A third resist mask 12 is formed to cover the gate region and the source / drain regions, and using this, a polyimide film 8, an ITO film 7, an n-type hydrogenated amorphous silicon film 71,
Removing the operating layer 4, and optionally the gate insulating film 3,
Source and drain are separated to form a source electrode 13 and a drain electrode 14.
第１図参照 第３のレジストマスク12を除去する。See FIG. 1. The third resist mask 12 is removed.
以上の工程においては、ソース電極13・ドレイン電極14
と遮光膜11とは、ゲート電極２をマスクとして自己整合
的に形成されているので、これら相互の重なりはなく、
ソース電極13・ドレイン電極14と遮光膜11との間の静電
容量は極めて小さく、薄膜トランジスタの動作速度は向
上している。In the above process, the source electrode 13 and the drain electrode 14
Since the light-shielding film 11 and the light-shielding film 11 are formed in a self-aligned manner using the gate electrode 2 as a mask, they do not overlap each other,
The electrostatic capacitance between the source electrode 13 / drain electrode 14 and the light shielding film 11 is extremely small, and the operation speed of the thin film transistor is improved.
以上説明せるとおり、本発明に係る薄膜トランジスタの
製造方法においては、逆スタガード型薄膜トランジスタ
の技術を使用して、ソース・ドレイン電極用透光性導電
膜をゲート電極に対向する領域からリフトオフした後、
層間絶縁膜を介してネガ型レジストを形成し、これを上
記と同様に、基板側から露光してゲート電極に対向する
領域に開口を有するレジストマスク（第２のレジストマ
スク）を形成し、この上に遮光膜用不透光性導電膜を形
成し、上記の第２のレジストマスクを使用して遮光膜用
不透光性導電膜をゲート電極に対向する領域以外から除
去して遮光膜を形成することとされているので（ゲート
電極・ソース電極・ドレイン電極・遮光膜とが自己整合
的に形成されているので）、遮光膜とソース電極・ドレ
イン電極との重なりがなく、静電容量が減少し、薄膜ト
ランジスタの動作特性が向上している。As described above, in the method of manufacturing a thin film transistor according to the present invention, using the technique of the inverted staggered thin film transistor, after the source / drain electrode translucent conductive film is lifted off from the region facing the gate electrode,
A negative resist is formed via an interlayer insulating film, and this is exposed from the substrate side in the same manner as above to form a resist mask (second resist mask) having an opening in a region facing the gate electrode. An opaque conductive film for a light-shielding film is formed on the light-shielding film, and the opaque conductive film for a light-shielding film is removed from a region other than the region facing the gate electrode by using the second resist mask to remove the light-shielding film. Since it is supposed to be formed (since the gate electrode, the source electrode, the drain electrode, and the light-shielding film are formed in a self-aligned manner), there is no overlap between the light-shielding film and the source electrode / drain electrode, and the capacitance And the operating characteristics of the thin film transistor are improved.
第１図は、本発明の一実施例に係る薄膜トランジスタの
製造方法を実施して製造した薄膜トランジスタの断面図
である。 第２〜８図は、本発明の一実施例に係る薄膜トランジス
タの製造方法の主要工程完了後の断面図である。 １……透光性基板（ガラス板）、２……ゲート電極、３
……ゲート絶縁膜、４……動作層、５……チャンネル保
護用絶縁膜、６……ホジ型レジスト膜、61……第１のレ
ジストマスク、７……透光性導電膜（ソース・ドレイン
電極用ITO膜）、８……透光性絶縁膜（層間絶縁膜用ポ
リイミド膜）、９……ネガ型レジスト膜、91……第２の
レジストマスク、10……不透光性導電膜（遮光膜用クロ
ーム膜）、11……遮光膜、12……第３のレジストマス
ク、13……ソース電極、14……ドレイン電極。FIG. 1 is a cross-sectional view of a thin film transistor manufactured by performing a method of manufacturing a thin film transistor according to an embodiment of the present invention. 2 to 8 are cross-sectional views after completion of main steps of the method of manufacturing a thin film transistor according to the embodiment of the present invention. 1 ... Translucent substrate (glass plate), 2 ... Gate electrode, 3
...... Gate insulating film, 4 ...... Operating layer, 5 ...... Channel protective insulating film, 6 ...... Hosi type resist film, 61 ...... First resist mask, 7 ...... Translucent conductive film (source / drain) ITO film for electrodes), 8 ... Translucent insulating film (polyimide film for interlayer insulating film), 9 ... Negative resist film, 91 ... Second resist mask, 10 ... Translucent conductive film ( Chrome film for light-shielding film), 11 ... Light-shielding film, 12 ... Third resist mask, 13 ... Source electrode, 14 ... Drain electrode.
Claims (1)
ト電極（２）を形成し、 ゲート絶縁膜（３）を形成し、 動作層（４）を形成し、 チャンネル保護用絶縁膜（５）を形成し、 ポジ型レジスト膜（６）を形成し、該ポジ型レジスト膜
（６）を前記透光性絶縁物基板（１）側から露光して前
記ゲート電極（２）と同一形状の第１のレジストマスク
（61）を形成し、 透光性導電膜（７）を形成し、 前記第１のレジストマスク（61）を除去して前記透光性
導電膜（７）を前記ゲート電極（２）に対向する領域か
ら除去し、 透光性絶縁膜（８）を形成し、 ネガ型レジスト膜（９）を形成し、該ネガ型レジスト膜
（９）を前記透光性絶縁物基板（１）側から露光して前
記ゲート電極（２）と対向する領域に開口を有する第２
のレジストマスク（91）を形成し、 不透光性導電膜（10）を形成し、 前記第２のレジストマスク（91）を除去して前記不透光
性導電膜（10）を前記ゲート電極（２）と対向する領域
に残留して遮光膜（11）を形成し、 ゲート領域とソース・ドレイン領域とを覆う第３のレジ
ストマスク（12）を形成し、該第３のレジストマスク
（12）を使用してソース・ドレイン分離をなすことを特
徴とする薄膜トランジスタの製造方法。1. A non-transparent gate electrode (2) is formed on a transparent insulating substrate (1), a gate insulating film (3) is formed, an operating layer (4) is formed, and channel protection is performed. Forming an insulating film (5) for forming a positive resist film (6), exposing the positive resist film (6) from the side of the transparent insulating substrate (1), and exposing the gate electrode (2). ), A first resist mask (61) having the same shape as that of (1) is formed, a transparent conductive film (7) is formed, and the first resist mask (61) is removed to remove the transparent conductive film (7). ) Is removed from a region facing the gate electrode (2), a light-transmissive insulating film (8) is formed, a negative resist film (9) is formed, and the negative resist film (9) is formed on the transparent film. A second opening which is exposed from the side of the optical insulator substrate (1) and has an opening in a region facing the gate electrode (2);
Resist mask (91) is formed, an opaque conductive film (10) is formed, the second resist mask (91) is removed, and the opaque conductive film (10) is removed from the gate electrode. A light-shielding film (11) is formed in a region opposite to (2), a third resist mask (12) covering the gate region and the source / drain regions is formed, and the third resist mask (12) is formed. ) Is used for source / drain separation, and a method for manufacturing a thin film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26026885A JPH0680683B2 (en) | 1985-11-20 | 1985-11-20 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26026885A JPH0680683B2 (en) | 1985-11-20 | 1985-11-20 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62120075A JPS62120075A (en) | 1987-06-01 |
| JPH0680683B2 true JPH0680683B2 (en) | 1994-10-12 |
Family
ID=17345693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26026885A Expired - Lifetime JPH0680683B2 (en) | 1985-11-20 | 1985-11-20 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680683B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107641A (en) * | 1997-09-10 | 2000-08-22 | Xerox Corporation | Thin film transistor with reduced parasitic capacitance and reduced feed-through voltage |
-
1985
- 1985-11-20 JP JP26026885A patent/JPH0680683B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62120075A (en) | 1987-06-01 |
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