JPH0679430B2 - VTR data recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a VTR in which a duty cycle of a control pulse having a constant cycle is varied in accordance with position information of a magnetic tape or data relating to a special function to record on a control track. The present invention relates to a data recording device.

[Prior Art] Conventionally, the duty cycle of the control pulse (CTL pulse) is made variable and recorded on the control track according to the data on the position information and arbitrary comment information of the magnetic tape used in the home VTR, and this is reproduced. There is a VTR data recording / reproducing apparatus based on the so-called CTL coding system, which is configured to display and to allow random access.

In such a VTR data recording / reproducing apparatus, a plurality of types of data are appropriately selected and recorded on the control track of the magnetic tape for reproduction, so that the absolute position from the recording start portion on the magnetic tape is pulsed. It can be configured at a lower cost than a VTR that records and reproduces SMPTE time code recorded on another track, and can freely record arbitrary information by extremely simple operation, and random access is also possible, which is rich in variety. It has excellent features such as being usable.

[Problems to be Solved by the Invention] However, the control pulse has one frame period (1/30
The data transmission bit rate is extremely low at 30 bits / second, and the method of recording data by changing the duty cycle of the control pulse is very low. When recording a code that constitutes one data block, it takes several seconds to record / reproduce one block data.

Therefore, when the time code is recorded by CTL coding as described above, since 1 bit is recorded per frame in the CTL coding system, one frame per frame is recorded.
Similar to 80-bit SMPTE time code, it is not possible to record the code format as it is, and the address code is treated as time data and recorded on the tape at regular intervals (for example, every 1 minute). The frame counter is reset at the position where
It is necessary to count the L pulses and manage the frame. However, there is a problem that the position where the code can be read is displaced when even one data in the address code is lost, and in the case of NTSC color signal, the number of frames is nominally 29.97 frames / sec. However, there is a problem in that the time code cannot be said to be small. Therefore, if skipping data (frame number 00.01) indicating a predetermined time in a certain cycle like correction of SMPTE time code is applied to CTL coding, one data block length of CTL coding extends for several seconds. Therefore, correction cannot be made unless such a time lag occurs, which is not preferable for real-time management.

Therefore, the present invention has been made in order to solve the above-mentioned problems, and when recording a time code by the CTL coding method, it is possible to achieve a match with a real time VTR.
It is an object of the present invention to provide a data recording device of.

[Means for Solving the Problems] In a VTR data recording apparatus according to the present invention, when recording a time code by a CTL coding method, a dummy bit is added to the rear part of a data block, and the number of dummy bits is set at a constant cycle. The data block is recorded on the control track of the magnetic tape, and a bit having a fixed positional relationship with the head bit of the data block is used as a discrimination bit indicating the number of bits of the dummy bit. Is provided.

That is, according to the present invention, one of a plurality of types of data including the position information of the magnetic tape on which the video signal is recorded and reproduced by the VTR is appropriately selected, and the duty of the control pulse having a constant cycle is selected according to the value of the selected data. In a VTR data recording device for controlling a cycle to record on a control track of the magnetic tape, means for adding a dummy bit to the rear portion of a data block having time code data consisting of the control pulse, and the dummy bit at a constant cycle. Device for changing the number of bits of the VTR, and means for making a bit having a fixed positional relationship with the first bit of the data block a discrimination bit indicating the number of bits of the dummy bit. Will be provided.

[Operation] According to the data recording device of the VTR of the present invention, dummy bits are provided at the rear of the data block and the number of dummy bits is changed at a constant period, so that the data content in the time code data is not skipped. Since it is possible to correct the time shift of the time code, a bit having a fixed positional relationship with the first bit of the data block is provided as a discrimination bit indicating the number of dummy bits, so that at the time of reproduction, By recognizing this discrimination bit, the number of dummy bits can be known.

[Embodiment] An embodiment of a VTR data recording apparatus of the present invention will be described in detail below with reference to the drawings.

In the present invention, in order to correct the time shift of the time code due to CTL coding, dummy bits are provided in the code to be recorded, and the number of dummy bits is changed at a constant cycle.

That is, when recording a time code by the CTL coding method, in the case of NTSC, in addition to a 50-bit code block, a dummy bit of 10 bits is added in order to match the real time. At present, the method of counting CTL pulses and setting 30 counts to 1 second is widely used as a linear time counter in consumer VTRs as well, but since the code itself is 50 bits, it is 1 second cycle, that is, 30 bit cycle. Recording is not possible, and when recording the time code continuously, it is possible to record in units of 2 seconds with a 60-bit cycle. However, in NTSC, the number of frames is 29.97 frames / sec to be precise, and therefore the number of frames by the CTL pulse count deviates from the real time. It takes 108 frames (3.6 seconds) per hour to correct this shift, which cannot be ignored for long-term operation. To correct this deviation, 10 per hour
You can skip the count for 8 frames. That is,
Number of dummy bits per hour (10 bits x 60 x
You can reduce 108 bits from 60/2 = 18000 bits). As a method, 2 dummy bits in the time code having data of each minute (xx hours xx minutes 00 seconds) excluding every 10 minutes (0,10,20,30,40,50 minutes) Even if it is reduced, it is 8 bits ((60-6) x 2 bits = 108 bits). By this operation, it is possible to eliminate the deviation from the real time in the time code recording by the CTL pulse count.

That is, in view of the above points, the VTR data recording apparatus according to the present invention controls the duty cycle of the control pulse having a constant cycle according to the value of the time code and records the control pulse on the control track on the magnetic tape. 1
The figure shows an example of a signal format of data recorded by the device of the present invention. In the figure, H is a header consisting of 11 fixed bits, and U is a 16 bit for the user to record a program number or the like using an input device such as a keyboard.
Bit (4 bits BCD 4 digits) User bit, T is 19 bits (BCD 6 digits) time information data that represents the current time in hours, minutes and seconds. The first 2 bits are the tens digit of "hour", Next 4
The bit indicates the ones digit of the "hour", the next three bits the tenth digit of the minute, the next four bits the ones digit of the minute, and the next three bits The tens digit of "second" and the next three bits indicate the ones digit of "second". Also, S indicates a 4-bit checksum, D indicates an 8 or 10 dummy bit, and the first 1 bit identifies the correction mode or the non-correction mode. When "0", the non-correction mode (non-drop mode Frame mode) does not correct the time lag,
As a correction mode (drop frame mode) for "1", 8 bits of dummy bits (bits including drop frame bits) at 00 seconds of each minute except 0, 10, 20, 30, 40, and 50 minutes Number). As described above, one data block consisting of 60 bits corresponds to about 2 seconds for a video signal of 29.97 frames / second such as NTSC. Therefore, the digit of ones digit of "second" of the time information data T. Is 0, 2, 4, 6, 8 seconds 5
Three bits are sufficient because only one value needs to be indicated.

Therefore, according to the above signal format, it is possible to correct the time shift by changing the data length in one data block without skipping the time code data, and the data in the time code data is PAL or SECAM. It can be applied to 25-frame / sec video signals like this without any time lag.

By the way, when recording a time code by the CTL coding method, a dummy bit is added to the data block in order to manage the real time, but there are both when the dummy bit is 8 bits and when it is 10 bits. If the dummy bit is reduced to 8 bits and it is a drop frame, and the uncorrected 10 bits is a non-drop frame, the time code is recorded.
A drop frame is required when operations such as editing for real time are required as in a commercial VTR, but when using it in an addressing method that does not require matching with real time in a consumer VTR. It is advantageous to use a non-drop frame that is easy to process. Therefore, it is assumed that both modes are used properly, but it is not possible to determine which mode is recorded from the code itself.

Therefore, the first bit of the dummy bit is used as a discrimination bit for the drop frame and the non-drop frame, and when the code is recorded as shown in FIG. 1, the discrimination bit is "1" for the drop frame and for the non-drop frame. Sets the discrimination bit to "0".

Then, this dummy bit is recorded after the code block of the time code. This is because when the code is read, the position of the drop frame determination bit is always fixed to the 51st bit from the beginning of the time code, and the mode can be determined immediately, and when the dummy bit is in front of the code block. Further, it is possible to prevent that the position of the discrimination bit is changed between when the dummy bit is 8 bits and when the dummy bit is 10 bits, and it becomes impossible to immediately discriminate the mode.

That is, when decoding the time code at the time of reproduction, the value of the first bit of the dummy bit is determined to determine whether it is the non-drop frame mode or the drop frame mode. The dummy bit is added to the last part of one data block. If so, the mode for the time code data in this data block can always be determined immediately by looking at the 51st bit from the beginning of the header, and the dummy bit whose bit length changes in a predetermined cycle is included in one data block. Since it is at the end, it is only necessary to determine a certain number of bits from the header when reading user data and time code data.

On the other hand, if the dummy bit is provided between the header and the user bit, the position of each data with respect to the header is shifted by 2 bits depending on whether the dummy bit is 8 bits or 10 bits, which is not preferable.

If the dummy bit corresponding to the time code data in one data block is in front of the header, the determination bit of the 51st bit drop frame from the first bit of the header is determined for the next data block. become unable. On the other hand, in the case of having a memory and discriminating the first discrimination bit of the dummy bit before header detection,
The position of the discrimination bit changes depending on whether the dummy bit is 8 bits or 10 bits, and the mode discrimination cannot be performed immediately. By providing the dummy bit at the end of one data block and providing the discrimination bit at the head bit of the dummy bit. The above-mentioned inconvenience can be eliminated.

Next, FIG. 2 is a block diagram showing a VTR data recording apparatus of the present invention for recording the code of FIG. 1 on the CTL track of the VTR. Reference numeral 1 is, for example, a digital timer, the digital output of which is applied to an encoder 3 together with an operation input of a keyboard 2 for generating user data, from which coded pulses are output. This coded pulse is a clock signal (VD pulse) from the vertical synchronizing signal generation circuit 4.
It is designed to prevent fluctuations on the time axis by synchronizing with. Further, the signals thus synchronized are added to the monostable multivibrator (monomulti) 5. Here, a predetermined modulation is applied to each frequency obtained by dividing the clock frequency by 1/2 in the frequency dividing circuit 6, and a time-coded pulse is obtained. Then, this pulse is recorded amplifier 7
The data is recorded on a control track of a magnetic tape (not shown) by the well-known CTL head 8 via the.

FIG. 3 shows the digital timer 1 and the encoder 3 in FIG.
3 is a block diagram showing the configuration of FIG. The drop frame / non-drop frame switching signal is a signal which is selected by a manual switch (not shown) and takes one of H and L.
Same as used in SMPTE timecode. The digital timer 1 is an hour / minute / second / frame counter, receives a drop frame / non-drop frame switching signal, and uses the VD pulse as a clock.

The count value is managed by time data (hour / minute / second / frame) and is output to the encoder 3 as parallel data.

When the drop frame mode is selected by the drop frame / non-drop frame switching signal, the count value is preset so as to be skipped.

The value to be skipped is 2 frames of 0, 1 of each minute (XX time XX minute 00 seconds) except for every 10 minutes (0, 10, 20, 30, 40, 50). The digital timer 1 is known as an IC for time code generator, for example, manufactured by Sony Corporation.
EEC _o- 5200 can be used.

The encoder 3 includes parallel-serial (P / S) shift registers 3a to 3d, a data load timing generation unit 3e, a drop frame data detection unit 3f, a checksum calculation unit 3g, and a data latch 3h. P / S shift registers 3a-3d
Are for drop frame and dummy bit, for time code, for user code which is user data, and for header, respectively. Data load timing generator 3e is for each P / S
It controls the timing of writing data to the shift register, and responds to the output signal of the digital timer 1 and the VD pulse. The output of the digital timer 1 is also given to the drop frame data detector 3f and the checksum calculator 3g. The data latch 3h is inputting user data from the keyboard 2 shown in FIG. That is, the user data input from the keyboard 2 is the data latch.
It is latched at 3h and output to the P / S shift register 3d and the checksum calculation unit 3g.

The hour / minute / second data input from the digital timer 1 is supplied to the checksum calculation unit 3g, and the checksum calculation is performed together with the separately input user data, and the result is output together with the data.

In addition, the drop frame data detection unit 3f detects the time data (each minute, except every 10 minutes) corresponding to the drop frame from the hour, minute, second data, and only when the status of the drop frame mode is selected. , Outputs the detection status to the P / S shift register 3a.

The data load timing generator 3e uses the VD pulse as a clock, and after determining the second data, generates a load pulse and
Load values into P / S shift registers 3a-3d.

The loaded data uses the VD pulse as a clock.
The CTL data is output bit by bit from the header to the monomulti 5 in FIG.

The CTL data recorded on the magnetic tape via the magnetic head 8 by the circuit of FIG. 2 is reproduced by the method described in the above-mentioned Japanese Utility Model Publication No. 57-34633, but in the reproducing circuit, it responds to the duty detecting section. The structure of the decoder is as shown in FIG. That is, the CTL pulse and CTL data (value determined by duty) input from the duty detection unit are input to the shift register 9 having a length of 51 bits or more, and the data is latched using the CTL pulse as a clock.

Comparing 11 bits from the output side of the shift register 9
At 11, the header patterns are sequentially compared, and if they match, the 51st bit data (corresponding to the drop frame bit) from the output side is latched by the latch 10 in the match detection status.
Output as drop frame mode status.

[Effects of the Invention] As is clear from the above description, according to the VTR data recording apparatus of the present invention, when the time code is recorded by the CTL coding method, the dummy bit in which the number of bits changes at a constant cycle. Since the data blocks added with are continuously recorded, the time code time deviation correction can be performed without skipping the data content in the time code data, and the data can be made continuous, and therefore There is an effect that the time can be easily managed and the number of bits, that is, the drop frame mode or the non-drop frame mode, can be discriminated at the time of reproduction even if the number of dummy bits changes.

[Brief description of drawings]

FIG. 1 is a signal format diagram of data recorded by a VTR data recording apparatus of the present invention, FIG. 2 is a block diagram of a recording apparatus for recording the code data of FIG. 1 in a VTR CTL track, and FIG. Is a block diagram showing the configuration of the digital timer and encoder in FIG. 2, and FIG. 4 is a block diagram showing the configuration of the decoder. 1 ... Digital timer, 2 ... Keyboard, 3 ... Encoder, 3a to 3d, 3e ... Data load timing generation section, 3f ... Drop frame data detection section, 3g ... Checksum calculation section, 3h ... Data Latch, 4 ... Vertical sync signal generation circuit, 5 ... Mono-multivibrator, 6 ...
1/2 divider circuit, 7 ... Recording amplifier, 8 ... CTL head, 9
... shift register, 10 ... latch, 11 ... comparator.

Claims (1)

[Claims] 1. A VTR is used to appropriately select one of a plurality of types of data including position information of a magnetic tape on which a video signal is recorded and reproduced, and a duty cycle of a control pulse having a constant cycle is set according to the value of the selected data. In a VTR data recording device for controlling and recording on a control track of the magnetic tape, means for adding a dummy bit to the rear part of a data block having time code data consisting of the control pulse, and bit of the dummy bit at a constant cycle. A VTR data recording device comprising: means for changing the number; and means for making a bit having a fixed positional relationship with the first bit of the data block a discrimination bit representing the number of bits of the dummy bit.