JPH0341688A - Data recorder for vtr - Google Patents

Abstract

PURPOSE:To coincide time codes with the real time of recording by providing discrimination bits indicating the bit number of the dummy bits added with the bits having a specified positional relation with the top bit of a data block. CONSTITUTION:The dummy bits D are added to the rear part of the data block and the dummy bits D are recorded by changing the bit number thereof at a specified period. The discrimination bits indicating the bit number of the dummy bits D added with the bits indicating the specified positional relation with the top bit H of the data block are provided. The deviation in the time of the time code is corrected in this way and the control of the real time is more easily executed. In addition, the discrimination of the bit number at the time of reproduction, i.e. whether a drop frame mode or non-drop frame mode is executed in this way even if the bit number of the dummy bits changes.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a VTR that records data on a control track by varying the duty cycle of control pulses having a constant period according to positional information on a magnetic tape and data regarding special functions. The present invention relates to a data recording device.

[Prior Art] Conventionally, the duty cycle of a control pulse (CTL pulse) is varied and recorded on a control track based on data regarding the position information and arbitrary comment information of a magnetic tape used in a home VTR. There is a VTR data recording and reproducing apparatus based on the so-called CTL coding method, which is configured to reproduce and display this data and to allow random access.

Such a VTR data recording and reproducing device selects multiple types of data as appropriate and records and reproduces them on the control track of the magnetic tape, so the absolute position from the recording start point on the magnetic tape is pulsed. A VTR that records and plays back SMPTE time code that is recorded on a separate track.
It has excellent features, such as being able to be constructed at a lower cost than the previous one, being able to freely record any information with extremely simple operations, allowing random access, and being able to be used in a wide variety of ways.

[Problem to be solved by the invention] However, the control pulse has a period of l frame (1/
The data transmission bit rate is extremely low at 30 bits/second, and the data transmission bit rate is extremely low at 30 bits/second. When recording codes constituting one data block, it takes several seconds to record/reproduce one block of data.

Therefore, when recording a time code using CTL coding as described above, since the CTL coding method records 1 bit per frame, the same code format as the SMPTE time code of 80 bits per frame is used. If you cannot record the address code, treat it as time data, record it on the tape at fixed intervals (for example, every minute), and reset the frame counter at the position where the code is read.
After that, it is necessary to manage the frame by counting CTL pulses. However, there is a problem that if even one piece of data in the address code is lost, the position where the code can be read shifts.
In the case of color signals, the number of frames is nominally 29.97 frames per second, so there is a problem that the time code deviates from the real time by a small amount. For this reason,
When applying to CTL coding, such as SMPTE time code correction, skipping data (frame 1 00.01) indicating a predetermined time in a certain period, the length of one data block of CTL coding spans several seconds. Therefore, correction cannot be made unless such a time lag occurs, which is not preferable for real-time management.

Therefore, the present invention has been made to solve the above-mentioned problems, and is capable of achieving consistency with real time when recording time food using the CTL coding method.
The purpose of the present invention is to provide a TR data recording device.

[Means for Solving the Problems] A VTR data recording device according to the present invention adds dummy bits to the rear of a data block when recording a time code using the CTL coding method, and changes the number of dummy bits at regular intervals. means for recording the data block on a control track of a magnetic tape by changing the number of bits of the dummy bit, and for recording a bit having a fixed positional relationship with respect to the first bit of the data block as a discrimination bit representing the number of bits of the dummy bit. It has been established.

That is, according to the present invention, one of a plurality of types of data including position information of a magnetic tape on which a video signal is recorded and played back by a VTR is appropriately selected, and a control pulse of a constant period is generated according to the value of the selected data. In a data recording device for a VTR that records on the control track of the magnetic tape by controlling the utility cycle, means for adding a dummy bit to the rear of a data block having time code data consisting of the control pulse; A VTR characterized in that it has means for changing the number of bits, and means for setting bits having a fixed positional relationship with respect to the first bit of the data block as a discrimination bit representing the number of bits of the dummy bits. A data recording device is provided.

[Function] According to the VT, H data recording device of the present invention, by providing dummy bits at the rear of the data block and changing the number of dummy bits at regular intervals, it is possible to skip the data content in time code data. This makes it possible to correct the time lag in the time code without any distortion, and also provides a means for using a bit that has a certain positional relationship with the first bit of the data block as a discrimination bit that represents the number of dummy bits. By recognizing this discrimination bit during reproduction, the number of dummy bits can be known.

[Embodiment] Hereinafter, an embodiment of the data recording device for a VTR according to the present invention will be described in detail with reference to the drawings.

In the present invention, dummy bits are provided in the code to be recorded, and the number of dummy bits is changed at regular intervals in order to correct the time shift of the time code due to CTL coding.

That is, when recording time codes using the CTL coding method, in the case of NTSC, in addition to a 50-bit code block, dummy bits for IO bibits are added in order to match real time. Currently, consumer VTRs also have C.
A method that counts TL pulses and sets 30 counts as 1 second is often used as a linear time counter, but since the code itself is 50 bits, the period of 1 second, that is, 30 counts, is often used as a linear time counter.
It is not possible to record bit cycles, but when recording time codes continuously, if the time code is set to 60 bit cycles, it is possible to record in units of 2 seconds. However, in NTSC, the number of frames is exactly 29.97 frames/second, so the number of frames determined by CTL pulse count deviates from the real time. Correcting this shift requires 108 frames (3.6 seconds) per hour, which cannot be ignored in long-term operations. In order to correct this deviation, it is sufficient to read the count of 108 frames per hour. In other words, the number of dummy bits per hour (10 bits x 60 x
60/2 = 18,000 bits) to 108 bits. As a method, every 10 minutes (0,10
, 20, 30, 40, 50 minutes), the dummy bits in the time code that has data for each minute (XX hours x x minutes OO seconds) are reduced by 2 bits to 8 bits ((50 -
6) minutes x 2 bits = 108 bits).

By this operation, it is possible to eliminate the deviation from real time in time code recording by CTL pulse counting.

In other words, in view of the above points, the data recording device for a VTR according to the present invention controls the duty cycle of a control pulse having a constant period according to the value of a time code and records data on a control track on a magnetic tape. FIG. 1 shows an example of a signal format of data recorded by the apparatus of the present invention. In the figure, H is a header consisting of 11 fixed bits, U is a 16-bit (4-bit BCD 4 digits) user bit for the user to record the program number etc. using a manual device such as a keyboard,
T represents the current time in hours, minutes, and seconds 19 pins 1- (BC
D (6 digits) time information data, the first 2 bits indicate "hour"
The next 4 bits indicate the 1's digit of hour j, and the next 3 bits indicate the 10's digit of minute.
The next 4 bits are the 1's digit of the minute, and the next 3 bits are the 1's digit of the minute.
The next 3 bits indicate the 1s digit of the second. Also, S is a 4-bit checksum, and D is an 8-bit checksum.
Or indicates a dummy bit of lO, and the first bit identifies whether it is a correction mode or an uncorrected mode.When it is "0", it is an uncorrected mode (non-drop frame mode), and no time difference correction is performed. 1” correction mode (drop frame mode): 0,10°20, $0
．． 40. The dummy bits are 8 bits (the number of bits including drop frame bits) at the 00th second of each equinomous period except for the 50th minute. Note that one data block consisting of <60 bits as described above is This corresponds to about 2 seconds for a video signal of 29.97 frames/second, so
The ones digit of "second" in time information data T is 0, 2, 4,
Since it is sufficient to indicate five values of 6.8 seconds, 3 bits is sufficient.

Therefore, according to the above signal format, it is possible to correct the time difference by changing the data length within the l data block without skipping the time code data, and the data within the time code data is PALS SEC.
The present invention can be applied directly to a 25 frame/second video signal such as AM without any time lag.

By the way, when recording a time code using the CTL coding method, dummy bits are added to the data block in order to manage real time.
There are both 1-bit and 10-bit times, and a drop frame is when the dummy bits are reduced to 8 bits, and a non-drop frame is when the dummy bits are not reduced and uncorrected IO bits are used, and the time code is recorded. When using a commercial VTR, when operations such as editing that correspond to real time are required, a drop frame is required, but with a consumer VTR, it is used in an addressing manner that does not require synchronization with real time. In some cases, it may be advantageous to use a non-drown knob frame that is easy to process. Therefore, it is assumed that both modes are used selectively, but it is not possible to determine which mode is being recorded from the code itself.

Therefore, the first pit of the dummy bit is set as a discrimination bit between a drop/knob frame and a non-drop frame, and as shown in Figure 1, when recording a code, the discrimination bit is set to "l" for a drop frame, and "l" for a non-drop frame. In this case, the determination bit is set to "0".

This dummy bit is recorded after the time code code block. This means that when reading the code, the position of the drop frame discrimination pit is always fixed at the 51st bit from the beginning of the time code, so mode discrimination can be made immediately, and if the dummy bit is before the code block. The dummy bit is 8 bits.

It is possible to prevent the position of the determination bit from changing between when the mode is set and when the mode is set and when the mode is set, and the mode cannot be immediately determined.

In other words, when decoding the time code during playback, the value of the first bit of the dummy bit is determined to determine whether the mode is non-drop frame mode or drop frame mode. If there is, the mode for the time code data in this data block can be immediately determined by always looking at the 51st bit from the beginning of the header, and the dummy bit whose bit length changes at a predetermined period can be used to determine the mode for the time code data in one data block. Since it is located at the end, when reading user data and time code data, it is only necessary to determine a certain focus distance from the header.

On the other hand, if dummy bits are provided between the header and the user pits, the position of each data relative to the header will be shifted by 2 bits depending on whether the dummy bits are 8 bits or 10 bits, which is not preferable.

Also, if a dummy bit corresponding to time code data in one data block is located before the header, the drop frame determination bit at the 51st bit from the first bit of the header will be determined for the next data block. become unable. On the other hand, if a memory is provided and the first discrimination bit of the dummy bits before header detection is determined, the position of the discrimination bit changes depending on whether the dummy bits are 8 bits or 10 bits, and the mode can be immediately determined. However, by providing a dummy bit at the end of one data block and providing a determination bit at the head bit of the dummy bit, the above-mentioned inconvenience can be resolved.

Next, FIG. 2 is a block diagram showing a data recording apparatus for a VTR according to the present invention, which records the code shown in FIG. 1 on a CTL track of a VTR. 1 is a digital timer, for example, and the digital output is applied to an encoder 3 together with an operation input from a keyboard 2 for generating user data, from which coded pulses are output. This coded pulse is a clock signal (V
D pulse) to prevent time axis fluctuations. Further, the signal synchronized in this manner is applied to a monostable multivibrator (monomulti) 5. Here, the clock frequency is halved by the frequency divider circuit 6.
A predetermined modulation is applied to each divided frequency to obtain a time-coded pulse. Subsequently, this pulse is transferred to a well-known CTL via a recording amplifier 7 and recorded by a node 8 on a control track of a magnetic tape (not shown).

Figure 3 shows digital timer 1 and encoder 3 in Figure 2.
FIG. 2 is a block diagram showing the configuration of FIG. Drop frame/non-drop frame switching signal This is a signal that selects either H or L by using a manual switch (not shown), and is the same as that used in the conventional SMPTE time code.

The digital timer 1 is an hour, minute, second, and frame counter, inputs a drop frame/non-drop, and knob frame frame switching signal, and uses a VD pulse as a clock.

The count value is managed as time data (hours, minutes, seconds, frames) and is output to the encoder 3 as parallel data.

When the drop frame mode is selected by the drop frame/non-drop frame switching signal, the count value is preset to be skipped.

The value to skip is every 10 minutes (0, 10, 20, 30,
0. of each minute (XX hours XX minutes 00 seconds) except 40, 50). This is two frames of 1. As this digital timer 1, for example, Sony EEC0-5200, which is known as a time code generator IC, is used.
can be used.

The encoder 3 includes parallel-serial (P/S) shift registers 3a to 3d and a data load timing generator 3e.
, a drop frame data detection section 3f, a checksum calculation section 3g, and a data latch 3h. P,・
'S shift registers 3a to 3d are used for drop frames and dummy bits, time codes, user codes as user data, and headers, respectively. The data load timing generator 3e controls the timing of data writing to each P/S shift register, and responds to the output signal of the digital timer 1 and the VD pulse. The output of the digital timer l is also given to a drop frame data detection section 3f and a checksum calculation section 3g. The data latch 3h inputs user data from the keyboard 2 of FIG. That is, keyboard 2
User data inputted from the data latch 3h is latched by the data latch 3h, and output to the P/S shift register 3d and checksum calculation section 3g.

The hour, minute, and second data inputted from the digital timer 1 is supplied to a checksum calculation section 3g, which performs a checksum calculation together with user data that has been input separately, and outputs the result together with the data.

In addition, the drop frame data detection unit 3f extracts time data corresponding to the drop frame (every 1
Detection is performed for each positive minute (excluding 0 minute), and the detection status is output to the P/S shift register 3a only when the drop frame mode status is selected.

The data load timing generating section 3e uses the VD pulse as a clock, and after determining the second data, generates a load pulse to load a value into each P/S shift register 3a to 3d.

The loaded data is outputted bit by bit from the header to the monomulti 5 in FIG. 2 as CTL data using the VD pulse as a clock.

The CTL data recorded on the magnetic tape via the magnetic head 8 by the circuit shown in FIG.
The signal is reproduced by the method described in Publication No. 3, and in the reproduction circuit, the configuration of the decoder that responds to the duty detection section is shown in FIG. That is, the CTL pulse and CTL data (value determined by duty) inputted from the duty detection section are inputted to a shift register 9 having a length of 51 bits or more, and the data is latched using the CTL pulse as a clock.

The comparator 11 sequentially compares the 11 bits from the output side of the shift register 9 with the header pattern, and if they match, the match detection status indicates that the data at the 51st bit from the output side (
(equivalent to drop frame bit) is latched by latch IO and output as drop frame mode status.

[Effects of the Invention] As is clear from the detailed explanation above, according to the VTR data recording device of the present invention, when recording a time code using the CTL coding method, dummy bits whose number of bits changes at a constant cycle are used. Since the data blocks with the addition of In addition to making time management easier, even if the number of dummy bits changes, the number of bits, that is, whether the mode is drop frame mode or non-drop frame mode, can be determined during playback.

[Brief explanation of drawings]

FIG. 1 is a signal format diagram of data recorded by the VTR data recording device of the present invention, FIG. 2 is a block diagram of the configuration of the recording device that records the code data of FIG. 1 on the CTL track of the VTR, and FIG. 3 2 is a block diagram showing the configuration of the digital timer and encoder in FIG. 2, and FIG. 4 is a block diagram showing the configuration of the decoder. 1...Digital timer, 2...Keyboard, 3
...Encoder, 3a-3d, 3e...f'-9
1: 1-de timing generation section, 3f: drop frame data detection section, 3g: checksum calculation section, 3h: data latch, 4: vertical synchronization signal generation circuit, 5: monomulti Vibrator, 6...
l/2 frequency divider circuit, 7...recording amplifier, 8...C
TL head, 9...shift register, 10...
Latch, 11... comparator. Inventor Takeshi Okauchi

Claims (1)

[Claims] Appropriately select one from multiple types of data including position information of the magnetic tape on which the video signal is recorded and played back by the VTR,
In a VTR data recording device that controls the duty cycle of control pulses of a constant period according to the value of selected data and records on the control track of the magnetic tape, the rear part of a data block having time code data consisting of the control pulses. means for adding dummy bits to the dummy bits; means for changing the number of the dummy bits at regular intervals; and a determination bit indicating the number of the dummy bits, which has a fixed positional relationship with respect to the first bit of the data block. A data recording device for a VTR, characterized in that it has means for.