JPH0677936A - Error correcting system and hargelbarger decoding circuit used for the same - Google Patents

Abstract

PURPOSE:To improve the transmission error rate of a frame synchronizing signal and to eliminate necessity for switching an encoding system and a decoding system for the frame synchronizing signal and an information part. CONSTITUTION:Hargelbarger encoding is performed to both of the frame synchronizing signal and the information part. In this decoding circuit, this code is inputted to a Hargelbarger encoders/decoders 10 and 12, and the Hargelbarger decoding is executed at the respective Hargelbarger encoders/decoders 10 and 12 while using clocks Q1 and Q2 which phases are opposite each other. A parallel output from the correspondent Hargelbarger encoder/decoder 10 or 12 is compared with a synchronism detection part code and when they are coincident, frame synchronism detection circuits 14 and 16 outputs synchronism detecting signals to an output switching circuit 18. The output switching circuit 18 selects a serial output from the Hargelbarger encoder/decoder 10 or 12 detected the frame synchronism and outputs it as a decoding output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction system using a Hagelberger code.

[0002]

2. Description of the Related Art The Hagerberger coding system is a system in which an information code and an error correction code are alternately transmitted one bit at a time. This method can be used in error correction of transmission codes in wireless communication, such as unidirectional communication, satellite communication, mobile communication, and the like.

When performing frame transmission using the Hagerberger code, the frame structure is as shown in FIG. 4, for example. The frame shown in this figure is composed of a frame synchronization signal generated without using the Hargelberger code and an information section encoded with the Hagelberger code. When a frame having such a configuration is transmitted, the decoding side switches the decoding method after detecting the frame synchronization signal, and performs Hagerberger decoding on the information section.

[0004]

However, in such a system, since the Hagerberger code is not used for the frame synchronization signal, the transmission error rate of the frame synchronization signal cannot be improved, and the frame synchronization signal cannot be improved. There is a problem that it is necessary to switch the encoding method and the decoding method between the information section and the information section.

The present invention has been made to solve the above problems, and makes it possible to perform transmission and error correction by using a Hagerberger encoded frame synchronization signal. With the goal.

[0006]

In order to achieve such an object, the error correction system of the present invention encodes a frame synchronization signal by Hagelberger encoding, and the decoding side performs mutual 1
Frame synchronization is detected by generating a two-phase clock with a bit phase shift, Hagerberger decoding of the frame synchronization signal using each phase of the clock, and using the clock of the phase in which the frame synchronization is detected, the information section Is characterized by performing error correction by Hagelberger decoding.

Further, the Hargelberger decoding circuit of the present invention includes a first Hargelberger code decoder for decoding a frame, which includes a frame synchronization signal and an information part and is entirely Hagerberger encoded, at a predetermined phase, A second Hargelberger code decoder for decoding the frame at a phase shifted by 1 bit with respect to the first Hargelberger code decoder;
A first frame synchronization detection circuit that detects frame synchronization based on the decoding output of the first Hagerberger code decoder, and a second frame synchronization detection circuit that detects frame synchronization based on the decoding output of the second Hargelberger code decoder. When the frame synchronization is detected by the frame synchronization detection circuit and the first frame synchronization detection circuit, the decoded output of the first Hagerberger code decoder is detected, and the frame synchronization is detected by the second frame synchronization detection circuit. In this case, an output switching circuit that selects the decoded output of the second Hargelberger code decoder and outputs the selected decoded result is provided.

[0008]

In the error correction system of the present invention, not only the information part but also the frame synchronization signal is Hagerberger encoded and transmitted. On the decoding side, a two-phase clock whose phase is shifted by one bit is generated, and the frame synchronization signal and the information part are subjected to Hargelberger decoding by using each phase of the clock. When the frame synchronization signal is subjected to the Hagerberger decoding, the frame synchronization is detected by any one of the two-phase clocks. Therefore, if the information section is subjected to the Hagelberger decoding using the clock of the phase in which the frame synchronization is detected, A decoded output that has been subjected to error correction by the Hagelberger code will be obtained.

Further, according to the Hagerberger decoding circuit of the present invention, this error correction system is preferably realized. That is, the entire frame including the frame synchronization signal and the information part, which has been Hagerberger coded, is input to each of the first Hagelberger code decoder and the second Hargelberger code decoder. The first Hargelberger code decoder and the second Hargelberger code decoder are mutually 1
The code relating to the input is decoded with the phase shifted from the bit, and the result is given to the output switching circuit. The first frame synchronization detection circuit and the second frame synchronization detection circuit detect frame synchronization based on the decoded output of the first Hargelberger code decoder or the second Hargelberger code decoder, respectively. Since the first Hargelberger code decoder and the second Hargelberger code decoder perform the decoding processing in a phase shifted by 1 bit from each other, the first frame synchronization detection circuit and the second frame synchronization detection circuit Frame synchronization is detected. The output switching circuit selects the decoded output of the Hagerberger code decoder associated with the phase in which frame synchronization is detected, and outputs it as the decoding result. In this way, it is possible to preferably perform error correction on the frame in which the Hagerberger decoding is performed on both the frame synchronization signal and the information portion, and also to suitably perform the frame synchronization detection.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a Hargelberger decoding circuit according to an embodiment of the present invention. The decoding circuit shown in this figure is a circuit capable of suitably decoding a frame in which both the frame synchronization signal and the information part are encoded using the Hagelberger code as shown in FIG. is there.

The circuit shown in this figure includes the Hagelberger code decoders 10 and 12, and the frame synchronization detection circuit 14.
16 and 16, output switching circuit 18 and flip-flop 2
It consists of zero. The flip-flop 20 divides a clock of a predetermined frequency into two and divides the clock Q1 in opposite phase.
And Q2. These clocks Q1 and Q2 are input to the Hagelberger code decoder 10 or the Hagelberger code decoder 12. The Hagerberger code decoders 10 and 12 are sequentially input with a frame synchronization signal and an information part transmitted in the order shown in FIG. The Hagerberger code decoder 10 outputs the result of decoding using the clock Q1 in parallel to the frame synchronization detection circuit 14 and in series to the output switching circuit 18. Similarly, the Hagerberger code decoder 12 performs Hagerberger decoding of the input code using the clock Q2, outputs the result in parallel to the frame synchronization detection circuit 16 and serially outputs to the output switching circuit 18. .

The frame sync detection circuits 14 and 16 receive a predetermined sync detection code and execute frame sync detection. That is, the frame synchronization detection circuit 14 compares the parallel output of the Hagerberger code decoder 10 with the synchronization detection code and outputs a synchronization detection signal when they match. Similarly, the frame synchronization detection circuit 16 also compares the parallel output of the Hagerberger code decoder 12 with the synchronization detection code and outputs a synchronization detection signal when they match. The output switching circuit 18 selects the serial output of the decoder (10 or 12) in which the frame synchronization is detected and outputs it to the circuit in the subsequent stage (decoding output).

As described above, according to the present embodiment, even when the frame synchronization signal is subjected to the Hagerberger coding in addition to the information part, the Hagerberger decoding can be performed while suitably detecting the frame synchronization. That is, it becomes possible to improve the transmission error rate of the frame synchronization signal by using the Hagerberger code, and it is not necessary to switch the encoding system and the decoding system between the frame synchronization signal and the information section. Even when transmitting, it is possible to realize an error correction method without switching the encoding method and the decoding method.

Although the above description relates to an example in which there is one frame synchronization signal for one frame,
As shown in FIG. 3, A, A
A plurality of B, ... May be used. In this case, the output of the decoder 10 or 12 in which the frame synchronization is detected a predetermined number of times may be selected.

[0016]

As described above, according to the error correction system of the present invention, the frame synchronization signal is subjected to Hagerberger coding in addition to the information part, and the frame synchronization is performed by using the two-phase clocks which are out of phase by one bit. Since the detection and the Hagerberger decoding are performed, it is possible to improve the transmission error rate of the frame synchronization signal and eliminate the need to switch the encoding system and the decoding system between the frame synchronization signal and the information section.

Further, according to the Hagerberger decoding circuit of the present invention, the two Hagelberger code decoders and the frame synchronization detection circuit are used, and the respective Hagelberger code decoders are operated in a phase shifted by 1 bit from each other. Since the output of the Hagerberger code decoder in which the frame synchronization is detected is selected as the decoding result, the error correction method according to the present invention can be preferably realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a Hargelberger decoding circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a frame structure in this embodiment.

FIG. 3 is a diagram showing another example of a frame structure in this embodiment.

FIG. 4 is a diagram showing an example of a conventional frame structure.

[Explanation of symbols]

 10, 12 Hargelberger code decoder 14, 16 frame synchronization detection circuit 18 output switching circuit 20 flip-flop

Claims (2)

[Claims] 1. An information section is Hagerberger coded by alternately inserting an error correction code every other bit in the information code, and the Hagerberger coded information section is transmitted as a frame together with a frame synchronization signal and transmitted. In the error correction system that performs error correction by performing Hargelberger decoding on the generated frame, the frame synchronization signal is Hargelberger encoded, and the decoding side generates two-phase clocks that are 1-bit out of phase with each other. The frame synchronization signal is detected by Hagelberger decoding of the frame synchronization signal using the phase, and the error is corrected by performing the Hagelberger decoding of the information part using the clock of the phase in which the frame synchronization is detected. Error correction method. 2. A first Hargelberger code decoder for decoding a frame which is entirely Hargelberger encoded including a frame synchronization signal and an information part in a predetermined phase, and a first Hargelberger code for the frame. A second Hagerberger code decoder for decoding at a phase shifted by 1 bit with respect to the decoder; and a first frame synchronization detection circuit for detecting frame synchronization based on the decoded output of the first Hargelberger code decoder. , A second frame synchronization detection circuit for detecting frame synchronization based on the decoded output of the second Hargelberger code decoder, and a first frame synchronization detection circuit when the frame synchronization is detected by the first frame synchronization detection circuit. The decoded output of the Gerberger code decoder is used as the second Hagerberger code when the frame synchronization is detected by the second frame synchronization detection circuit. Select the decoded output of the issue unit, hard gel Burger decoding circuit, characterized in that it comprises an output switching circuit for output as a decoding result.