JPH03135116A - Error control system - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency by providing a memory storing the decoding state for each frame and the channel state corresponding to a frame data after decoding or an output of a detector or a bit. CONSTITUTION:A diversity synthesis circuit 5 takes a product between a reception level Rn and a detector output Vn for each bit and adds it to a diversity synthesis output up to the preceding time. Only an identification result MSB of a reception data in an output 5-3 of the synthesis circuit 5 is inputted to an inner coder decoder 6, from which the result is decoded, and a switch 7 selects a frame data 5-3 before decoding when an error unable to be corrected by the decoder 6 and a decoded data 6-1 when the correction is enabled and the selected data is inputted to a memory 8. When the decoder 6 detects an error unable to be corrected, the presence of error detection is inputted to the memory 8 from a terminal 6-2 as decoding disable information. Through the constitution above, a long block is divided into plural short frames and only a frame whose error is not corrected by a preceding reception is decoded and the rate of occurrence of correction disable error is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an error control method for realizing high quality control signal transmission in mobile communications with fading.

(Prior Art) In control signal transmission in mobile communications, it is required to reduce the probability of erroneous reception and to increase the probability of correct reception. As a signal encoding method that satisfies these conditions,
There is a concatenated encoding method that divides encoding into two stages: outer encoding and inner encoding, and uses an error detection code for outer encoding and a plurality of short block codes for inner encoding.

A block diagram for implementing this concatenated encoding method is shown in FIG. In the same figure, transmission information of k bits is first (nt-kt
) is outer encoded using an error detection code with check bits. As this, a 16-bit cyclic code (CRC) such as that normally used in HDLC encoding can be used. Divide this into every 2 bits and divide each bit into t
A frame of n2 bits is created by correcting errors up to bits and internally encoding with an error correction code (2 at n2.) that can detect the occurrence of errors from +1 to S bits. The number of check bits is (nz-2) bits.

This process is shown in FIG. In the figure, the code format (a
), (b), (c) are (a) in Figure 3,
(b) and (c) are the code formats of points. in this way,
Concatenated coding is to combine nt/L frames into one and transmit them as a block of bits to n, Xn, /. The encoding method used in inner encoding is capable of error detection as well as error correction, so from 1 to n+/
It is possible to specify which frame of the two frames has been detected as having an error. Therefore, if even one frame in which an uncorrectable error is detected during frame decoding is found, it can be immediately retransmitted. Normally in this case the entire block would be retransmitted.

A method of executing the above-mentioned decoding process from the beginning when it is retransmitted is described in the literature (T, Kasami et al.).

et al,, “A concatenated c.
oding schime forerror co
ntrol,” IEEE Trans, Commu.
n,,vol.

C0M-34, pp. 481-488. No, 5.
May 1986). Concatenated encoding has a feature that the erroneous reception rate can be extremely small because the encoding is done in two stages.

(Problem to be Solved by the Invention) However, in the conventional method described above, if even one error-detected frame is detected, the entire received data block is discarded and retransmitted. As the number of times increases, the transmission efficiency decreases. This poses a particularly serious problem when fading occurs, such as in mobile communications.

The present invention is intended to solve these problems, and provides an error control method that realizes highly reliable control signal transmission in a fading environment without reducing transmission efficiency even when the information length becomes long. With the goal.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides error correction and retransmission in which a transmission data block is encoded with an error detection code, further divided into a plurality of small blocks, framed, and transmitted. This error control method is characterized by having a memory that stores the decoding state of each frame, decoded frame data or detector output, and channel state information corresponding to bits.

(Operation) According to the present invention having the above configuration, firstly, in the first invention, when a frame whose error could not be corrected is detected in the inner code decoding process, retransmission of the entire block is requested. For only frames whose errors could not be corrected during reception, the inner code is applied after diversity combining the previous pre-decoded frame data and the corresponding pre-decoded frame data in the block received by retransmission using channel state information. Decrypt with . Once the error is corrected, the correct decoded erroneous frame data is stored. As an example of the diversity method, the reception level is used as the channel state, and the reception level Rn and the detector output V are used for each bit. Which product is taken and added to the previous diversity synthesis output wn to obtain a new W. You can apply the method to obtain Here, n represents the nth bit within one frame. This can be expressed as a formula: Wn+RnX
It becomes vy1-wn.

Another diversity method is to select the bit with the higher received level.

In mobile communications, fading significantly degrades transmission characteristics, so the longer the data length, the greater the probability that uncorrectable errors will occur, the number of retransmissions increases with data length, and transmission efficiency decreases. Resulting in. However, in the first invention, a long block is divided into a plurality of short frames, and only frames whose errors could not be corrected in the previous reception are decoded, so errors that cannot be corrected occur due to the short frame length. rate becomes smaller. Therefore, even if there is a frame in which an error that cannot be corrected occurs in the first received block, there is a low probability that the error cannot be corrected in the next received frame. Transmission efficiency can be higher than when retransmitted blocks are newly decoded from the beginning without storing the state. Furthermore, for frames whose errors could not be corrected, the reliability of each bit in the pre-decoded frame is increased through pre-decoding diversity combining and then decoded using the inner code, so there is a probability that an error bit will occur when decoding again. can be made very low, and control signals can be transmitted with almost no errors in just one retransmission.

In the second invention, the number of error correction bits is stored as a frame decoding state, each frame of a block received by retransmission is decoded using an inner code, the number of error correction bits is compared with the previous value, and the smaller number is The decoded frame data and the number of error correction bits thereof are stored. This can be called post-decoding diversity combining. The reason why this reduces the frame error rate is that the greater the number of corrected bits, the higher the probability of incorrect correction. This method has the advantage that it does not require diversity combining using reception levels, so the configuration of the receiving side can be simplified.

(Example) Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

First, convert the detector output 1 and the received level detector output 2 into an A/D
Sampling is performed by converters 3 and 4, respectively. In a typical example, the clock extracted and regenerated on the receiving side is used as a sunfull pulse, and the detector output and reception level are A/D converted. The sample pulses of A/D converters 3 and 4 are synchronized. Below, a case will be explained in which, for example, an 8-bit output A/D converter is used. For example, the output of the A/D converter 3 is a digital output of the amplitude of the detected received data,
The MSB indicates the polarity of the received data, and the second to LSB indicate the amplitude. Therefore, the MSB becomes the identification result of the received data. 5-1 is a calculator, and each 8
Multiply the outputs of converters 3 and 4 in bits and the resulting 16
The upper 8 bits are extracted and used as frame data before decoding.

5-2 is an adder which adds the undecoded frame data of one frame before and new data. M representing the identification result of received data among the outputs 5-3 of the diversity combining circuit 5
Only the SB is input to the inner code decoder 6 and decoded. In the switch 7, if an error that cannot be corrected by the inner code decoder 6 (
If an error in bits t+1 to S bits) is detected, the output of the diversity combining circuit 5, that is, the 8-bit pre-decoded frame data 5-3, is corrected, and if the error is corrected, the decoded data 6-1 is selected and input to the memory 8. do. The decoded data 6-1 is obtained by extracting only the MSB of the 8 bits and setting the remaining bits to O, for example. Further, when an error that cannot be corrected is detected by the decoder 6, the presence of the error detection is inputted to the memory 8 from the terminal 6-2 as decoding off-field information. Here, the memory 8 is a write/read control section 8-1
and a memory area 8-2. The memory area 8-2 has an area for storing decoding status information and frame data for each frame. This frame data is decoded data when no error is detected by the inner code decoder 6, and is pre-decoded frame data consisting of n2×8 bits when an error is detected. The control unit 8-1 controls writing and reading of frame decoding state information and frame data.

When all frames have been corrected without errors (as can be seen from the frame decoding status information), the n1-bit inner code decoded data is transferred to the outer code decoder 9, and the decoder 9 performs error detection. If no error is detected, the error check bit is removed, the bit is output from the terminal 10, and the memory 8 is cleared.

On the other hand, if there is an error in even one of the frames (as can be seen from the frame decoding status information), or if an error is detected in the decoder 9, the retransmission control unit 11 retransmits the data from the terminal 12 to the transmitting side. Outputs a request signal.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

First, the detector output 21 is converted to a binary (1 or O) discrimination circuit 2.
2, and the identification result is input to the inner code decoder 23 and decoded. Since no A/D converter is used here as in the first embodiment, the circuit is not designed for an 8-bit parallel data structure but for a normal bit string. The inner code decoder 23 performs decoding and detects the number of corrected bits of the frame. Comparison circuit 24 compares the number of bits of the previous time and this time, and if the number of corrected bits is smaller this time, a switch 25 inputs the number of corrected bits together with the current decoded frame data to memory 26 as decoding state information.

The memory 26 is composed of a write/read control section 26-1 and a memory area 26-2. Memory area 26-2
Each frame has an area that can store decoding state information and frame data of n,- bits. The write/read control unit 26-1 controls writing/reading of frame decoding state information and frame data. The memory area 26-2 only needs to store 02 bits per frame, and has a capacity of 178 bits compared to the memory of the first embodiment.

When all frames have been decoded, n1 bits of data are transferred to the outer code decoder 27, and the decoder 27 performs error detection. If no error is detected, the error check bit is removed and every one bit is output from the terminal 28, and the memory 26 is cleared. On the other hand, if an error is detected,
The retransmission control unit 29 outputs a retransmission request signal from the terminal 30 to the transmitting side.

(Effects of the Invention) As described above, according to the present invention, since diversity combining is performed using retransmitted block data, transmission efficiency can be increased with a simpler configuration than in conventional transmission systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a block diagram showing a second embodiment of the present invention, and FIG. 3 is a block diagram showing the structure of a conventional continuous error correction coding system. The block diagram, FIG. 4, is a diagram showing the contents of each signal in FIG. 3. 1.21...Detector output, 2...Reception level, 3.4...A/D converter, 5...Diversity combining circuit, 6.23...Inner code decoder, 7 .25...Switch, 8.26φφ・Memory, 9.27...Outer code decoder, 10, 28...k1 bit output data, 11, 29...
...Retransmission control unit, 12, 30...Retransmission request, 22...Identification circuit, 24...Comparison circuit. U, II Mi I Seven 3-cho ヱ, Natej Shii 3rd figure

Claims (2)

[Claims] (1) Encode the transmission data block with an error detection code,
Furthermore, in an error control method that combines error correction and retransmission in which the frames are divided into multiple small blocks and transmitted, the decoding state of each frame, post-decoded frame data or detector output, and bit-based channel state information are When a retransmitted data block is received, only for frames in which an error was detected last time, the detector outputs in the memory for the current and previous received data are weighted using the channel state information in the memory. An error control method characterized in that the frames are combined and then subjected to error correction decoding. (2) The number of error correction bits of each frame of the retransmitted data block is compared with the previous value, and the smaller decoded frame data is selected and stored in the memory. error control scheme.