JPH0677351A - Semiconductor mounting board - Google Patents

Semiconductor mounting board

Info

Publication number
JPH0677351A
JPH0677351A JP23050592A JP23050592A JPH0677351A JP H0677351 A JPH0677351 A JP H0677351A JP 23050592 A JP23050592 A JP 23050592A JP 23050592 A JP23050592 A JP 23050592A JP H0677351 A JPH0677351 A JP H0677351A
Authority
JP
Japan
Prior art keywords
package
semiconductor
semiconductors
terminal pins
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23050592A
Other languages
Japanese (ja)
Inventor
Teruyoshi Baba
照義 馬場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP23050592A priority Critical patent/JPH0677351A/en
Publication of JPH0677351A publication Critical patent/JPH0677351A/en
Pending legal-status Critical Current

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Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To enable a plurality of packages to be mounted in high density on a board and enable the mounting of another different kind of semiconductor or circuit element, too, by loading a plurality of package semiconductors into multistage. CONSTITUTION:This semiconductor mounting board is constituted by mounting a plurality of package semiconductors 2 such as package ICs, etc., on a board 9. Moreover, for the package semiconductor 2, a plurality of terminal pins 3 are arranged in matrix shape on one side of a package with a built-in semiconductor bare chip. Especially, a plurality of package semiconductors 2 are loaded in such a manner as to insert a plurality of terminal pins 3 of a separate package semiconductor 2 into a plurality of openings 4 of a package semiconductor 2. Hereby, package semiconductors 2 can be mounted in higher density than before.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複数のパッケージ半導
体を実装して成る半導体実装基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting board on which a plurality of package semiconductors are mounted.

【0002】[0002]

【従来の技術】従来の半導体実装基板は、抵抗、コンデ
ンサ、トランジスタ等の回路素子や、パーケージIC等
のパッケージ半導体を、直接はんだ付け若しくは差込み
コネクタを介して回路パターンを敷設した基板に実装し
て構成されている。
2. Description of the Related Art In a conventional semiconductor mounting board, circuit elements such as resistors, capacitors and transistors, and package semiconductors such as package ICs are mounted on a board on which a circuit pattern is laid directly by soldering or through a plug connector. It is configured.

【0003】[0003]

【発明が解決しようとする課題】然しながら従来、複数
のパッケージ半導体を基板に実装するためには、前記基
板に前記パッケージ半導体の実装個数分の専有面積を必
要とするので、該パッケージ半導体の実装個数に応じて
基板の大型化が避けられなかった。
However, conventionally, in order to mount a plurality of package semiconductors on a substrate, the board requires an occupied area corresponding to the number of package semiconductors mounted. Therefore, the number of package semiconductors mounted is required. Therefore, the size of the substrate has inevitably increased.

【0004】本発明は上記の問題に鑑みて成されたもの
で、その目的とするところは、パッケージ半導体を従来
に比して高密度に実装した半導体実装基板を提供するこ
とにある。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor mounting substrate on which package semiconductors are mounted at a higher density than in the conventional case.

【0005】[0005]

【課題を解決するための手段】上記の問題点を解決する
ため本発明は、パッケージの一方の面に配設された複数
の端子ピンと、前記パッケージの他方の面に開口し且つ
前記端子ピンに電気的接続された開口孔であって、前記
複数の端子ピンの配設位置に対応して前記パッケージに
配設された複数の開口孔とを具備するパッケージ半導体
を、複数個実装して成る半導体実装基板において、前記
パッケージ半導体の複数の開口孔夫々に、別体のパッケ
ージ半導体の複数の端子ピン夫々を挿入して、複数のパ
ッケージ半導体を積載したことを特徴とするものであ
る。
In order to solve the above problems, the present invention provides a plurality of terminal pins arranged on one surface of a package and an opening on the other surface of the package and the terminal pins. A semiconductor in which a plurality of package semiconductors, each of which is an electrically connected opening hole and has a plurality of opening holes arranged in the package corresponding to the arrangement positions of the plurality of terminal pins, are mounted. In the mounting substrate, a plurality of package semiconductors are loaded by inserting a plurality of terminal pins of a separate package semiconductor into the plurality of opening holes of the package semiconductor, respectively.

【0006】[0006]

【作用】複数のパッケージ半導体を多段に積載すること
により、複数のパッケージを基板に高密度に実装するこ
とが出来る。
By stacking a plurality of package semiconductors in multiple stages, a plurality of packages can be mounted on the substrate at a high density.

【0007】[0007]

【実施例】以下に本発明を、その実施例を示す図面を用
いて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments.

【0008】図1は、本発明実施例の半導体実装基板を
示す要部斜視図であり、図2は、同半導体実装基板の要
部拡大断面図である。該半導体実装基板は、パッケージ
ICなどのパッケージ半導体2を、複数個積載して、基
板9に実装して構成されている。
FIG. 1 is a perspective view of an essential part of a semiconductor mounting board according to an embodiment of the present invention, and FIG. 2 is an enlarged sectional view of an essential part of the semiconductor mounting board. The semiconductor mounting substrate is constructed by stacking a plurality of package semiconductors 2 such as package ICs and mounting them on a substrate 9.

【0009】該パッケージ半導体2は、例えば図1に示
すように半導体ベアチップを内蔵したパッケージ8の一
方の面に、複数の端子ピン3をマトリクス状に配置した
構成となっている。該パッケージ8には、前記複数の端
子ピン3のマトリクス状配置に対応して、該端子ピン3
の配置面とは反対側の面に開口するよう、複数の開口孔
4が設けられている。又、図2に示すように、該開口孔
4の内面及び開口部付近には銅、ニッケル、金等の金属
メッキ7が施されており、該金属メッキ7が、パッケー
ジ8に内蔵の半導体ベアチップ(図示せず)に電気的接
続されている。前記端子ピン3は、図2の如く、前記開
口孔4に圧入され、半田6により固定されて、前記金属
メッキ7に電気的接続されている。
The package semiconductor 2 has, for example, as shown in FIG. 1, a plurality of terminal pins 3 arranged in a matrix on one surface of a package 8 having a semiconductor bare chip built therein. In the package 8, the terminal pins 3 corresponding to the matrix arrangement of the plurality of terminal pins 3 are provided.
A plurality of opening holes 4 are provided so as to open on the surface opposite to the arrangement surface of. Further, as shown in FIG. 2, metal plating 7 of copper, nickel, gold or the like is applied to the inner surface of the opening 4 and the vicinity of the opening, and the metal plating 7 is a semiconductor bare chip built in a package 8. (Not shown). As shown in FIG. 2, the terminal pin 3 is press-fitted into the opening hole 4, fixed with solder 6, and electrically connected to the metal plating 7.

【0010】該半導体実装基板1は、パッケージ半導体
2の複数の端子ピン3夫々を、別のパッケージ半導体2
の複数の開口孔4夫々に嵌挿することにより、複数のパ
ッケージ半導体2を多段に積載して成っている。この積
載方法のついて述べると、下段のパッケージ半導体2の
各開口孔4夫々に熱硬化性のクリーム状の半田6を必要
に応じて注入し、上段のパッケージ半導体2の各端子ピ
ン3夫々に金属性のスペーサー5を嵌合すると共に、該
上段のパッケージ半導体2の各端子ピン3夫々を、前記
下段のパッケージ半導体2の各開口孔4夫々に嵌挿し、
更に前記各端子ピン3と前記金属メッキ4とに係るよう
前記クリーム状の半田6を盛る。このようにして、複数
のパッケージ半導体2を積載していき、最終的にリフロ
ー処理して前記クリーム状の半田6を熱硬化させる。
The semiconductor mounting substrate 1 includes a plurality of terminal pins 3 of a package semiconductor 2 which are connected to another package semiconductor 2 respectively.
The plurality of package semiconductors 2 are stacked in multiple stages by being fitted into each of the plurality of opening holes 4. This stacking method will be described. Thermosetting cream-like solder 6 is injected into each of the opening holes 4 of the lower package semiconductor 2 as needed, and metal is applied to each of the terminal pins 3 of the upper package semiconductor 2. A spacer 5 having a conductive property, and each terminal pin 3 of the upper package semiconductor 2 is fitted into each opening hole 4 of the lower package semiconductor 2,
Further, the creamy solder 6 is laid on the terminal pins 3 and the metal plating 4. In this way, a plurality of package semiconductors 2 are stacked, and finally the reflow process is performed to thermally cure the creamy solder 6.

【0011】以上構成の半導体実装基板1は、様々な用
途の回路基板に応用出来るが、特に高密度実装が要求さ
れるコンピューター用の回路基板の高密度実装化が実現
出来る。
The semiconductor mounting board 1 having the above-described structure can be applied to circuit boards for various purposes, but it is possible to realize high density mounting of a circuit board for a computer which requires high density mounting.

【0012】[0012]

【発明の効果】以上の如く構成した本発明によれば、複
数のパッケージ半導体を積載することにより、該パッケ
ージ半導体を基板に高密度に実装することが出来、更な
る別種類の半導体や回路素子の実装が可能となると共
に、小面積の基板に対しても、半導体や回路素子を高密
度に実装することが出来る。
According to the present invention configured as described above, by mounting a plurality of package semiconductors, the package semiconductors can be mounted on a substrate at a high density, and further different types of semiconductors and circuit elements can be mounted. In addition to being able to be mounted, semiconductors and circuit elements can be mounted at high density even on a substrate having a small area.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例の半導体実装基板を示す要部斜視
図。
FIG. 1 is a perspective view of a main part showing a semiconductor mounting substrate according to an embodiment of the present invention.

【図2】本発明実施例の半導体実装基板を示す要部拡大
断面図。
FIG. 2 is an enlarged sectional view of an essential part showing a semiconductor mounting board according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体実装基板 2 パッケージ半導体 3 端子ピン 4 開口孔 8 パッケージ 9 基板 1 semiconductor mounting substrate 2 package semiconductor 3 terminal pin 4 opening hole 8 package 9 substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 パッケージの一方の面に配設された複数
の端子ピンと、前記パッケージの他方の面に開口し且つ
前記端子ピンに電気的接続された開口孔であって、前記
複数の端子ピンの配設位置に対応して前記パッケージに
配設された複数の開口孔とを具備するパッケージ半導体
を、複数個実装して成る半導体実装基板において、 前記パッケージ半導体の複数の開口孔夫々に、別体のパ
ッケージ半導体の複数の端子ピン夫々を挿入して、複数
のパッケージ半導体を積載したことを特徴とする半導体
実装基板。
1. A plurality of terminal pins arranged on one surface of a package, and opening holes opened on the other surface of the package and electrically connected to the terminal pins, wherein the plurality of terminal pins are provided. Of a plurality of package semiconductors having a plurality of opening holes arranged in the package corresponding to the arrangement positions of the package semiconductors. A semiconductor mounting board, characterized in that a plurality of terminal pins of a package semiconductor of a body are respectively inserted and a plurality of package semiconductors are loaded.
JP23050592A 1992-08-28 1992-08-28 Semiconductor mounting board Pending JPH0677351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23050592A JPH0677351A (en) 1992-08-28 1992-08-28 Semiconductor mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23050592A JPH0677351A (en) 1992-08-28 1992-08-28 Semiconductor mounting board

Publications (1)

Publication Number Publication Date
JPH0677351A true JPH0677351A (en) 1994-03-18

Family

ID=16908816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23050592A Pending JPH0677351A (en) 1992-08-28 1992-08-28 Semiconductor mounting board

Country Status (1)

Country Link
JP (1) JPH0677351A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278548B1 (en) 1998-03-27 2001-08-21 Hitachi, Ltd. Polarizing diffraction grating and magneto-optical head made by using the same
KR20040069788A (en) * 2003-01-30 2004-08-06 아남반도체 주식회사 Structure of epitaxy package in module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278548B1 (en) 1998-03-27 2001-08-21 Hitachi, Ltd. Polarizing diffraction grating and magneto-optical head made by using the same
KR20040069788A (en) * 2003-01-30 2004-08-06 아남반도체 주식회사 Structure of epitaxy package in module

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