JPH0677318A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0677318A JPH0677318A JP22540792A JP22540792A JPH0677318A JP H0677318 A JPH0677318 A JP H0677318A JP 22540792 A JP22540792 A JP 22540792A JP 22540792 A JP22540792 A JP 22540792A JP H0677318 A JPH0677318 A JP H0677318A
- Authority
- JP
- Japan
- Prior art keywords
- chips
- substrate
- scribing
- semiconductor
- trenches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
係り、特に複数の素子が形成された半導体基板を素子に
分割する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of dividing a semiconductor substrate having a plurality of elements formed into elements.
【0002】[0002]
【従来の技術】化合物半導体基板上に形成された素子の
分離方法については、硬質結晶針例えばダイアモンドス
クライバで該基板をけがいた後に応力を印加してけがき
部で分離するか、またはブレードダイサを用いて直接該
基板を切断する方法が知られている。2. Description of the Related Art As a method for separating elements formed on a compound semiconductor substrate, the substrate is inscribed by a hard crystal needle such as a diamond scriber, and then stress is applied to separate the inscribed portions, or a blade dicer is used. There is known a method of directly cutting the substrate.
【0003】従来の素子分離技術の一例として、以下、
GaAs半導体素子製造の素子分離工程について述べ
る。図2(a)および(b)はGaAs基板上に形成さ
れた半導体素子をダイヤモンドスクライバを用いて行う
分離工程を示すものである。As an example of a conventional element isolation technique,
A device isolation process for manufacturing a GaAs semiconductor device will be described. FIGS. 2A and 2B show a separation process in which a semiconductor element formed on a GaAs substrate is performed using a diamond scriber.
【0004】図2(a)に示すようにGaAs基板11
上に素子12と同時に形成されたスクライブ予定域13
に該基板11表面からダイヤモンドのスクライバ15で
けがき19部を設ける。As shown in FIG. 2A, the GaAs substrate 11
Planned scribe area 13 formed at the same time as element 12
Then, 19 parts of scribing are provided from the surface of the substrate 11 with a diamond scriber 15.
【0005】次に図2(b)に示すように該基板11の
けがき部19を表面または裏面から部分的に応力を加え
るため、例えばピンセット16やローラで押圧し工程を
終了していた。Next, as shown in FIG. 2B, in order to partially apply stress to the scribed portion 19 of the substrate 11 from the front surface or the back surface, for example, tweezers 16 or a roller is pressed to complete the process.
【0006】[0006]
【発明が解決しようとする課題】上記において、該基板
11の厚さが100μm以上と大きく、面内で不均一な
部分があればダイヤモンドスクライバ15で一定の圧力
のけがきを施すことはできず、後に応力を加えても分離
できない、または第4図に示すように素子周辺部が欠け
る等の問題が発生していた。素子分離を確実に行う方法
ではブレードダイサを用いた切断法があるが、これは前
者で述べたけがき方法以上に素子周辺部に与える損傷が
大きく、基板のへき開性によっては素子自体に悪影響を
及ぼすなどの問題があった。In the above, if the thickness of the substrate 11 is as large as 100 μm or more and there is a non-uniform portion in the plane, the diamond scriber 15 cannot apply a constant pressure scribing. However, even if stress is applied later, there is a problem such that the element cannot be separated, or the peripheral portion of the element is chipped as shown in FIG. There is a cutting method using a blade dicer as a method for surely separating the elements, but this causes more damage to the element periphery than the scribe method described in the former, and it adversely affects the element itself depending on the cleavage of the substrate. There was such a problem.
【0007】本発明は上記従来の問題点に鑑みて素子分
離を容易にし、かつ素子の品質の向上をはかることを目
的とする。In view of the above conventional problems, it is an object of the present invention to facilitate element isolation and improve element quality.
【0008】[0008]
【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、複数の半導体素子が形成された半導体基
板のスクライブ予定域に選択エッチングによりV字形の
溝を形成する工程と、前記溝内にスクライビングを施し
素子分離を行う工程とを含むものである。A method for manufacturing a semiconductor device according to the present invention comprises a step of forming a V-shaped groove by selective etching in a planned scribe area of a semiconductor substrate on which a plurality of semiconductor elements are formed, and the groove. And a step of performing elemental isolation by performing scribing inside.
【0009】[0009]
【作用】半導体基板上に複数形成された素子の分離にお
いて、素子の周辺部および素子自体に損傷を与えず確実
に分離が達成できる。また、素子の形状が改善されるの
で、素子単体で取り扱う組立工程においても素子の損傷
が少なくなる。In the separation of a plurality of elements formed on the semiconductor substrate, the separation can be reliably achieved without damaging the peripheral portion of the element and the element itself. Further, since the shape of the element is improved, the element is less damaged even in the assembly process of handling the element alone.
【0010】[0010]
【実施例】以下、本発明の実施例につき図面を参照して
説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0011】図1(a)〜(d)に本発明の実施例を工
程順に断面図で示す。図1(a)は化合物半導体基板、
例えばGaAs半導体基板の素子形成表面工程を終了し
た状態を示し、該基板1の素子2表面を保護し、スクラ
イブ予定域3を一部開孔するもの例えばレジストパター
ン7を形成する。1A to 1D are sectional views showing an embodiment of the present invention in the order of steps. FIG. 1A shows a compound semiconductor substrate,
For example, a state in which the element forming surface process of the GaAs semiconductor substrate is completed is shown, the surface of the element 2 of the substrate 1 is protected, and a part of the planned scribe area 3 is opened, for example, a resist pattern 7 is formed.
【0012】次に図1(b)の様にレジスト開孔部8の
該基板1に対して斜方的にエッチングが行える例えばリ
ン酸系エッチャントのウェットエッチングによってV字
形の溝4を形成する。ここでV字形となるまでのエッチ
ング溝4の深さはレジスト開孔部8の寸法に依存し、G
aAs半導体基板(100)を用いた場合はレジスト開
口寸法のおよそ1/2がエッチング溝の深さに相当す
る。例えばレジスト開孔部8が30〜40μmであれば
エッチング溝4の深さは15〜20μm程度となる。Next, as shown in FIG. 1B, a V-shaped groove 4 is formed by wet etching with a phosphoric acid-based etchant which can obliquely etch the substrate 1 in the resist opening 8. Here, the depth of the etching groove 4 until it becomes V-shaped depends on the size of the resist opening portion 8, and G
When the aAs semiconductor substrate (100) is used, approximately 1/2 of the resist opening size corresponds to the depth of the etching groove. For example, if the resist opening 8 is 30 to 40 μm, the depth of the etching groove 4 is about 15 to 20 μm.
【0013】上記エッチング溝4が形成された該基板の
裏面に対し図1(c)に示すように従来と同様に研磨に
よって基板を薄層化し、素子を完成させる。このとき研
磨時に起こりうる機械的衝撃によって該基板1が割れる
ことも有り得るが、スクライブ予定域3に形成されてい
るV字形の溝底4に衝撃力が集中するので素子自体が損
傷することは無い。As shown in FIG. 1 (c), the substrate is thinned by polishing in the same manner as in the prior art on the back surface of the substrate on which the etching groove 4 has been formed, to complete the element. At this time, the substrate 1 may be cracked by a mechanical shock that may occur during polishing, but since the impact force concentrates on the V-shaped groove bottom 4 formed in the planned scribe area 3, the element itself is not damaged. .
【0014】次に図1(d)に示すようにダイヤモンド
スクライバ5でスクライブ予定域3のエッチング溝4底
にけがきを施してけがき部9を設けたのち、従来と同様
に素子分離する。Next, as shown in FIG. 1 (d), a diamond scriber 5 is used to scribing on the bottom of the etching groove 4 in the planned scribing area 3 to provide a scribing portion 9, and then the elements are separated in the same manner as in the prior art.
【0015】この方法によると、基板の厚さが面内にお
いて多少不均一でダイヤモンドスクライバ5の圧力が一
定にかからなかったとしてもエッチング溝により確実に
スクライブ予定域内で分離できる。According to this method, even if the thickness of the substrate is a little uneven in the surface and the pressure of the diamond scriber 5 is not constant, the etching groove can surely separate the scribed region.
【0016】また、図3に示すように素子上部の周辺部
に傾斜をもつ状態に分離されるため、その後のハンドリ
ングによる基板の欠けや素子自体の損傷を極めて少なく
することができる。Further, as shown in FIG. 3, since the peripheral portion of the upper portion of the element is separated into an inclined state, chipping of the substrate and damage to the element itself due to subsequent handling can be extremely reduced.
【0017】[0017]
【発明の効果】以上述べたようにこの発明によれば、化
合物半導体基板上に形成された素子の分離において、素
子の周辺部および素子自体に損傷を与えず確実に分離が
達成できる。As described above, according to the present invention, in the isolation of the element formed on the compound semiconductor substrate, the isolation can be surely achieved without damaging the peripheral portion of the element and the element itself.
【0018】また、素子単体で取り扱う組立工程の場合
においても、素子の損傷、例えば、ピンセットなどで素
子上部を欠くようなことも少なくなる。Also, in the case of an assembly process in which the element is handled alone, damage to the element, for example, the fact that the upper part of the element is chipped due to tweezers or the like is reduced.
【図1】(a)〜(d)は本発明に係る一実施例の半導
体装置の製造方法を工程順に示すいずれも断面図。1A to 1D are cross-sectional views each showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in process order.
【図2】(a)および(b)は従来例の半導体装置の製
造方法を工程順に示すいずれも断面図。2A and 2B are cross-sectional views each showing a method of manufacturing a conventional semiconductor device in the order of steps.
【図3】本発明の方法により素子分離された素子の外観
を説明するための斜視図。FIG. 3 is a perspective view for explaining the external appearance of an element separated by the method of the present invention.
【図4】従来の方法により素子分離された素子の外観を
説明するための斜視図。FIG. 4 is a perspective view for explaining the external appearance of an element separated by a conventional method.
1、11 半導体基板 2、12 半導体導子 3、13 スクライブ予定域 4 エッチング溝 5、15 スクライバ 7 レジストパターン 8 レジスト開孔部 9、19 けがき部 1, 11 Semiconductor substrate 2, 12 Semiconductor conductor 3, 13 Scheduled scribe area 4 Etching groove 5, 15 Scriber 7 Resist pattern 8 Resist opening 9 and 19 Scribing
Claims (1)
板のスクライブ予定域に選択エッチングによりV字形の
溝を形成する工程と、前記溝内にスクライビングを施し
素子分離を行う工程とを含む半導体装置の製造方法。1. A semiconductor device comprising: a step of forming a V-shaped groove by selective etching in a planned scribe area of a semiconductor substrate on which a plurality of semiconductor elements are formed; and a step of performing element separation by scribing in the groove. Manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22540792A JPH0677318A (en) | 1992-08-25 | 1992-08-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22540792A JPH0677318A (en) | 1992-08-25 | 1992-08-25 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0677318A true JPH0677318A (en) | 1994-03-18 |
Family
ID=16828887
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22540792A Pending JPH0677318A (en) | 1992-08-25 | 1992-08-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0677318A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100863364B1 (en) * | 2005-09-26 | 2008-10-13 | 어드벤스드 칩 엔지니어링 테크놀로지, 인크. | Method for separating package of wlp |
-
1992
- 1992-08-25 JP JP22540792A patent/JPH0677318A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100863364B1 (en) * | 2005-09-26 | 2008-10-13 | 어드벤스드 칩 엔지니어링 테크놀로지, 인크. | Method for separating package of wlp |
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