JPH0677274A - Semiconductor device bonding wire - Google Patents

Semiconductor device bonding wire

Info

Publication number
JPH0677274A
JPH0677274A JP4228977A JP22897792A JPH0677274A JP H0677274 A JPH0677274 A JP H0677274A JP 4228977 A JP4228977 A JP 4228977A JP 22897792 A JP22897792 A JP 22897792A JP H0677274 A JPH0677274 A JP H0677274A
Authority
JP
Japan
Prior art keywords
wire
ceramic layer
semiconductor device
wires
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4228977A
Other languages
Japanese (ja)
Inventor
Toshinori Ishii
利昇 石井
Naoki Uchiyama
直樹 内山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP4228977A priority Critical patent/JPH0677274A/en
Publication of JPH0677274A publication Critical patent/JPH0677274A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/435—Modification of a pre-existing material
    • H01L2224/4352—Anodisation
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/438—Post-treatment of the connector
    • H01L2224/4382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/43824—Chemical solution deposition [CSD], i.e. using a liquid precursor
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/438—Post-treatment of the connector
    • H01L2224/4382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/43826—Physical vapour deposition [PVD], e.g. evaporation, sputtering
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/438—Post-treatment of the connector
    • H01L2224/4382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/43827—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/45686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/45687—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide bonding wires used for a semiconductor device, where wires are prevented from causing a short circuit even if they come into contact with each other, kept high in insulating properties, hardly clog a capillary and deteriorate in bonding properties, can be surely bonded, and hardly react with sealing resin after a semiconductor device is sealed with resin. CONSTITUTION:A ceramic layer is set in thickness 1/500 to 1/25 as large as the diameter of a wire main body, whereby wires are kept high in resistance to abrasion, the ceramic layer is hardly separated off if the wire comes into contact with a capillary, the bonded wires are kept high in insulating properties as required when they come into contact with each other, and as the ceramic layer is low in reactivity with sealing resin, it hardly reacts with sealing resin even if a semiconductor device is kept at a high temperature after it is sealed with resin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、集積回路（ＩＣ，ＬＳ
Ｉ，トランジスター等）素子上の電極と、回路配線基板
上（リードフレーム，セラミックス基板等）の導体配線
との間を接続する絶縁被覆ボンディングワイヤに関す
る。BACKGROUND OF THE INVENTION The present invention relates to an integrated circuit (IC, LS
The present invention relates to an insulation coating bonding wire for connecting between an electrode on an element (I, transistor, etc.) and a conductor wiring on a circuit wiring board (lead frame, ceramics substrate, etc.).

【０００２】[0002]

【従来の技術】従来、この種のボンディングワイヤとし
ては、直径１８〜５０μｍ程度の金または金合金製の極
細裸線が用いられていた。2. Description of the Related Art Conventionally, as this type of bonding wire, an ultrafine bare wire made of gold or a gold alloy having a diameter of about 18 to 50 μm has been used.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、上記従
来のボンディングワイヤにあっては、多様化するパッケ
ージ構造に伴い複雑化、高密度化する配線において、ワ
イヤに多少の曲がりがあっただけで、隣接する他のワイ
ヤに接触して短絡するという問題が発生していた。ま
た、ワイヤボンディング時には接触していなくても、樹
脂封止時のワイヤの流動により短絡が発生するという問
題があった。そこで、これらの問題を解決すべく、ポリ
ウレタン等の樹脂を被覆したいわゆるエナメル被覆ワイ
ヤが提案されている（例えば、特開平２−４０９２９号
公報参照）。ところが、このエナメル被覆ワイヤにおい
ては、キャピラリーとの接触により被覆材が剥離すると
いう問題、ボールアップ時に溶けた被覆材がキャピラリ
ーに詰まるという問題、さらには、樹脂封止後に高温保
存した場合に、被覆材と封止用樹脂とが反応するなど多
くの問題を抱えており、殆ど実用化に到っていない。However, in the above-described conventional bonding wire, in the wiring which becomes complicated and has a high density due to the diversified package structure, the wires are slightly bent, There was a problem of short-circuiting by contacting another wire. Further, there is a problem that a short circuit occurs due to the flow of wires during resin sealing even if they are not in contact during wire bonding. Therefore, in order to solve these problems, a so-called enamel-coated wire coated with a resin such as polyurethane has been proposed (see, for example, Japanese Patent Laid-Open No. 2-40929). However, in this enamel-coated wire, the problem that the coating material peels due to contact with the capillary, the problem that the coating material melted at the time of ball-up is clogged in the capillary, and further, when the coating is stored at high temperature after resin sealing There are many problems such as the reaction between the material and the encapsulating resin, and it has hardly been put to practical use.

【０００４】本発明は、上記事情に鑑みてなされたもの
で、その目的とするところは、ワイヤどうしが接触して
も短絡することがなく、充分な絶縁性を保持することが
できると共に、キャピラリーの詰まりや接合性を悪化さ
せることがなく、確実にボンディングすることができる
上に、樹脂封止後に封止用樹脂と反応することがない半
導体装置用ボンディングワイヤを提供することにある。The present invention has been made in view of the above circumstances, and it is an object of the present invention to prevent short-circuiting even if wires come into contact with each other and to maintain sufficient insulating properties and to provide a capillary. It is an object of the present invention to provide a bonding wire for a semiconductor device, which can surely perform bonding without causing clogging and deterioration of bondability and which does not react with a sealing resin after resin sealing.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、ワイヤ本体にセラミックス層が被覆さ
れ、かつこのセラミックス層が、上記ワイヤ本体の線径
の１／５００〜１／２５の膜厚に設定されたものであ
る。In order to achieve the above object, the present invention provides a wire body covered with a ceramic layer, and the ceramic layer is 1/500 to 1/25 of the wire diameter of the wire body. The film thickness is set to.

【０００６】[0006]

【作用】本発明の半導体装置用ボンディングワイヤにあ
っては、ワイヤ本体を被覆したセラミックス層によっ
て、充分な耐摩耗性を確保してキャピラリーと接触して
もセラミックス層が剥離することがないと共に、ボンデ
ィングされたワイヤどうしが接触しても所望の絶縁性を
発揮する一方、封止用樹脂との反応性が低いことにより
樹脂封止後に高温保存してもセラミックス層と封止用樹
脂とが反応することがない。また、ボール形成時に表面
のセラミックス層がボールに溶け込むが、上記セラミッ
クス層を、上記ワイヤ本体の線径の１／５００〜１／２
５の膜厚に設定したことにより、溶け込むセラミックス
量が制限されて、ボール硬度を著しく増加させることが
ない上に、ボールの真球性を損なうこともない。ここ
で、上記セラミックス層を、上記ワイヤ本体の線径の１
／５００〜１／２５の膜厚に設定したのは、膜厚が１／
５００より小さいと、充分な絶縁性が得られないからで
あり、また、膜厚が１／２５を越えると、製造が困難で
あるばかりか、１ｓｔボンドにおけるボールの形成及び
２ｎｄボンドにおける接合性に大きな悪影響を与え、所
定のボールの真球性が得られず、しかも２ｎｄボンドの
接合性が低下するからである。そして、これらの絶縁性
（耐電圧）や接合性は、ワイヤ本体の線径に依存するた
め、セラミックス層の膜厚の範囲限定は、ワイヤ本体の
線径の１／５００〜１／２５としている。さらに、本発
明のボンディングワイヤは、ＣＶＤ法，ゾル・ゲル法，
スパッタ法などを用いて、金または金合金製のワイヤ本
体の表面に、ＳｉＯ2，ＳｉＡｌＯＮ，ＡｌＮなどで代
表されるセラミックスを被覆することにより製造され
る。また、被覆法としては、上記方法の他に、例えば、
Ａｌを蒸着させておき、大気中で焼鈍することにより、
ワイヤ本体の表面にＡｌ2Ｏ3を形成させる方法でもよ
い。In the bonding wire for a semiconductor device of the present invention, the ceramic layer covering the wire body ensures sufficient wear resistance and does not peel off even when it comes into contact with the capillary. Even if the bonded wires come into contact with each other, the desired insulating property is exhibited, while the reactivity with the sealing resin is low, so the ceramic layer reacts with the sealing resin even when stored at high temperature after resin sealing. There is nothing to do. Further, when the ball is formed, the ceramic layer on the surface melts into the ball, but the ceramic layer is 1/500 to 1/2 of the wire diameter of the wire body.
By setting the film thickness to 5, the amount of ceramics to be melted is limited, the hardness of the ball is not significantly increased, and the sphericity of the ball is not impaired. Here, the above-mentioned ceramic layer is 1
The film thickness is set to / 500 to 1/25 when the film thickness is 1 /
If it is less than 500, sufficient insulation cannot be obtained, and if the film thickness exceeds 1/25, not only is it difficult to manufacture, but also ball formation in the 1st bond and bondability in the 2nd bond. This is because it exerts a great adverse effect, the predetermined spherical property of the ball cannot be obtained, and the bondability of the second bond is deteriorated. Since the insulating property (withstand voltage) and the bondability depend on the wire diameter of the wire body, the film thickness range of the ceramic layer is limited to 1/500 to 1/25 of the wire diameter of the wire body. . Furthermore, the bonding wire of the present invention is manufactured by the CVD method, the sol-gel method,
It is manufactured by coating the surface of a wire body made of gold or a gold alloy with a ceramic represented by SiO 2 , SiAlON, AlN or the like by using a sputtering method or the like. As the coating method, in addition to the above method, for example,
By depositing Al and annealing in the atmosphere,
A method of forming Al 2 O 3 on the surface of the wire body may be used.

【０００７】[0007]

【実施例】以下、本発明の実施例を具体的に説明する。
すなわち、直径２５μｍの金製のワイヤ本体に様々な厚
みで各種のセラミックスを被覆し、セラミックス被覆ボ
ンディングワイヤを作製した。そして、これらのボンデ
ィングワイヤについて、ボンディング性（接合率），故
意に接触させた時の電気的ショートの発生の有無，連続
ボンディングによるキャピラリーの詰まりの有無（１０
万回ボンド後のキャピラリーの状態）の評価を行った。
この結果を表１に示す。EXAMPLES Examples of the present invention will be specifically described below.
That is, a gold wire main body having a diameter of 25 μm was coated with various types of ceramics with various thicknesses to produce ceramics-coated bonding wires. With respect to these bonding wires, the bondability (bonding rate), the presence or absence of an electrical short when intentionally contacted, and the presence or absence of clogging of the capillary due to continuous bonding (10
The state of the capillary after 10,000 bondings was evaluated.
The results are shown in Table 1.

【０００８】[0008]

【表１】 [Table 1]

【０００９】この表からもわかるように、ワイヤ本体の
線径の１／５００〜１／２５、すなわち、セラミックス
の被覆厚みが０．０５〜１μｍの範囲内にあるＮｏ．１
〜８については、ボンディング性が良好で、はがれが生
じず、かつ故意に接触させてもショートの発生がなく、
しかも１０万回ボンド後のキャピラリーの状態も良好で
あった。これに対して、上記範囲を外れているＮｏ．９
〜１２のうち、セラミックスの被覆厚みが０．０５μｍ
より小さいＮｏ．９、１１については、ショートが発生
する一方、セラミックスの被覆厚みが１μｍを越えてい
るＮｏ．１０、１２については、ボンディング性が悪
く、はがれが生じた。また、Ｎｏ．１３は、被覆をして
いない従来のボンディングワイヤであり、この場合に
は、当然のことながらショートが発生した。As can be seen from this table, the wire diameter of the wire body is 1/500 to 1/25, that is, the ceramic coating thickness is in the range of 0.05 to 1 μm. 1
Regarding Nos. 8 to 8, the bonding property is good, peeling does not occur, and no short circuit occurs even if they are intentionally contacted,
Moreover, the state of the capillaries after 100,000 bondings was good. On the other hand, in the case of No. 9
~ 12, the ceramic coating thickness is 0.05 μm
Smaller No. Regarding Nos. 9 and 11, while the short circuit occurred, the coating thickness of the ceramics exceeded 1 μm. Regarding Nos. 10 and 12, the bondability was poor and peeling occurred. In addition, No. Reference numeral 13 is a conventional bonding wire that is not covered, and in this case, a short circuit naturally occurred.

【００１０】[0010]

【発明の効果】以上説明したように、本発明は、ワイヤ
本体にセラミックス層が被覆され、かつこのセラミック
ス層が、上記ワイヤ本体の線径の１／５００〜１／２５
の膜厚に設定されたものであるから、ワイヤ本体を被覆
したセラミックス層によって、充分な耐摩耗性を確保し
てキャピラリーと接触してもセラミックス層が剥離する
ことがないと共に、ボンディングされたワイヤどうしが
接触しても所望の絶縁性を発揮して短絡することがない
一方、封止用樹脂との反応性が低いことにより樹脂封止
後に高温保存してもセラミックス層と封止用樹脂とが反
応することがない。また、ボール形成時に表面のセラミ
ックス層がボールに溶け込むが、上記セラミックス層
を、上記ワイヤ本体の線径の１／５００〜１／２５の膜
厚に設定したことにより、溶け込むセラミックス量が制
限されて、ボール硬度を著しく増加させることがない上
に、ボールの真球性を損なうこともない。従って、キャ
ピラリーの詰まりや接合性を悪化させることがなく、確
実にボンディングすることができる。この結果、特に、
多ピン高密度の半導体素子において効果が大きく、電気
的ショート等による不良の発生を皆無にできるから、実
装時の歩留まりを著しく向上させることができる。As described above, according to the present invention, the wire body is covered with the ceramic layer, and the ceramic layer is 1/500 to 1/25 of the wire diameter of the wire body.
Since the ceramic layer covering the wire body ensures sufficient wear resistance, the ceramic layer does not peel off even when it comes into contact with the capillary, and the bonded wire Even if they come into contact with each other, they do not short-circuit by exhibiting the desired insulating property, but due to their low reactivity with the encapsulating resin, the ceramic layer and encapsulating resin can be stored even at high temperatures after resin encapsulation. Does not react. Further, the ceramic layer on the surface melts into the ball during ball formation, but the amount of ceramic that melts is limited by setting the thickness of the ceramic layer to 1/500 to 1/25 of the wire diameter of the wire body. In addition, the ball hardness is not significantly increased, and the sphericity of the ball is not impaired. Therefore, it is possible to perform reliable bonding without causing clogging of the capillary or deterioration of the bondability. As a result of this,
The effect is large in a multi-pin high-density semiconductor element, and the occurrence of defects due to electrical shorts and the like can be eliminated, so that the yield at the time of mounting can be significantly improved.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 ワイヤ本体にセラミックス層が被覆さ
れ、かつこのセラミックス層が、上記ワイヤ本体の線径
の１／５００〜１／２５の膜厚に設定されたことを特徴
とする半導体装置用ボンディングワイヤ。1. A bonding for a semiconductor device, characterized in that a wire body is coated with a ceramic layer, and the ceramic layer is set to a film thickness of 1/500 to 1/25 of a wire diameter of the wire body. Wire.
JP4228977A 1992-08-27 1992-08-27 Semiconductor device bonding wire Pending JPH0677274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4228977A JPH0677274A (en) 1992-08-27 1992-08-27 Semiconductor device bonding wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4228977A JPH0677274A (en) 1992-08-27 1992-08-27 Semiconductor device bonding wire

Publications (1)

Publication Number Publication Date
JPH0677274A true JPH0677274A (en) 1994-03-18

Family

ID=16884841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4228977A Pending JPH0677274A (en) 1992-08-27 1992-08-27 Semiconductor device bonding wire

Country Status (1)

Country Link
JP (1) JPH0677274A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017092816A1 (en) * 2015-12-03 2017-06-08 Osram Opto Semiconductors Gmbh Electronic chip package and production method of an electronic chip package
CN110718525A (en) * 2019-10-22 2020-01-21 烟台一诺电子材料有限公司 Insulating corrosion-resistant inorganic amorphous coating bonding wire and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017092816A1 (en) * 2015-12-03 2017-06-08 Osram Opto Semiconductors Gmbh Electronic chip package and production method of an electronic chip package
CN110718525A (en) * 2019-10-22 2020-01-21 烟台一诺电子材料有限公司 Insulating corrosion-resistant inorganic amorphous coating bonding wire and preparation method thereof

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