JPH0677232A - Bump electrode structure of semiconductor device and formation thereof - Google Patents
Bump electrode structure of semiconductor device and formation thereofInfo
- Publication number
- JPH0677232A JPH0677232A JP4247091A JP24709192A JPH0677232A JP H0677232 A JPH0677232 A JP H0677232A JP 4247091 A JP4247091 A JP 4247091A JP 24709192 A JP24709192 A JP 24709192A JP H0677232 A JPH0677232 A JP H0677232A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- semiconductor device
- hardness
- layer gold
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置のバンプ電
極構造およびその形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump electrode structure for a semiconductor device and a method for forming the bump electrode structure.
【０００２】[0002]
【従来の技術】ＴＡＢ方式と呼ばれる半導体装置（ＩＣ
チップ）の実装技術では、半導体装置をＴＡＢテープ上
に搭載している。この場合、半導体装置に金バンプを有
するバンプ電極を設け、このバンプ電極をＴＡＢテープ
のインナリードに金すず共晶法や金金熱圧着法等による
ボンディングによって接続している。2. Description of the Related Art A semiconductor device called an TAB system (IC
In the chip) mounting technology, a semiconductor device is mounted on a TAB tape. In this case, bump electrodes having gold bumps are provided on the semiconductor device, and the bump electrodes are connected to the inner leads of the TAB tape by bonding such as a gold-tin eutectic method or a gold-gold thermocompression bonding method.
【０００３】ところで、従来の金バンプの硬度は５０Ｈ
ｖ（ビッカース硬さ）以上と比較的高くなるようにして
いる。この理由は、硬度が５０Ｈｖ未満の場合には、金
バンプが軟らかくてボンディング時につぶれることがあ
り、この結果半導体装置のエッジ（シリコン等の半導体
が露出している部分）がＴＡＢテープのインナリードに
接近して接触し、このエッジを介してインナリード同士
が短絡してしまうことがあり、したがってこのような不
都合を回避するためである。By the way, the hardness of the conventional gold bump is 50H.
It is set to be relatively higher than v (Vickers hardness). The reason for this is that if the hardness is less than 50 Hv, the gold bumps may be soft and crushed during bonding, and as a result, the edge of the semiconductor device (the portion where the semiconductor such as silicon is exposed) becomes the inner lead of the TAB tape. This is because they may come into close contact with each other and the inner leads may be short-circuited to each other via this edge, and thus such an inconvenience is avoided.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
このような半導体装置のバンプ電極構造では、金バンプ
の硬度が５０Ｈｖ以上と比較的高いので、ボンディング
時における金バンプの変形量が少なく、このためボンデ
ィング時の加圧力を金バンプで十分に吸収することがで
きず、この結果半導体装置の表面に大きな圧力が加わ
り、半導体装置表面の絶縁膜や電極引き回し線にクラッ
クが生じることがあるという問題があった。また、金バ
ンプがあまり変形しないので、ＴＡＢテープのインナリ
ードとの密着性が十分に良いとはいえないという問題も
あった。この発明の目的は、ボンディング時に金バンプ
が不要につぶれることがなく、かつボンディング時の加
圧力を金バンプで十分に吸収することができ、さらにＴ
ＡＢテープのインナリードとの密着性を十分に良くする
ことのできる半導体装置のバンプ電極構造を提供するこ
とにある。この発明の他の目的は、金バンプを簡易な処
理工程で能率良く形成することのできる半導体装置のバ
ンプ電極形成方法を提供することにある。However, in the conventional bump electrode structure of such a semiconductor device, since the hardness of the gold bump is relatively high at 50 Hv or more, the deformation amount of the gold bump during bonding is small, and therefore, The pressure applied during bonding cannot be sufficiently absorbed by the gold bumps, and as a result, a large pressure is applied to the surface of the semiconductor device, which may cause cracks in the insulating film on the surface of the semiconductor device and the electrode routing lines. there were. Further, since the gold bumps do not deform so much, there is a problem that the adhesion of the TAB tape to the inner leads is not sufficiently good. An object of the present invention is to prevent the gold bumps from being unnecessarily crushed during bonding and to sufficiently absorb the pressure applied during bonding by the gold bumps.
It is an object of the present invention to provide a bump electrode structure of a semiconductor device capable of sufficiently improving the adhesion of the AB tape to the inner leads. Another object of the present invention is to provide a bump electrode forming method for a semiconductor device, which can efficiently form gold bumps by a simple processing step.
【０００５】[0005]
【課題を解決するための手段】請求項１記載の発明は、
金バンプを備えた半導体装置のバンプ電極構造におい
て、前記金バンプを、硬度が５０Ｈｖ以上の下層金バン
プと、硬度が５０Ｈｖ未満の上層金バンプとによって構
成したものである。請求項２記載の発明は、下層金バン
プと上層金バンプとからなる金バンプを備えた半導体装
置のバンプ電極の形成方法において、ある電流密度で前
記下層金バンプを形成し、次いで電流密度を下げて前記
上層金バンプを形成するようにしたものである。The invention according to claim 1 is
In a bump electrode structure of a semiconductor device including a gold bump, the gold bump is composed of a lower layer gold bump having a hardness of 50 Hv or more and an upper layer gold bump having a hardness of less than 50 Hv. According to a second aspect of the present invention, in a method of forming a bump electrode of a semiconductor device having a gold bump composed of a lower layer gold bump and an upper layer gold bump, the lower layer gold bump is formed at a certain current density, and then the current density is lowered. To form the upper gold bump.
【０００６】[0006]
【作用】請求項１記載の発明によれば、下層金バンプの
硬度が５０Ｈｖ以上と比較的高いので、ボンディング時
における下層金バンプの変形量が少なく、したがってボ
ンディング時に下層金バンプが不要につぶれることがな
く、ひいては全体としての金バンプが不要につぶれない
ようにすることができ、一方、上層金バンプの硬度が５
０Ｈｖ未満と比較的低いので、ボンディング時における
上層金バンプの変形量が大きく、したがってボンディン
グ時の加圧力を上層金バンプで十分に吸収することがで
き、またＴＡＢテープのインナリードとの密着性を十分
に良くすることができる。請求項２記載の発明によれ
ば、下層金バンプとこの下層金バンプよりも硬度の低い
上層金バンプとをメッキ電流密度を変えて形成している
ので、下層金バンプと上層金バンプとからなる金バンプ
を簡易な処理工程で能率良く形成することができる。According to the invention of claim 1, since the hardness of the lower layer gold bumps is relatively high at 50 Hv or more, the deformation amount of the lower layer gold bumps during bonding is small, and therefore the lower layer gold bumps are unnecessarily crushed during bonding. Therefore, the gold bumps as a whole can be prevented from being unnecessarily crushed, while the hardness of the upper gold bumps is 5
Since it is relatively low at less than 0 Hv, the amount of deformation of the upper gold bump during bonding is large, and therefore the pressure applied during bonding can be sufficiently absorbed by the upper gold bump, and the adhesion with the inner lead of the TAB tape can be improved. Can be good enough. According to the second aspect of the present invention, since the lower layer gold bump and the upper layer gold bump having a hardness lower than that of the lower layer gold bump are formed with different plating current densities, the lower layer gold bump and the upper layer gold bump are formed. Gold bumps can be efficiently formed by a simple process.
【０００７】[0007]
【実施例】図１はこの発明の一実施例における半導体装
置のバンプ電極構造を示したものである。このバンプ電
極構造では、シリコンウエハ１の上面にゲート電極等の
内部電極２および酸化シリコンからなる絶縁膜３が形成
されている。絶縁膜３の上面には、内部電極２と接続さ
れた接続用電極４が形成されている。接続用電極４はア
ルミニウム（Ａｌ）またはアルミニウム−けい素（Ａｌ
−Ｓｉ）、アルミニウム−銅−けい素（Ａｌ−Ｃｕ−Ｓ
ｉ）等のアルミニウム合金からなっている。接続用電極
４の周辺部および絶縁膜３の上面には窒化シリコンから
なる絶縁膜５が形成されている。したがって、接続用電
極４の中央部は絶縁膜５に形成された開口部６を介して
露出されている。この露出された接続用電極４およびそ
の周囲の絶縁膜５の上面には中間接続膜７が形成されて
いる。中間接続膜７はチタン−タングステン（Ｔｉ−
Ｗ）、白金−チタン（Ｐｔ−Ｔｉ）、パラジウム−チタ
ン（Ｐｄ−Ｔｉ）等の合金、すなわちバリアメタルと接
着メタルとの合金からなっている。中間接続膜７の上面
には金薄膜８が形成され、金薄膜８の上面には硬度が５
０Ｈｖ以上の下層金バンプ９が形成され、下層金バンプ
９の上面には硬度が５０Ｈｖ未満の上層金バンプ１０が
形成されている。FIG. 1 shows a bump electrode structure of a semiconductor device according to an embodiment of the present invention. In this bump electrode structure, an internal electrode 2 such as a gate electrode and an insulating film 3 made of silicon oxide are formed on the upper surface of a silicon wafer 1. A connection electrode 4 connected to the internal electrode 2 is formed on the upper surface of the insulating film 3. The connecting electrode 4 is made of aluminum (Al) or aluminum-silicon (Al).
-Si), aluminum-copper-silicon (Al-Cu-S)
It is made of aluminum alloy such as i). An insulating film 5 made of silicon nitride is formed on the peripheral portion of the connection electrode 4 and the upper surface of the insulating film 3. Therefore, the central portion of the connecting electrode 4 is exposed through the opening 6 formed in the insulating film 5. An intermediate connection film 7 is formed on the exposed upper surface of the connection electrode 4 and the surrounding insulating film 5. The intermediate connecting film 7 is made of titanium-tungsten (Ti-
W), platinum-titanium (Pt-Ti), palladium-titanium (Pd-Ti), and other alloys, that is, an alloy of a barrier metal and an adhesive metal. A gold thin film 8 is formed on the upper surface of the intermediate connecting film 7, and the hardness of the gold thin film 8 is 5 on the upper surface.
The lower-layer gold bumps 9 of 0 Hv or more are formed, and the upper-layer gold bumps 10 having a hardness of less than 50 Hv are formed on the upper surface of the lower-layer gold bumps 9.
【０００８】次に、このようなバンプ電極構造を形成す
る場合について図２を参照しながら説明する。まず、図
２（Ａ）に示すように、シリコンウエハ１の上面に内部
電極２および酸化シリコンからなる絶縁膜３を形成し、
絶縁膜３の上面にアルミニウムまたはアルミニウム合金
からなる接続用電極４を形成する。次に、接続用電極４
を含む絶縁膜３の上面全体に窒化シリコンからなる絶縁
膜５を形成した後、絶縁膜５の所定の個所にエッチング
により開口部６を形成することにより、接続用電極４の
周辺部および絶縁膜３の上面に絶縁膜５を残存させると
ともに、絶縁膜５の開口部６を介して接続用電極４の中
央部を露出させる。次に、チタン−タングステン等の合
金および金をこの順で蒸着またはスパッタリングするこ
とにより、上面全体に中間接続膜形成用膜７ａおよび金
薄膜形成用薄膜８ａをそれぞれ数千Å程度の厚さに形成
する。Next, a case of forming such a bump electrode structure will be described with reference to FIG. First, as shown in FIG. 2A, an internal electrode 2 and an insulating film 3 made of silicon oxide are formed on the upper surface of a silicon wafer 1,
A connection electrode 4 made of aluminum or an aluminum alloy is formed on the upper surface of the insulating film 3. Next, the connection electrode 4
After forming the insulating film 5 made of silicon nitride on the entire upper surface of the insulating film 3 including the insulating film 5, an opening 6 is formed in a predetermined portion of the insulating film 5 by etching. The insulating film 5 is left on the upper surface of the insulating film 3, and the central portion of the connecting electrode 4 is exposed through the opening 6 of the insulating film 5. Next, an alloy such as titanium-tungsten and gold are vapor-deposited or sputtered in this order to form the intermediate connection film forming film 7a and the gold thin film forming thin film 8a each having a thickness of about several thousand Å. To do.
【０００９】次に、図２（Ｂ）に示すように、金薄膜形
成用薄膜８ａの上面に、フォトレジスト液を滴下してス
ピンコーティングすることにより、フォトレジスト膜１
１を膜厚が２０〜３０μｍ程度となるように比較的厚く
形成する。この場合、フォトレジスト膜１１の膜厚を２
０〜３０μｍ程度と比較的厚くするために、フォトレジ
スト液として粘度が数百〜千数百ＣＰＳ（センチポイ
ズ）で通常のスピンコーティングのものよりも数倍ない
し数十倍高いもの（例えば東京応化工業（株）製のＢＭ
Ｒ１０００）を使用し、スピンコーティング時の回転速
度を数百ｒｐｍとする。Next, as shown in FIG. 2B, a photoresist solution is dropped onto the upper surface of the gold thin film forming thin film 8a and spin-coated to form a photoresist film 1.
1 is formed relatively thick so that the film thickness is about 20 to 30 μm. In this case, the thickness of the photoresist film 11 is set to 2
In order to make it relatively thick, such as 0 to 30 μm, the viscosity of the photoresist liquid is several hundred to several thousand and several hundred CPS (centipoise), which is several to several tens of times higher than that of ordinary spin coating (for example, Tokyo Ohka Kogyo). BM manufactured by
R1000) is used, and the rotation speed during spin coating is several hundred rpm.
【００１０】次に、フォトレジスト膜１１を所定のマス
クを介して露光して現像することにより、図２（Ｃ）に
示すように、フォトレジスト膜１１の所定の個所つまり
図１に示す下層金バンプ９および上層金バンプ１０を形
成すべき領域に対応する部分に開口部１２を形成する。
この場合、現像液としてはキシレンを主成分とする有機
溶剤（例えば東京応化工業（株）製のＣ−３）を用い
る。次に、開口部１２内に金を電解メッキすることによ
り、開口部１２内の金薄膜形成用薄膜８ａの上面に下層
金バンプ９を形成し、次いで図２（Ｄ）に示すように、
下層金バンプ９の上面に上層金バンプ１０を形成する。
この場合、下層金バンプ９を形成する時のメッキ電流密
度を８ｍＡ／ｃｍ2程度とし、上層金バンプ１０を形成
する時のメッキ電流密度を２ｍＡ／ｃｍ2程度とする。
すると、図３に示す金メッキにおける電流密度に対する
硬度の関係から明らかなように、この時点における硬度
が下層金バンプ９で９５Ｈｖ程度となり、上層金バンプ
１０で７０Ｈｖ程度となる。なお、上層金バンプ１０の
上面を平坦とするために、下層金バンプ９と上層金バン
プ１０と金薄膜形成用薄膜８ａの合計膜厚を２０〜３０
μｍ程度とし、上層金バンプ１０の上面がフォトレジス
ト膜１１の上面から突出しないようにする。また、上層
金バンプ１０の膜厚は、下層金バンプ９と上層金バンプ
１０の合計膜厚の１／４〜１／２とする。次に、２００
〜３００℃程度の温度下で３０分〜１時間程度の加熱処
理を行ない、これにより下層金バンプ９の硬度を９５Ｈ
ｖ以下で５０Ｈｖ以上望ましくは５０Ｈｖ以上で８０Ｈ
ｖ以下とし、上層金バンプ１０の硬度を５０Ｈｖ未満望
ましくは３０Ｈｖ以上で５０Ｈｖ未満とする。Next, the photoresist film 11 is exposed to light through a predetermined mask and developed, so that a predetermined portion of the photoresist film 11, that is, the lower layer metal shown in FIG. 1 is formed as shown in FIG. 2C. An opening 12 is formed in a portion corresponding to a region where the bump 9 and the upper gold bump 10 are to be formed.
In this case, an organic solvent containing xylene as a main component (for example, C-3 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is used as the developer. Next, the lower layer gold bump 9 is formed on the upper surface of the gold thin film forming thin film 8a in the opening 12 by electrolytically plating gold in the opening 12, and then, as shown in FIG.
The upper gold bump 10 is formed on the upper surface of the lower gold bump 9.
In this case, the plating current density when forming the lower layer gold bumps 9 is about 8 mA / cm 2, and the plating current density when forming the upper layer gold bumps 10 is about 2 mA / cm 2 .
Then, as is clear from the relationship between the current density and the hardness in the gold plating shown in FIG. 3, the hardness at this time is about 95 Hv for the lower layer gold bump 9 and about 70 Hv for the upper layer gold bump 10. In order to make the upper surface of the upper-layer gold bump 10 flat, the total thickness of the lower-layer gold bump 9, the upper-layer gold bump 10 and the gold thin film forming thin film 8a is set to 20 to 30.
The upper surface of the upper layer gold bump 10 does not project from the upper surface of the photoresist film 11. The film thickness of the upper layer gold bumps 10 is set to 1/4 to 1/2 of the total film thickness of the lower layer gold bumps 9 and the upper layer gold bumps 10. Then 200
A heat treatment is performed at a temperature of about 300 ° C. for about 30 minutes to 1 hour, whereby the hardness of the lower layer gold bump 9 is 95H.
50 V or more at v or less, preferably 80 H at 50 Hv or more
The hardness of the upper layer gold bumps 10 is set to v or less, and the hardness of the upper layer gold bump 10 is set to be less than 50 Hv, preferably 30 Hv or more and less than 50 Hv.
【００１１】次に、フォトレジスト膜１１をエチルセル
ソルブ、ジクロルベンゼンを主成分とする有機溶剤（例
えば東京応化工業（株）製の剥離液ＳＰ）を用いて剥離
すると、図２（Ｅ）に示すようになる。次に、下層金バ
ンプ９および上層金バンプ１０をマスクとして金薄膜形
成用薄膜８ａの不要な部分をヨウ素系のエッチング液で
エッチングして除去し、次いで同様に下層金バンプ９お
よび上層金バンプ１０をマスクとして中間接続膜形成用
膜７ａの不要な部分をドライエッチングして除去する
と、図１に示すバンプ電極構造が得られる。なお、チタ
ン−タングステン合金からなる中間接続膜形成用膜７ａ
のエッチングは、フロン系ガスを用いた反応性イオンエ
ッチングが好ましい。その理由は、絶縁膜４の残り量が
少ない場合の高精度のエッチングに適するとともに、ア
ンダーカットを防止することができるからである。Next, the photoresist film 11 is stripped using ethyl cellosolve and an organic solvent containing dichlorobenzene as a main component (for example, a stripping solution SP manufactured by Tokyo Ohka Kogyo Co., Ltd.). As shown in. Next, using the lower layer gold bumps 9 and the upper layer gold bumps 10 as masks, unnecessary portions of the gold thin film forming thin film 8a are removed by etching with an iodine-based etching solution, and then the lower layer gold bumps 9 and the upper layer gold bumps 10 are similarly removed. When the unnecessary portion of the intermediate connection film forming film 7a is removed by dry etching using the as a mask, the bump electrode structure shown in FIG. 1 is obtained. The intermediate connecting film forming film 7a made of titanium-tungsten alloy
The etching is preferably reactive ion etching using a fluorocarbon gas. The reason is that it is suitable for highly accurate etching when the remaining amount of the insulating film 4 is small, and can prevent undercut.
【００１２】次に、図４および図５を参照して、上記の
ように構成された半導体装置のバンプ電極をＴＡＢテー
プのインナーリードに接続する場合について説明する。
まず、上述した処理工程を経た後シリコンウエハ１はダ
イシングにより切断され、複数の半導体装置２１に分割
される。ここで、１つの半導体装置２１には上述した下
層金バンプ９および上層金バンプ１０からなる金バンプ
が複数配列されている。一方、ＴＡＢテープ２２の複数
のインナーリード２３は、表面に半田２３ａがメッキさ
れた銅箔２３ｂをベーステープ２４上にラミネートした
後エッチングして所定の形状にパターン形成したものか
らなり、ベーステープ２４に形成されたデバイスホール
２５内に突出されている。この場合、銅箔２３ｂの表面
にメッキされた半田２３ａは、すず（Ｓｎ）と鉛（Ｐ
ｂ）との混合比が８０：２０の合金からなり、その厚さ
が０．２〜０．６μｍ程度となっている。Next, with reference to FIGS. 4 and 5, the case where the bump electrodes of the semiconductor device configured as described above are connected to the inner leads of the TAB tape will be described.
First, after passing through the above-described processing steps, the silicon wafer 1 is cut by dicing and divided into a plurality of semiconductor devices 21. Here, in one semiconductor device 21, a plurality of gold bumps including the lower layer gold bumps 9 and the upper layer gold bumps 10 described above are arranged. On the other hand, the plurality of inner leads 23 of the TAB tape 22 are formed by laminating a copper foil 23b having a surface on which solder 23a is plated on a base tape 24 and then etching the same to form a pattern into a predetermined shape. And is projected into the device hole 25 formed in. In this case, the solder 23a plated on the surface of the copper foil 23b is made of tin (Sn) and lead (Pn).
It is made of an alloy having a mixing ratio of 80:20 with b) and has a thickness of about 0.2 to 0.6 μm.
【００１３】さて、半導体装置２１のバンプ電極をＴＡ
Ｂテープ２２のインナーリード２３に接続する場合に
は、半導体装置２１をデバイスホール２５内に配置し、
各バンプ電極の上層金バンプ１０をそれぞれ対応するイ
ンナーリード２３に、温度２００〜４００℃、加圧力３
０〜３６０ｇ／ｍｍ2、時間１〜５ｓｅｃの条件でボン
ディングする。この場合、下層金バンプ９の硬度が５０
Ｈｖ以上と比較的高いので、ボンディング時における下
層金バンプ９の変形量が少なく、したがってボンディン
グ時に下層金バンプ９が不要につぶれることがなく、ひ
いては全体としての金バンプが不要につぶれないように
することができる。この結果、半導体装置２１のエッジ
とインナリード２３との間隔を保つことができ、したが
って半導体装置２１のエッジがインナリード２３に接触
しないようにすることができる。また、上層金バンプ１
０の硬度が５０Ｈｖ未満と比較的低いので、ボンディン
グ時における上層金バンプ１０の変形量が大きく、した
がってボンディング時の加圧力を上層金バンプ１０で十
分に吸収することができ、ひいては半導体装置２１の表
面に大きな圧力が加わることがなく、半導体装置２１の
表面の絶縁膜３、５や接続用電極４の引き回し線にクラ
ックが生じないようにすることができる。また、ボンデ
ィング時における上層金バンプ１０の変形量が大きいの
で、ＴＡＢテープ２２のインナリード２３との密着性を
十分に良くすることができる。さらに、下層金バンプ９
とこの下層金バンプ９よりも硬度の低い上層金バンプ１
０とをメッキ電流密度を変えて形成しているので、下層
金バンプ９と上層金バンプ１０とからなる金バンプを簡
易な処理工程で能率良く形成することができる。The bump electrode of the semiconductor device 21 is set to TA.
When connecting to the inner lead 23 of the B tape 22, the semiconductor device 21 is placed in the device hole 25,
The upper layer gold bump 10 of each bump electrode is applied to the corresponding inner lead 23 at a temperature of 200 to 400 ° C. and a pressing force of 3
Bonding is performed under the conditions of 0 to 360 g / mm 2 and time of 1 to 5 sec. In this case, the hardness of the lower gold bump 9 is 50.
Since it is relatively high as Hv or more, the deformation amount of the lower layer gold bumps 9 at the time of bonding is small, so that the lower layer gold bumps 9 are not crushed unnecessarily at the time of bonding, and thus the gold bumps as a whole are not crushed unnecessarily. be able to. As a result, the distance between the edge of the semiconductor device 21 and the inner lead 23 can be maintained, and thus the edge of the semiconductor device 21 can be prevented from contacting the inner lead 23. Also, the upper gold bump 1
Since the hardness of 0 is relatively low, which is less than 50 Hv, the amount of deformation of the upper layer gold bump 10 during bonding is large, and therefore the pressing force during bonding can be sufficiently absorbed by the upper layer gold bump 10 and, by extension, the semiconductor device 21 A large pressure is not applied to the surface, and it is possible to prevent cracks from being generated in the wiring lines of the insulating films 3 and 5 and the connection electrode 4 on the surface of the semiconductor device 21. In addition, since the amount of deformation of the upper layer gold bump 10 during bonding is large, the adhesion of the TAB tape 22 to the inner leads 23 can be sufficiently improved. In addition, the lower gold bump 9
And the upper layer gold bump 1 having a hardness lower than that of the lower layer gold bump 9
Since 0 and 0 are formed with different plating current densities, gold bumps composed of the lower layer gold bumps 9 and the upper layer gold bumps 10 can be efficiently formed by a simple processing step.
【００１４】なお、半導体装置２１のバンプ電極をＴＡ
Ｂテープ２２のインナーリード２３に接続した後は、半
導体装置２１上に図示しない保護用レジンをポッティン
グして、このポッティングした保護用レジンによって半
導体装置２１を覆って保護し、この後図４において二点
鎖線で示す部分で切断することになる。The bump electrode of the semiconductor device 21 is TA
After connecting to the inner lead 23 of the B tape 22, a protective resin (not shown) is potted on the semiconductor device 21, and the potted protective resin covers and protects the semiconductor device 21. It will be cut at the part indicated by the dotted chain line.
【００１５】[0015]
【発明の効果】以上説明したように、請求項１記載の発
明によれば、下層金バンプの硬度が５０Ｈｖ以上と比較
的高いので、ボンディング時に下層金バンプが不要につ
ぶれないようにすることができ、この結果半導体装置の
エッジがＴＡＢテープのインナリードに接触しないよう
にすることができる。また、上層金バンプの硬度が５０
Ｈｖ未満と比較的低いので、ボンディング時の加圧力を
上層金バンプで十分に吸収することができ、この結果半
導体装置表面の絶縁膜や電極引き回し線にクラックが生
じないようにすることができ、またＴＡＢテープのイン
ナリードとの密着性を十分に良くすることができる。ま
た、請求項２記載の発明によれば、下層金バンプとこの
下層金バンプよりも硬度の低い上層金バンプとをメッキ
電流密度を変えて形成しているので、下層金バンプと上
層金バンプとからなる金バンプを簡易な処理工程で能率
良く形成することができる。As described above, according to the first aspect of the present invention, since the hardness of the lower layer gold bump is 50 Hv or more, which is relatively high, it is possible to prevent the lower layer gold bump from being unnecessarily crushed during bonding. As a result, the edge of the semiconductor device can be prevented from coming into contact with the inner lead of the TAB tape. Also, the hardness of the upper gold bump is 50
Since the pressure is less than Hv, which is relatively low, the pressure applied during bonding can be sufficiently absorbed by the upper-layer gold bumps, and as a result, it is possible to prevent cracks from occurring in the insulating film and the electrode wiring lines on the semiconductor device surface. Further, the adhesion of the TAB tape to the inner leads can be sufficiently improved. According to the second aspect of the present invention, since the lower layer gold bump and the upper layer gold bump having a hardness lower than that of the lower layer gold bump are formed with different plating current densities, the lower layer gold bump and the upper layer gold bump are formed. The gold bumps made of can be efficiently formed by simple processing steps.
【図１】この発明の一実施例における半導体装置のバン
プ電極構造の断面図。FIG. 1 is a sectional view of a bump electrode structure of a semiconductor device according to an embodiment of the present invention.
【図２】（Ａ）〜（Ｅ）はそれぞれこの半導体装置のバ
ンプ電極構造の各形成工程の断面図。2A to 2E are cross-sectional views of respective steps of forming a bump electrode structure of this semiconductor device.
【図３】金メッキにおける電流密度に対する硬度の関係
を示す図。FIG. 3 is a diagram showing a relationship between hardness and current density in gold plating.
【図４】この半導体装置のバンプ電極をＴＡＢテープの
インナーリードに接続した状態の平面図。FIG. 4 is a plan view showing a state in which bump electrodes of this semiconductor device are connected to inner leads of a TAB tape.
【図５】図４の一部の断面図。5 is a cross-sectional view of a portion of FIG.
９ 下層金バンプ １０ 上層金バンプ ２３ インナーリード 9 Lower layer gold bump 10 Upper layer gold bump 23 Inner lead
Claims (2)
極構造において、 前記金バンプを、硬度が５０Ｈｖ以上の下層金バンプ
と、硬度が５０Ｈｖ未満の上層金バンプとによって構成
したことを特徴とする半導体装置のバンプ電極構造。1. A bump electrode structure for a semiconductor device having a gold bump, wherein the gold bump is composed of a lower layer gold bump having a hardness of 50 Hv or more and an upper layer gold bump having a hardness of less than 50 Hv. Bump electrode structure for semiconductor devices.
金バンプを備えた半導体装置のバンプ電極の形成方法に
おいて、 ある電流密度で前記下層金バンプを形成し、次いで電流
密度を下げて前記上層金バンプを形成することを特徴と
する半導体装置のバンプ電極の形成方法。2. A method of forming a bump electrode of a semiconductor device having a gold bump composed of a lower layer gold bump and an upper layer gold bump, wherein the lower layer gold bump is formed at a certain current density, and then the current density is reduced to form the upper layer gold bump. A method of forming a bump electrode of a semiconductor device, which comprises forming a gold bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24709192A JP3446021B2 (en) | 1992-08-25 | 1992-08-25 | Bump electrode structure of semiconductor device and method for forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24709192A JP3446021B2 (en) | 1992-08-25 | 1992-08-25 | Bump electrode structure of semiconductor device and method for forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0677232A true JPH0677232A (en) | 1994-03-18 |
| JP3446021B2 JP3446021B2 (en) | 2003-09-16 |
Family
ID=17158300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24709192A Expired - Fee Related JP3446021B2 (en) | 1992-08-25 | 1992-08-25 | Bump electrode structure of semiconductor device and method for forming the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3446021B2 (en) |
Cited By (7)
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|---|---|---|---|---|
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| US6518649B1 (en) * | 1999-12-20 | 2003-02-11 | Sharp Kabushiki Kaisha | Tape carrier type semiconductor device with gold/gold bonding of leads to bumps |
| KR100378919B1 (en) * | 1999-04-28 | 2003-04-08 | 가부시키가이샤 무라타 세이사쿠쇼 | Surface acoustic wave device having bump electrodes and method for producing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100378919B1 (en) * | 1999-04-28 | 2003-04-08 | 가부시키가이샤 무라타 세이사쿠쇼 | Surface acoustic wave device having bump electrodes and method for producing the same |
| US6518649B1 (en) * | 1999-12-20 | 2003-02-11 | Sharp Kabushiki Kaisha | Tape carrier type semiconductor device with gold/gold bonding of leads to bumps |
| KR100361084B1 (en) * | 2000-01-21 | 2002-11-18 | 주식회사 하이닉스반도체 | Semiconductor package and fabricating method thereof |
| JP2006086532A (en) * | 2004-09-15 | 2006-03-30 | Samsung Electronics Co Ltd | Microelectronic element chip containing hybrid gold bump, its package, liquid crystal display device containing it, and manufacturing method of such microelectronic element chip |
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| US10974524B2 (en) | 2009-09-11 | 2021-04-13 | Seiko Epson Corporation | Recording method |
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