JPH0677127A - Compound semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve controllability of threshold voltages of FETs in producing FETs having different threshold voltages and resistor elements from a single wafer by forming an epitaxially grown layer of varying thickness on a single wafer with good controllability. CONSTITUTION:The fundamental structure of a HIGFET is obtained such that a gate electrode 8 is formed by working a refractory gate metal, an n-type semiconductor regions 5 are formed by ion implantation using the gate electrode 8 as a mask, and a source electrode 6 and a drain electrode 7 are formed on those regions. The threshold voltage of a HIGFET varies with the crystal thickness. Since the thickness of an epitaxially grown layer is a function of the selective growth rate, it is possible to precisely vary the thickness of a growing layer on a wafer surface by means of the selective growth rate. That is, threshold voltages of HIGFETs can be varied by controlling the selective growth rate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art HEMT (High Electron Mobility Tra)
nsistor) and HIGFET (Hetrostructure I
A compound semiconductor device using an epitaxial layer such as a nsulated gate field effect transistor) has characteristics of ultrahigh frequency and ultrahigh speed operation, and is used as a single unit or as a circuit in which these are integrated. In a conventional FET using an epitaxial layer, first, an epitaxial crystal layer is grown on the entire surface of a wafer, and a required element region is separated by mesa to form an element.

[0003]

In the FET, it is necessary to accurately match the threshold voltage with the design value. However, there are factors that change this in the following items. (1)
Variations in the film thickness and carrier concentration of the growth layer during epitaxial crystal growth, (2) Crystal thickness reduction and carrier concentration change during gate formation, and (3) Characteristic variation after gate formation.

Therefore, in order to reduce these, a great deal of consideration has been given to the construction of the process, but there remains a problem that the control cannot be performed on the device or the process, and in the past, the fluctuation range of the threshold voltage was previously set. Understand, make wafers with different specifications adjusted by the thickness of the growth layer and carrier concentration during epitaxial crystal growth, make prototypes using these, and select only those whose threshold voltage is within the design allowable range. I was using it. Therefore, as a result, there is a disadvantage that useless wafers are generated and the yield is not increased.

Further, an integrated circuit is generally constructed by using FETs and resistors having different threshold voltages. Therefore, in the conventional technique, the epitaxial crystal growth layer has the same thickness on the entire surface of the wafer. Therefore, when FETs or resistance elements having different threshold voltages are manufactured from this wafer, the crystal is ion-implanted. It was necessary to add a complicated process such as adjusting the carrier concentration or shaving the crystal. For this reason, the number of manufacturing days is increased, and the controllability of the threshold voltage is further deteriorated by this process.

The present invention has been made to solve the above problems.

[0007]

In the present invention, the above-mentioned problems are solved by obtaining an epitaxial crystal growth layer having a different thickness in the same wafer surface with good controllability.

For this reason, the present invention uses the principle that the film thickness of the epitaxial crystal growth layer obtained by selective growth has different values depending on the size of the pattern and the density of the pattern. For example, in the case of GaAs selective growth, about 1
A region in which crystals are grown in a division of a size of 00 × 100 μm ² (this is called a basic cell and this area is represented by s ₀ ) (this is called a window, and the total window area is represented by s)
And this ratio s / s ₀ (this is called the selective growth rate, s
/ S ₀ ) and the growth film thickness t are shown in FIG. From now on, compared to the total grown film thickness of s / s ₀ = 1
In the region where the selective growth rate is small, the grown film thickness becomes thick (about 3
It is understood that the grown film thickness can be varied within this range.

This area dependency is investigated in advance in detail about the apparatus and growth conditions (temperature, gas composition, gas species, etc.), and a database is provided, and based on this, element design is carried out to obtain a desired threshold voltage. It has become possible to form many types of FETs on the same wafer. In reality, the width of the film to be changed is about ± 50% with respect to the central value. When a mixed crystal such as GaAlAs is obtained by selective growth, the film thickness of the epitaxial crystal growth layer and the composition of the mixed crystal change depending on the size of the pattern and the density of the pattern. However, since the change in the composition ratio is not so large as to change the characteristics of the FET, it is sufficient to pay attention to the change in the film thickness in this case as well.

[0010]

The selective growth is performed by the vapor phase epitaxial growth technique. The surface before the selective growth is composed of a mask material region of, for example, SiO ₂ in order to prevent crystal growth, and a region of the crystal surface exposed by removing a part of the mask material and opening a window. The raw material for crystal growth that has reached the surface region of the SiO ₂ mask material floats because it has no nucleus for crystal growth here, moves to the region of the crystal plane, and grows there. Therefore, the raw material for crystal growth gathers in a region where the selective growth rate is small, and a thick growth layer can be obtained. At the growth temperature of 700 ° C., in the case of GaAs, the distance that the raw material for crystal growth can move through the SiO ₂ mask material is about 200 μm. In the present invention, the area of the basic cell is determined within a distance in which the raw material for crystal growth can move the mask material, and the relationship between the selective growth rate and the thickness of the growth layer is determined based on this, and these growth layers are used. And various elements are configured.

[0011]

EXAMPLES Example 1 HI used for GaAs IC
A cross-sectional view of the GFET is shown in FIG. A SiO ₂ mask material 2 is deposited on the surface of the semi-insulating substrate 1 to open a desired window, and a crystal selectively epitaxially grown 3 or 4 is used only in this portion. FIG. 3 shows the details of this crystal, which is mainly composed of a buffer layer and an active layer, and is composed of an undoped GaAs buffer layer 101, p on a substrate crystal 100.
This is a structure in which a -GaAs barrier layer 102, an n + -GaAs channel layer 103, and an undoped GaAlAs / GaAs cap layer 104/105 are sequentially grown.

In the HIGFET, a high heat resistant gate metal (for example, WSix) is processed on the HIGFET to form a gate electrode 8. The n-type semiconductor layer 5 is formed by ion implantation using this as a mask, and these regions are formed in these regions. Each is based on the structure obtained by the process of forming the source electrode 6 and the drain electrode 7. The threshold voltage of the HIGFET changes depending on the crystal thicknesses tn, ta and tc shown in FIG. Therefore, as described in FIG. 1, since the thickness t of the epitaxial growth layer is a function of the selective growth rate, it is possible to precisely change the thickness of the growth layer within the wafer surface by the selective growth rate. It is possible to change the threshold voltage of the HIGFET by controlling the.

FIG. 4 shows an example of a pattern for controlling and changing the thickness t of the epitaxial growth layer. This is a pattern and a cross-sectional view of a region in a wafer on which crystal growth has been seen from above. Each of the basic cells A, B, and C has an area of s ₀ and is covered with the SiO ₂ mask material 42. The windows a, b, and c are opened in these, respectively, and these are s
The area relation is ₁ <s ₂ <s ₃ . As a result, the thickness t of the epitaxial growth layer is t as shown in the sectional view.
The relationship is ₁ > t ₂ > t ₃ . When the FET is formed in each of these crystal regions, the magnitude of the threshold voltage is increased.
(Absolute value) is obtained by the relationship of Vt ₁ > Vt ₂ > Vt ₃ . An example of the size of the basic cell is 50 × 50 μm ² . In this case, the selective growth rates are s ₁ / s ₀ , s ₂ / s ₀ , s ₃ /
It is represented by s ₀ and is in a relatively narrow range (eg 40, 50, 60
%), The fluctuation of the threshold voltage becomes small. If this is selected in advance as a variation range of the threshold voltage that cannot be controlled on the device or in the process, it is possible to make an FET in which the threshold voltage is within the design allowable range in the same wafer.

As a result, wasteful wafers that cannot be used are eliminated, and the yield is remarkably improved. This is a method to form FET arrays with different threshold voltages by one-time selective growth.
A large number of these are arranged in the structure of the integrated circuit, the threshold voltage of each single element is measured before forming the wiring layer, and only the element closest to the design value is selected and wired by the configuration method.
A yield of 00% can be achieved. Although the FET arrays having different threshold voltages have been described in detail in this embodiment, it goes without saying that a diode array or a resistance element array may be added thereto.

<Embodiment 2> Different from Embodiment 1, another example of changing the growth area in the basic cell will be described. 5 and 6 are top views of a partial region in the wafer. Each of these is composed of a growth region (area sr) for FET and a dummy pattern region (area sd) for adjusting growth area in a basic cell (area s ₀ = a × b).

The example of FIG. 5 has a structure in which the spacing g is adjusted to change the selective growth rate (sd + sr) / s ₀ . In the example of FIG. 6, the size m and the interval g are adjusted so that the selective growth rate (sr + Σs
This is a structure for changing d) / s ₀ . Here, only the basic structure for changing the selective growth rate is shown, and the shape and size of the basic cell, FET, and dummy pattern are not limited from the point of the present invention. Further, two or more element crystal growth layers may be provided and used in the basic cell.

<Embodiment 3> The present invention is applied to E-FET and DF.
A basic configuration example of an integrated circuit configured by using the ET and the resistance element (R) will be described.

FIG. 7 shows an outline of these elements alone as seen from the upper surface and cross section of the wafer, which is in a state before the circuit is formed. An element in which current does not flow between the source and drain with a gate voltage of 0 V is represented by E-FET, and an element through which current flows is represented by D-FET. These elements may be formed by the difference in crystal film thickness as shown in FIG. it can. Similarly, in the resistance element, the sheet resistance is determined by the difference in the crystal film thickness, so that an element having an arbitrary value can be formed. These crystal film thicknesses can be adjusted on the same wafer by changing the selective growth rate as described in the first and second embodiments. As a result, the process of the integrated circuit can be greatly simplified as compared with the conventional method.

Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the material and structure for crystal growth, and the same crystal layer such as GaAs MESFET, HEMT or HIGFET can be used. InG like
It goes without saying that the present invention is applied to an aAs-based heterojunction crystal layer or the like. Also, the selective growth rate in selective crystal growth has been expressed in units of basic cells, but this basic cell does not necessarily have to have the same area in the wafer, and if the basics of changing the thickness are clear. good.

[0020]

The effects of the compound semiconductor device and the manufacturing method according to the present invention are as follows.

(1) Since regions having different crystal film thicknesses can be arbitrarily formed in the same wafer, it is possible to obtain devices having different characteristics by one production at a time. As a result, even if the threshold voltage changes due to process variations, FET arrays with different threshold voltages, diode arrays with different rising voltages and withstand voltages, and resistance element arrays with different sheet resistances should be placed in the design value. A 100% yield can be achieved by selecting and using only close elements.

(2) Since regions having different crystal film thicknesses can be arbitrarily formed in the same wafer, it becomes possible to obtain devices having different characteristics by one production at a time. As a result, FETs and resistance elements having different threshold voltages can be arbitrarily formed, and an integrated circuit having a high yield can be obtained by integrating these elements in a wiring layer with a smaller number of steps than in the prior art.

(3) Since regions having different crystal film thicknesses can be selectively and arbitrarily formed in the same wafer, it becomes possible to obtain devices having different characteristics by one production at a time. As a result, since the regions of the respective elements are separated, the unevenness in the wafer is reduced, and an integrated circuit with a high yield can be obtained with less man-hours than the conventional one.

[Brief description of drawings]

FIG. 1 is a characteristic diagram based on experimental results of a selective growth rate and a grown film thickness used in the present invention.

FIG. 2 is a sectional view of a HIGFET used in Example 1 of the present invention.

FIG. 3 is a sectional view of a crystal structure of a HIGFET used in Example 1 of the present invention.

FIG. 4 is a cross-sectional view showing the shapes of basic cells having different selective growth rates used in Example 1 of the present invention.

FIG. 5 is an explanatory diagram of the shape of a basic cell used in Example 2 of the present invention.

FIG. 6 is an explanatory diagram of the shape of another basic cell used in Example 2 of the present invention.

FIG. 7 is an explanatory diagram of the shapes of two types of FETs and resistance elements having different threshold voltages used in Example 3 of the present invention.

[Explanation of symbols]

_2, 42, 52, 62 ... SiO ₂ mask material, 40, 5
0, 60 ... Basic cell, 3, 4, 101, 102, 10
3, 104, 105 ... Epitaxial crystal layer, 8, 78
... gate electrode, 6,76 ... source electrode, 7,77 ... drain electrode.

Claims (6)

[Claims] 1. A compound semiconductor device characterized in that regions having different crystal film thicknesses are arbitrarily provided in the same wafer by at least one epitaxial growth. 2. The compound semiconductor device according to claim 1, wherein the selective growth film thickness is controlled by adjusting the ratio of the area covered by the material serving as the selective growth mask. 3. The design according to claim 1, wherein an area mainly having a different crystal film thickness is arbitrarily provided in the same wafer by at least one epitaxial growth, and these areas are arranged as a FET array, a diode array or a resistance element array. A compound semiconductor device that selects and uses only the element closest to the value. 4. An area mainly having a different crystal film thickness is arbitrarily provided in the same wafer by at least one epitaxial growth, and FETs having different threshold voltages, diodes having different rising voltages and withstand voltages, and resistors having different resistance values are provided. A compound semiconductor device which is arranged as an element and which is used to form an integrated circuit. 5. A step of forming a material serving as a mask for selective growth on a compound semiconductor substrate, opening an arbitrary window standardized by the selective growth rate to expose a crystal plane, and obtaining an epitaxial crystal growth layer. A step and a step of forming an FET, a diode or a resistance element using these crystal growth layers,
A method of manufacturing a compound semiconductor device, which comprises a wiring process for connecting these elements. 6. A step of forming a material serving as a mask for selective growth on a compound semiconductor substrate, opening an arbitrary window standardized by a selective growth rate to expose a crystal plane, and obtaining an epitaxial crystal growth layer. A method of manufacturing a compound semiconductor device, which comprises steps and steps of forming an FET, a diode, or a resistance element using these crystal growth layers.