KR100269394B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR100269394B1 KR100269394B1 KR1019930017839A KR930017839A KR100269394B1 KR 100269394 B1 KR100269394 B1 KR 100269394B1 KR 1019930017839 A KR1019930017839 A KR 1019930017839A KR 930017839 A KR930017839 A KR 930017839A KR 100269394 B1 KR100269394 B1 KR 100269394B1
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- pad
- gate
- gates
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005137 deposition process Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 12
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
제1도는 일반적인 HEMT구조도.1 is a general HEMT structure diagram.
제2도는 본 발명의 반도체 소자 구조도,2 is a structural diagram of a semiconductor device of the present invention,
제3도는 본 발명의 반도체 소자 제조공정도.3 is a semiconductor device manufacturing process diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : SI-GaAs기판 2 : 언도우프드 GaAS1: SI-GaAs substrate 2: Undoped GaAS
3 : 언도 우프드 AlGaAs 4 : n+-AlGaAs3: Undoped AlGaAs 4: n + -AlGaAs
5 : n+-GaAs 7 : 소오스5: n + -GaAs 7: Source
8 : 드레인 9,10A,10B : 게이트8: drain 9, 10A, 10B: gate
11 : 제1패 드 12 : 제2패드11: first pad 12: second pad
13 : 패시베이션막 14 : 본딩패드13: passivation film 14: bonding pad
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 HEMT(High Electron Mobility Transistor)구조를 채용한 2개의 게이트를 갖는 트랜지스터의 제조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a transistor having two gates employing a HEMT (High Electron Mobility Transistor) structure.
제1도에 종래의 HEMT(High Election Mobility Transistor)구조를 도시하였다. 제1도에 나타낸 바와 같이 종래의 HEMT구조는 SI-GaAs기판(1)위에 언도우프드(Undoped) GaAs(2), 언도우프드 AlGaAs(3), n+-AlGaAs(4), n+-GaAs(5)를 차례로 에피택셜 성장시켜 형성후, 메사에칭(Mesa etching)을 하여 소자간 분리를 행한 다음 소오스(7)와 드레인(8)을 형성하여 오믹접촉이 되도록 하고, 게이트 형성을 위한 사진식각공정을 행하여 리세스 에칭(Recess etching)을 실시한 후 이부분에 게이트(9)를 형성함으로써 이루어진다.FIG. 1 illustrates a conventional HEMT (High Election Mobility Transistor) structure. As shown in FIG. 1, the conventional HEMT structure has an undoped GaAs (2), an undoped AlGaAs (3), n + -AlGaAs (4), n + -on the SI-GaAs substrate (1) After GaAs (5) is formed by epitaxial growth in order, the elements are separated by mesa etching, and then source (7) and drain (8) are formed to be in ohmic contact. The etching process is performed by recess etching, and then the gate 9 is formed in this portion.
상기한 HEMT구조에 있어서는 언도우프드 AlGaAs층(3)과 언도우프드 GaAs층(2) 사이에 물리적으로 생기는 2차원 전자가스(Two-Dimension Electron Gas)를 게이트에 인가되는 전압에 의해 게이트 아래 흐르는 전자의 수를 조절함으로써 소오스와 드레인 사이의 전류를 조절하게 된다.In the above HEMT structure, a two-dimensional electron gas, which is physically generated between the undoped AlGaAs layer 3 and the undoped GaAs layer 2, flows under the gate by a voltage applied to the gate. By controlling the number of electrons, you control the current between the source and drain.
상기 종래의 HEMT는 1개의 게이트에 의해 1개의 HEMT가 동작하는 단순한 동작특성을 가지고 있고, 트랜지스터이외의 소자로는 전용이 불가능하며, 드레인과 소오스 패드가 일정하게 정해져 있다.The conventional HEMT has a simple operation characteristic in which one HEMT operates by one gate, cannot be converted to a device other than a transistor, and a drain and a source pad are fixed.
본 발명은 한개의 소자내에 2개의 HEMT를 집적할 수 있으며 , HEMT이외에도 애더(Adder) 및 로직트랜지스터등으로도 사용이 가능한 반도체 소자의 제조방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for fabricating a semiconductor device in which two HEMTs can be integrated in one device and can be used as an adder, a logic transistor, etc. in addition to the HEMT.
상기 목적을 달성하기 위해 본 발명은 기판(1)의 소정부위를 V형으로 에칭하는 단계와, 상기 기판상에 반도체층들(2,3,4,5)을 차례로 성장시키는 단계, 상기 반도체층들의 소정부분을 메사에칭하는 단계, 상기 반도체층위에 전극용 패드(11,12)를 형성하는 단계, 상기 기판의 V형으로 에칭된 영역상에 경사 증착공정에 의해 동시에 2개의 게이트(10)를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of etching a predetermined portion of the substrate (1) in V-type, and growing the semiconductor layers (2, 3, 4, 5) in order on the substrate, the semiconductor layer Mesa etching a predetermined portion of the electrodes, forming pads 11 and 12 for electrodes on the semiconductor layer, and simultaneously forming two gates 10 by a gradient deposition process on the V-etched region of the substrate. It provides a method for manufacturing a semiconductor device comprising the step of forming.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도(a)와 (b)에 본 발명의 V형 이중게이트를 갖는 반도체 소자의 수직구조도 및 평면레이아웃을 각각 나타내었고, 제3도에 이의 제조방법을 공정순서에 따라 나타내었다.2A and 2B respectively show a vertical structure diagram and a planar layout of a semiconductor device having a V-type double gate of the present invention, and FIG. 3 shows a manufacturing method thereof according to a process sequence.
본 발명의 트랜지스터는 일반적인 HEMT의 에피텍셜층구조를 이용하여 제조된다. 먼저, 제3(a)도와 같이 SI-GaAs기판(1)을 포토레지스트(PR)을 이용하여 소정부위를 V형으로 에칭한 후, 제3도(b)와 같이 V형으로 에칭된 기판(1)상에 언도우프드 GaAs(2), 언도우프드 AlGaAs(3), n+-AlGaAs(4), n+-GaAs(5)를 MOCVD(Metal Organic Chemical Vapor Deposition)법을 이용하여 순차적으로 에피텍셜 성장시킨다.The transistor of the present invention is manufactured using the epitaxial layer structure of a general HEMT. First, as shown in FIG. 3 (a), the SI-GaAs substrate 1 is etched into a V-type using a photoresist PR, and then the substrate is etched into a V-type as shown in FIG. 1) Phase undoped GaAs (2), undoped AlGaAs (3), n + -AlGaAs (4), n + -GaAs (5) in sequence using MOCVD (Metal Organic Chemical Vapor Deposition) method Epitaxial growth.
이어서 제3도(c)와 같이 사진식각공정을 이용하여 상기 결과물의 수정부분을 메사에칭하여 소자간 분리를 행한다.Subsequently, the element is separated by mesa etching the modified portion of the resultant product using a photolithography process as shown in FIG.
다음에 제2도(b)에 도시된 제1패드(11)와 제2패드(12)를 형성하기 위해 포토레지스트를 적용한 사진식각공정을 행한 후 금속을 증착하고 리프트 오프(lift-off)공정을 거쳐 패드제작을 완성한다.(패드 형성공정은 제3도에는 도시되지 않음)Next, after forming a photolithography process using a photoresist to form the first pad 11 and the second pad 12 shown in FIG. 2 (b), a metal is deposited and a lift-off process. The pad manufacturing process is completed through the process (the pad forming process is not shown in FIG. 3).
이어서 제3도(d)와 같이 소오스 전극(7) 및 드레인 전극(8)을 형성하여 오믹접촉이 이루어지도록 한 후, 결과물전면에 포토레지스트(PR)를 도포하고 게이트 패턴으로 패터닝한 다음 마스크로 상기 n+-GaAs층(5)을 선택적으로 제거한다.Subsequently, as shown in FIG. 3 (d), the source electrode 7 and the drain electrode 8 are formed to make ohmic contact, and then the photoresist PR is applied to the entire surface of the resultant, patterned with a gate pattern, and then masked. The n + -GaAs layer 5 is selectively removed.
이때 n+-GaAs층(5)과 n+-AlGaAs(4)의 선택적 에칭효과를 갖는 에쳔트(Etchant)를 사용하여 에칭을 하게 되면 n+-GaAs만 에칭이 되고 언더컷(Undercut)효과를 이용 하면 제3도(d)의 게이트 영역과 같은 에칭 프로파일을 얻을 수 있다.In this case, when etching using an etchant having a selective etching effect of n + -GaAs layer (5) and n + -AlGaAs (4), only n + -GaAs is etched and the undercut effect is used. The etching profile as shown in FIG. 3D can be obtained.
이어서 경사각도 증착(angle evaporation)기술을 이용하여 2개의 게이트(10)을 동시에 형성한다.Subsequently, two gates 10 are simultaneously formed using an angle evaporation technique.
다음에 제3도(e)와 같이 리프트 오프 공정에 의해 상기 포토레지스트(PR) 및 그 상부의 게이트 형성물질(10)을 제거한 후, 결과물상에 패시베이션막(13)을 증착하고 소정부분을 선택적으로 제거하여 개구부를 형성한 다음 금도금(Au-plating)공정을 거쳐 본딩패드(14)를 형성함으로써 소자를 완성한다.Next, the photoresist PR and the gate forming material 10 thereon are removed by a lift-off process as shown in FIG. 3 (e), and then, the passivation film 13 is deposited on the resultant, and a predetermined portion is selectively selected. After the removal, the opening is formed, and then the bonding pad 14 is formed through an Au-plating process to complete the device.
이와 같이 제조된 소자는 일반적인 HEMT동작외에도 애더(Adder), 로직 트랜지스터등의 동작이 가능하다.The device manufactured as described above may operate an adder, a logic transistor, or the like in addition to the general HEMT operation.
먼저, HEMT로서의 동작을 살펴보면 제2도(b)에서 제2패드(12)를 소오스로 하고 제1패드(11)를 드레인으로 하면 제1게이트(10A)와 제2게이트(10B)의 전압을 조절함으로써 각기 다른 2개의 신호를 뽑아낼 수 있는 2개의 HEMT가 존재하는 소자로 사용할 수 있다.First, as an HEMT, when the second pad 12 is sourced and the first pad 11 is drained in FIG. 2 (b), the voltages of the first gate 10A and the second gate 10B are reduced. By adjusting, it can be used as a device with two HEMTs that can extract two different signals.
또한, 애더(Adder)로서는 제2패드(12)를 도통시키고 제1패드(11)에 전압을 인가하여 제1게이트(10A)과 제2게이트(10B)사이의 전압을 조절함으로써 제2패드로 흐르는 전류의 양이 제2패드에서 흐르는 전류와 합쳐져서 출력으로 나오므로 애더로서 사용이 가능하다.In addition, as an adder, the second pad 12 is conducted and a voltage is applied to the first pad 11 to adjust the voltage between the first gate 10A and the second gate 10B to the second pad. Since the amount of current flowing is combined with the current flowing in the second pad and outputted, it can be used as an adder.
또한, 로직 트랜지스터로서는 제2도(b)의 제1패드(11)에 전압을 걸고 제1게이트(10A)가 온(ON), 제2게이트(1B)가 오프(OFF)이면 제2패드와 제1패드가 동시에 오프되며, 제1게이트가 오프되고 제2게이트가 온되면 제2패드는 온, 제1패드는 오프가 되고, 제1게이트와 제2게이트가 동시에 온이면 모든 패드는 오프가 되고 제1게이트와 제2게이트가 오프이면 모든 패드는 동시에 온이되어 로직 트랜지스터로서도 사용이 가능하다.As the logic transistor, if the first pad 11 of FIG. 2 (b) is energized and the first gate 10A is ON and the second gate 1B is OFF, the second pad and When the first pad is turned off at the same time and the first gate is turned off and the second gate is turned on, the second pad is turned on and the first pad is turned off. When the first and second gates are turned on at the same time, all the pads are turned off. When the first gate and the second gate are off, all the pads are turned on at the same time and can be used as logic transistors.
이와 같이 1개의 소자로서 외부에서 인가하는 패드를 바꾸어주면 HEMT, 애더(Adder), 로직 트랜지스터등으로 다양하게 사용할 수 있다.As described above, if the pad applied from the outside is changed as one element, it can be used in various ways such as HEMT, adder, logic transistor, and the like.
이상 상술한 바와 같이 본 발명은 1개의 소자를 형성하는 공정에 의해 각기 출력을 다르게 낼 수 있는 HEMT 2개를 집적시키는데 효율적이며, 공정 또한 매우 간단하다.As described above, the present invention is efficient in integrating two HEMTs capable of different outputs by the process of forming one element, and the process is also very simple.
또한 HEMT외에도 애더 또는 로직트랜지스터로도 전용하여 사용하는 것이 가능하다.In addition to HEMT, it can be used exclusively as an adder or a logic transistor.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930017839A KR100269394B1 (en) | 1993-09-06 | 1993-09-06 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930017839A KR100269394B1 (en) | 1993-09-06 | 1993-09-06 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950010140A KR950010140A (en) | 1995-04-26 |
| KR100269394B1 true KR100269394B1 (en) | 2000-10-16 |
Family
ID=19363005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930017839A KR100269394B1 (en) | 1993-09-06 | 1993-09-06 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100269394B1 (en) |
-
1993
- 1993-09-06 KR KR1019930017839A patent/KR100269394B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR950010140A (en) | 1995-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4599790A (en) | Process for forming a T-shaped gate structure | |
| US4711858A (en) | Method of fabricating a self-aligned metal-semiconductor FET having an insulator spacer | |
| JP2599381B2 (en) | Method of manufacturing FET device | |
| US5362677A (en) | Method for producing a field effect transistor with a gate recess structure | |
| KR100939037B1 (en) | ENHANCEMENT AND DEPLETION-MODE PHEMT DEVICE HAVING TWO InGaP ETCH-STOP LAYERS AND METHOD OF FORMING SAME | |
| WO2002031886A1 (en) | Monolithically integrated e/d mode hemt and method for fabricating the same | |
| KR0163833B1 (en) | Method of fabricating semiconductor device | |
| KR100269394B1 (en) | Manufacturing method of semiconductor device | |
| US5541424A (en) | Permeable base transistor having laminated layers | |
| US20080064155A1 (en) | Method for Producing a Multi-Stage Recess in a Layer Structure and a Field Effect Transistor with a Multi-Recessed Gate | |
| US5483089A (en) | Electrically isolated MESFET | |
| JP2658171B2 (en) | Method for manufacturing field effect transistor | |
| JP2504785B2 (en) | Semiconductor integrated circuit and manufacturing method thereof | |
| JP2914429B2 (en) | Manufacturing method of semiconductor integrated circuit | |
| US5177026A (en) | Method for producing a compound semiconductor MIS FET | |
| JPH05190574A (en) | Field effect transistor | |
| KR100304869B1 (en) | Method for manufacturing field effect transistor | |
| JPH07142685A (en) | Semiconductor integrated circuit device and manufacture thereof | |
| JPS61163664A (en) | Manufacture of semiconductor device | |
| JPS62115782A (en) | Manufacture of semiconductor device | |
| JPS58107677A (en) | Semiconductor device | |
| JPS5898974A (en) | Vertical mis-fet and manufacture thereof | |
| JPH04217329A (en) | Fabrication of field effect transistor | |
| JPH03293733A (en) | Manufacture of semiconductor device | |
| JPS6143443A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20070629 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |