JPH067672B2 - Switching position correction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VTR servo system, and relates to a switching position correction circuit that corrects a phase of a reproduced vertical synchronizing signal and a head switching timing so as to be appropriate.

[Background of the Invention]

In the VTR according to the VHS standard, the reproduced vertical synchronizing signal is 5H to 8 in the horizontal cycle from the head switching timing.
It is supposed to be located at a time delayed by H minutes. Therefore, even when the video signal is recorded on the tape, the vertical synchronizing signal is controlled to be located at 5H to 8H from the head switching phase.

An example of the conventional device will be described below. First, the relationship between the conventional switching pulse and the vertical synchronizing signal will be described.

FIG. 3 shows a tape running state according to the VHS standard. In the figure, 1 is a cylinder, which rotates in the direction of arrow a. 2 is a tape, which advances in the direction of arrow b. 3 is a video head, and 4 is a magnet for changing the position of the head into an electric signal. The magnet 4 has one S pole and one N pole, and is positioned so as to precede the video head 3 in the rotation direction.

Reference numeral 5 denotes a tack head for detecting the passage of a magnet, which is located at the beginning of winding the tape around the cylinder 1. Therefore, when the magnet 4 passes the tack head 5, it coincides with the time when the video head 3 corresponding to the magnet 4 starts to hit the tape.

The signal output from the tack head 5 is input to the block circuit shown in FIG. Note that FIG. 5 shows a time chart of signals of main parts of FIG.

By using the block circuit shown in FIG. 4 and the VHS reference tape, the above conventional device has a vertical synchronizing signal of 5H to 8H.
The block circuit is adjusted so that it comes to 6.5 H in the middle of the above. That is, the tack pulse signal detected by the tack head 5 is input to the tack pulse detection circuit 9 and the positive and negative tack pulse signals 6a, 6 which are the outputs thereof.
b is input to the mono multivibrator (MM) 10 and MM 11, respectively. The positive / negative tack pulse signal 6a
And 6b are MM1s each having a time constant of R ₂ C _2.
It is delayed by MM11 with a time constant of 0, R ₁ C ₁ as shown at 7 in FIG. The delayed signal is R
It is input to the S flip-flop circuit 12, and the switching pulse waveform shown in FIG. 5 is output. The time constants of R ₁ C ₁ and R ₂ C ₂ of MM10 and MM11 are changed so that the vertical synchronizing signal is recorded at a position delayed by 5H to 8H, preferably 6.5H from the switching position.

However, in some cases, the recording was initially adjusted to 5H to 8H due to temperature characteristics, aging, and the like, but the recording may be performed at 5H or less or 8H or more. At this time, when this is reproduced, it is naturally reproduced at 5H or less or 8H or more.

For this reason, when reproduced at 3H or less, the vertical sync signal comes to be positioned before the pseudo sync pulse during high-speed search and still image reproduction, causing vertical pitching on the screen. Also, 9
When it is higher than H, there is a drawback that a switching horizontal line due to vertical synchronization appears on the lower side of the reproduction screen.

[Object of the Invention]

An object of the present invention is to provide a switching position correction circuit in which a recorded vertical synchronizing signal always comes to a position delayed by 5H to 8H from a switching point.

[Summary of the Invention] A feature of the present invention is that a phase difference between a switching pulse and a reproduced vertical synchronizing signal has a predetermined phase width (for example, 5H to 8H).
H) is detected, and when it is not within the phase width, the switching delay amount is corrected so as to be within the phase width.

Example of Invention

The present invention will be described below with reference to examples. In the present invention, the time constant of the multivibrator of the above-mentioned conventional circuit is switched according to the phase of the reproduced vertical synchronizing switching pulse.

FIG. 1 shows a block diagram of an embodiment of the present invention. Also,
The waveform of the signal of the main part of FIG. 1 is shown in FIG. In FIG. 1, the two correction circuits A ₁ and A ₂ surrounded by a dotted line have the same configuration as each other, and therefore the description of the configuration and operation will be given below with reference to _one correction circuit A _1. To do. The same reference numerals as those in FIG. 4 indicate the same or equivalent items.

A switching pulse 8 output from the RS flip-flop circuit 12 having the waveform shown in 8 of FIG.
Is input to the gate circuit 14 of the _first correction circuit A ₁ .
The gate circuit 14 operates by a signal applied to the input terminal 13 of the gate circuit 14 when the servo becomes stable after loading, and becomes conductive. The switching pulse 8 enters the MM15 and is delayed by 5H by the time constant of the MM15. The waveform of the output signal 23 of the MM 15 becomes a high level signal with a pulse width of 0 to 5H, as shown in FIG. This signal 23 is input to one input terminal of the latch circuit 18.

The output of the MM15 is inverted by the inverter,
Input to MM16. The MM 16 produces a signal 24 which goes high during 5H-8H, as shown in FIG. The signal 24 is inverted by the inverter and then input to the MM 17. The MM 17 produces a signal 25 which becomes high level between 8H and several tens H as shown in FIG. 2, and the signal 25 is inputted to one input terminal of the latch circuit 19.

The vertical synchronizing signal 20 separated from the reproduced signal is input to the other input terminal of each of the latch circuits 18 and 19. Therefore, if the reproduced vertical synchronizing signal 20 is between 0 and 5H from the switching point, as shown in 20a of FIG. 2, the two inputs of the latch circuit 18 become high level and the latch Circuit 1
A high signal is output from 8. Similarly, as shown in 20b of FIG. 2, if the reproduced vertical synchronizing signal 20 is at 8H or higher, two inputs of the latch circuit 19 become high level, and the latch circuit 19 outputs high level. Signal is output.

Now, as described above, the reproduced vertical synchronizing signal 20 is
If the output signal of the latch circuit 18 is at the H level between the switching point and 0 to 5H, both the transistors Q ₁ and Q ₂ connected to the output side of the latch circuit 18 are turned on. Therefore, the resistance R ₃ is added in parallel to the resistance R ₁ of the time constant circuit of the MM 11, and the delay amount of the MM 11 is reduced. Therefore, the switching point corresponding to the trailing edge of the switching pulse 8 is advanced, and the vertical synchronizing signal can be separated from the switching point by 5H or more.

On the other hand, if the reproduced vertical synchronizing signal 20 is 8H or more from the switching point and the output signal of the latch circuit 19 becomes H level, the transistor Q ₃ connected to the output side of the latch circuit 19 is Turn on. Therefore, since the capacitor C ₃ is connected in parallel with the capacitor C ₁ of the time constant circuit of the MM 11, the time constant becomes large and M
The delay amount of M11 becomes large and the switching point becomes slow. Therefore, the interval between the switching point and the vertical synchronizing signal can be shortened and corrected to 8H or less.

As is apparent, the correction amount H number can be arbitrarily selected by the values of the resistor R ₃ and the capacitor C ₃ . The latched state of the latch circuits 18 and 19 is released by the stop signal 21 generated when the tape running is completed.

The second correction circuit A ₂ includes the RS flip-flop circuit 1
The switching pulse 8 output from 2 is input through the inverter 22. The second correction circuit A ₂ operates in the same manner as the first correction circuit A _1, and corrects the time constant of the MM 10 to delay or accelerate the rising of the switching pulse 8. Therefore, the interval between the switching point corresponding to the rising edge of the switching pulse 8 and the reproduced vertical synchronizing signal is 5H to 8H.
It is corrected so that it is in the interval.

When the timing of the reproduced vertical synchronizing signal is between 5H and 8H from the switching point, neither of the latch circuits 18 and 19 is turned on, and M
It will be clear that operation continues with the time constants M10 and MM11 have.

As described above, according to this embodiment, the interval between the switching points corresponding to the falling and rising edges of the switching pulse and the reproduced vertical synchronizing signal is always 5H to 8H.
It can be corrected to be in between.

〔The invention's effect〕

As described above, according to the present invention, the phase of the recorded vertical synchronizing signal with respect to the switching pulse is 5H to 8H.
Even if it is not within the range, it can be corrected so that it comes within 5H to 8H, the vertical pitch of the screen during variable speed playback or the exposure of the switching horizontal line at the bottom of the screen can be maintained, and a good image can always be obtained. it can.

[Brief description of drawings]

FIG. 1 is a block diagram of a switching point correction circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of signals of main parts of FIG. 1, FIG. 3 is a tape running diagram around a cylinder, and FIG. FIG. 5 is a block diagram of a conventional head switching circuit, and FIG. 5 is a timing chart of signals of main parts of FIG. 1 ... cylinder, 2 ... tape, 3 ... video head,
4 ... Magnet, 5 ... Tack head, 9 ... Tack pulse detection circuit, 10, 11 ... MM, 12 ... RS flip-flop circuit, 14 ... Gate circuit, 15, 1
6, 17 ... MM, 18, 19 ... Latch circuit, 20 ...
… Vertical sync signal, 21 …… Stop signal

Claims (3)

[Claims] 1. A tack pulse detected by a tack head, and delay means for delaying the tack pulse by a predetermined amount.
In a switching position correction circuit having a switching pulse generating means having an output of the delay means as an input, the phase difference between the switching pulse output from the switching pulse generating means and the reproduced vertical synchronizing signal is within a predetermined phase width. Means for detecting whether the phase is included or not included in the phase width, and a delay of the delay means so as to be included in the phase width when the phase is not included in the phase width. A switching position correction circuit comprising means for correcting the amount. 2. The switching position correction circuit according to claim 1, wherein the phase width is 5H to 8H (where H is a horizontal period). 3. The switching position correction circuit according to claim 1, wherein the delay amount of the delay means is corrected by changing the time constant of the delay means.