JPH0676659A - Manufacture of flat cable circuit - Google Patents

Manufacture of flat cable circuit

Info

Publication number
JPH0676659A
JPH0676659A JP25405092A JP25405092A JPH0676659A JP H0676659 A JPH0676659 A JP H0676659A JP 25405092 A JP25405092 A JP 25405092A JP 25405092 A JP25405092 A JP 25405092A JP H0676659 A JPH0676659 A JP H0676659A
Authority
JP
Japan
Prior art keywords
circuit pattern
metal foil
punched
flat cable
punching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25405092A
Other languages
Japanese (ja)
Other versions
JP3245231B2 (en
Inventor
Juichi Nishiyama
寿一 西山
Takao Sugita
孝夫 杉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Cable Industries Ltd
Original Assignee
Mitsubishi Cable Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Cable Industries Ltd filed Critical Mitsubishi Cable Industries Ltd
Priority to JP25405092A priority Critical patent/JP3245231B2/en
Publication of JPH0676659A publication Critical patent/JPH0676659A/en
Application granted granted Critical
Publication of JP3245231B2 publication Critical patent/JP3245231B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To form a circuit pattern of a flat cable at small intervals. CONSTITUTION:Metal foil 12 laminated over a carrier tape 11 by a laminator 13 is punched along a circuit pattern by the punch die 16a of a half-cut press 14a. The metal foil is then punched by the punch die 16b of a half-cut press 14b along a new circuit pattern complementing the preformed circuit pattern so as to refine the circuit pattern, and then the unnecessary portion 12' of the metal foil 12 is removed using a winding roller 15.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、各種電気機器の配線に
使用されるフラットケーブル回路の製造方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a flat cable circuit used for wiring various electric devices.

【0002】[0002]

【従来の技術】従来、この種のフラットケーブルの回路
パターンを形成するためには、例えば図5に示すよう
に、キャリアテープ1上に金属箔2をラミネータ3によ
り積層し、ハーフカットプレス4によって金属箔2のみ
を回路パターンに応じて打ち抜き、残りの不要部2’を
巻取りローラ5に巻き付けて除去している。この金属箔
2を打ち抜くためには、図6に示すような複数の切刃6
a、6bをスペーサ7を介して木型8に埋め込んだ所謂
ビク型が用いられる。この切刃6a、6bとしては、図
6(a) に示すように刃先の両面が傾斜した両面型の切刃
6aや、図6(b) に示すように刃先の片面のみが傾斜し
た片面型の切刃6bが用いられ、それぞれ打ち抜くべき
回路パターンの間隔等に応じて組み合わされるようにな
っている。
2. Description of the Related Art Conventionally, in order to form a circuit pattern of this type of flat cable, for example, as shown in FIG. 5, a metal foil 2 is laminated on a carrier tape 1 by a laminator 3 and a half cut press 4 is used. Only the metal foil 2 is punched out according to the circuit pattern, and the remaining unnecessary portion 2 ′ is wound around the winding roller 5 and removed. In order to punch out this metal foil 2, a plurality of cutting blades 6 as shown in FIG.
A so-called big mold in which a and 6b are embedded in a wooden mold 8 via a spacer 7 is used. As the cutting blades 6a and 6b, a double-sided cutting blade 6a in which both surfaces of the cutting edge are inclined as shown in FIG. 6 (a) or a single-sided cutting edge in which only one surface of the cutting edge is inclined as shown in FIG. 6 (b) Cutting blades 6b are used and are combined according to the intervals of the circuit patterns to be punched.

【0003】[0003]

【発明が解決しようとする課題】しかしながら上述した
従来方法では、昨今のように接続するコネクタ等が小型
になるにつれ、フラットケーブルの回路パターンの間隔
を狭くしなければならず、切刃6a、6bの刃先間隔P
1、P2、P3を狭くする必要があるが、ビク型の構造上か
ら刃先間隔P1、P2、P3を狭くするにも限度があり、細か
い回路パターンを形成することが不可能な状態が生じて
いる。
However, in the above-mentioned conventional method, as the connectors and the like to be connected become smaller in size as in recent years, it is necessary to narrow the distance between the circuit patterns of the flat cable, and the cutting edges 6a, 6b. Blade edge spacing P
It is necessary to narrow 1, P2, P3, but there is a limit to narrowing the cutting edge pitch P1, P2, P3 due to the structure of the Viku type, and it is impossible to form a fine circuit pattern. There is.

【0004】これを解決するためには、放電加工により
微細な構造を造り得る金型を使用することも考えられる
が、金型は価格が高く経済的に大きな負担となる。
In order to solve this, it is possible to use a mold capable of forming a fine structure by electric discharge machining, but the mold is expensive and becomes a heavy economical burden.

【0005】本発明の目的は、上述の問題点を解消し、
従来のビク型を用いて細かい回路パターンを形成するこ
とができるフラットケーブル回路の製造方法を提供する
ことにある。
The object of the present invention is to solve the above problems,
It is an object of the present invention to provide a method for manufacturing a flat cable circuit capable of forming a fine circuit pattern by using a conventional Biku type.

【0006】[0006]

【課題を解決するための手段】上述の目的を達成するた
めの本発明に係るフラットケーブル回路の製造方法は、
フラットケーブル製造過程における積層された金属箔を
打ち抜いて回路パターンを形成する場合において、前記
金属箔の同一領域を別個の抜き型により複数回に分けて
打ち抜くことを特徴とするものである。
A method of manufacturing a flat cable circuit according to the present invention for achieving the above-mentioned object, comprises:
When the laminated metal foils are punched out to form a circuit pattern in the flat cable manufacturing process, the same region of the metal foils is punched in plural times by separate punching dies.

【0007】[0007]

【作用】上述の構成を有するフラットケーブル回路の製
造方法は、金属箔を打ち抜く抜き型を複数個用意し、金
属箔の同一領域を複数回に分けて打ち抜くことにより、
細かな回路パターンを形成する。
According to the method of manufacturing the flat cable circuit having the above-described structure, a plurality of punching dies for punching the metal foil are prepared, and the same region of the metal foil is punched in a plurality of times.
Form a fine circuit pattern.

【0008】[0008]

【実施例】本発明を図1〜図4に図示の実施例に基づい
て詳細に説明する。図1は本実施例の工程図であり、キ
ャリアテープ11と金属箔12が移動する方向には順
に、キャリアテープ11と金属箔12を積層するための
ラミネータ13、積層された金属箔12のみを打ち抜く
ためのハーフカットプレス14a、14b、そして打ち
抜かれた金属箔12の不要部12’を巻き取るための巻
取ローラ15が設けられている。また、ハーフカットプ
レス14aには図2に示すような打ち抜くべき回路パタ
ーンに対応する切刃パターンの抜き型16aが設けら
れ、同様にハーフカットプレス14bには図3に示すよ
うな回路パターンの抜き型16bに対応する切刃パター
ンが設けられている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the embodiments shown in FIGS. FIG. 1 is a process chart of this embodiment, in which only a laminator 13 for laminating the carrier tape 11 and the metal foil 12 and only the laminated metal foil 12 are arranged in the moving direction of the carrier tape 11 and the metal foil 12. Half-cut presses 14a and 14b for punching, and a take-up roller 15 for taking up the unnecessary portion 12 'of the punched metal foil 12 are provided. Further, the half-cut press 14a is provided with a cutting die 16a having a cutting edge pattern corresponding to the circuit pattern to be punched as shown in FIG. 2, and similarly, the half-cut press 14b is provided with a circuit pattern punch as shown in FIG. A cutting edge pattern corresponding to the mold 16b is provided.

【0009】ここで、図2に示す回路パターンの打抜部
A1、A2、A3、A4と、図3に示す回路パターンの打抜部B
1、B2、B3、B4は、抜き型16a、16bの周囲に設け
られた位置決め部17を合致させることにより、最終的
に図4に示すように交互に入り込んだ打抜部A1、B1、A
2、B2、A3、B3、A4、B4が形成されるようになってい
る。
Here, the punching portion of the circuit pattern shown in FIG.
A1, A2, A3, A4 and punched part B of the circuit pattern shown in FIG.
1, B2, B3, and B4 are punched parts A1, B1, and A, which finally enter alternately as shown in FIG. 4, by matching the positioning parts 17 provided around the punching dies 16a and 16b.
2, B2, A3, B3, A4, B4 are formed.

【0010】即ち、金属箔12は先ずハーフカットプレ
ス14aの抜き型16aよって図2に示すような回路パ
ターンに打ち抜かれ、打抜部A1、A2、A3、A4が形成され
る。次に、この打抜部A1〜A4を設けた金属箔12が移動
してハーフカットプレス14bの下に位置決め部17を
用いて正確に位置決めされ、金属箔12は抜き型16b
によって図3に示すような回路パターンが打ち抜かれる
と、図4に示すような打抜部A1、B1、A2、B2、A3、B3、
A4、B4を有する間隔の狭い回路パターンが打ち抜かれる
ことになる。この打ち抜かれた金属箔12の不要部1
2’を巻取ローラ15に巻き取って除去することによ
り、間隔の狭い所望の回路パターンが得られる。
That is, the metal foil 12 is first punched by the punching die 16a of the half-cut press 14a into a circuit pattern as shown in FIG. 2 to form punched portions A1, A2, A3, A4. Next, the metal foil 12 provided with the punched parts A1 to A4 is moved and accurately positioned using the positioning part 17 under the half-cut press 14b, and the metal foil 12 is removed from the die 16b.
When the circuit pattern as shown in FIG. 3 is punched by, the punching parts A1, B1, A2, B2, A3, B3, as shown in FIG.
A circuit pattern with a narrow interval having A4 and B4 is punched out. The unnecessary portion 1 of the punched metal foil 12
By winding 2'on the winding roller 15 and removing it, a desired circuit pattern having a narrow interval can be obtained.

【0011】なお、本実施例では2台のハーフカットプ
レス14a、14bを使用しているが、ハーフカットプ
レスを更に増加することにより、更に細かい回路パター
ンを形成することが可能である。
Although two half-cut presses 14a and 14b are used in this embodiment, it is possible to form a finer circuit pattern by further increasing the number of half-cut presses.

【0012】[0012]

【発明の効果】以上説明したように本発明に係るフラッ
トケーブル回路の製造方法は、複数の抜き型を用いて、
順次に先の打ち抜きで形成した回路パターンを補完する
ように打ち抜くことにより、細かな回路パターンを形成
することができる。
As described above, the method for manufacturing a flat cable circuit according to the present invention uses a plurality of punching dies,
Fine circuit patterns can be formed by sequentially punching so as to complement the circuit patterns formed by the preceding punching.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例の工程図である。FIG. 1 is a process drawing of an example.

【図2】抜き型の回路パターンの平面図である。FIG. 2 is a plan view of a punching circuit pattern.

【図3】抜き型の回路パターンの平面図である。FIG. 3 is a plan view of a punching circuit pattern.

【図4】完成した回路パターンの平面図である。FIG. 4 is a plan view of a completed circuit pattern.

【図5】従来例の工程図である。FIG. 5 is a process diagram of a conventional example.

【図6】ビク型の断面図である。FIG. 6 is a cross-sectional view of a Viku type.

【符号の説明】[Explanation of symbols]

11 キャリアテープ 12 金属箔 13 ラミネータ 14a、14b ハーフカットプレス 15 巻取ローラ 16a、16b 抜き型 11 Carrier Tape 12 Metal Foil 13 Laminator 14a, 14b Half Cut Press 15 Winding Roller 16a, 16b Die

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 フラットケーブル製造過程における積層
された金属箔を打ち抜いて回路パターンを形成する場合
において、前記金属箔の同一領域を別個の抜き型により
複数回に分けて打ち抜くことを特徴とするフラットケー
ブル回路の製造方法。
1. In the case of forming a circuit pattern by punching out laminated metal foils in a flat cable manufacturing process, the same region of the metal foils is punched out in a plurality of times by separate punching dies. Cable circuit manufacturing method.
JP25405092A 1992-08-28 1992-08-28 Manufacturing method of flat cable circuit Expired - Fee Related JP3245231B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25405092A JP3245231B2 (en) 1992-08-28 1992-08-28 Manufacturing method of flat cable circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25405092A JP3245231B2 (en) 1992-08-28 1992-08-28 Manufacturing method of flat cable circuit

Publications (2)

Publication Number Publication Date
JPH0676659A true JPH0676659A (en) 1994-03-18
JP3245231B2 JP3245231B2 (en) 2002-01-07

Family

ID=17259538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25405092A Expired - Fee Related JP3245231B2 (en) 1992-08-28 1992-08-28 Manufacturing method of flat cable circuit

Country Status (1)

Country Link
JP (1) JP3245231B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003037427A (en) * 2001-07-24 2003-02-07 Dainippon Printing Co Ltd Manufacturing method of antenna pattern
JP2007506277A (en) * 2003-09-17 2007-03-15 アクレオ アーベー Method and apparatus for manufacturing electrical components and laminated structures
JP2009523635A (en) * 2006-01-24 2009-06-25 マイクロラボ ピーティーワイ エルティーディー Stamping method and apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003037427A (en) * 2001-07-24 2003-02-07 Dainippon Printing Co Ltd Manufacturing method of antenna pattern
JP2007506277A (en) * 2003-09-17 2007-03-15 アクレオ アーベー Method and apparatus for manufacturing electrical components and laminated structures
US7919027B2 (en) 2003-09-17 2011-04-05 Webshape Ab Methods and devices for manufacturing of electrical components and laminated structures
JP2009523635A (en) * 2006-01-24 2009-06-25 マイクロラボ ピーティーワイ エルティーディー Stamping method and apparatus

Also Published As

Publication number Publication date
JP3245231B2 (en) 2002-01-07

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