JPH067652B2 - Communication control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device of a communication system using a transmission medium that can be simultaneously transmitted by a plurality of devices, and in particular to a communication medium on the transmission medium by the self-address of each device. The present invention relates to a communication control device whose priority is determined.

[Background of the Invention]

2. Description of the Related Art With the widespread use of household electric appliances with built-in microcomputers, various so-called home automation systems have been proposed in which various devices in the home are mutually connected to perform centralized control and the like. One of them is the home bus system (HB) from KEC (Kansai Electronics Industry Promotion Center).
S) standardization proposal has been announced. This is September 1983
It is described in "About HBS (Home Bus System)" by Murata and Namegawa in Material Number SC-83-41 at the Society of Electrical Engineers, System and Control Study Group on the 30th. Further, regarding the control procedure and the collision detection in the baseband of this system, page 3A-2- of the Electronic Industrial Technology Conference Conference 3A Home Automation System data, October 7, 1983, "About HBS baseband" by Honda.
5, 3A-2-6. This HBS
The circuit block diagram for realizing the system is as shown in Fig. 1. In the figure, 1 is an arithmetic processing unit (hereinafter abbreviated as CPU), 2 is parallel data converted into serial data and output to a home bus. Or a serial interface circuit that converts serial data on the home bus to parallel data,
Reference numeral 3 is a transmission control circuit for detecting collision on the bus and transmission control, 4 is a switch for self-address setting, 5 is a 3-state buffer, 6 is a resistor for keeping a high level even when the switch is off, 7 is a data bus, 8 Is a bus line such as a home bus. In such a home bus system, each device has a self-address setting switch 4 so that the number of connected devices can be easily increased or decreased, and the user can freely set the device when connecting the device to the home bus. ing. Now, considering the case where certain information is sent to the home bus 8 and sent to another device, first, the CPU 1 sets the switch 4
The self-address (set to hexadecimal 53 in FIG. 1) set in step 1 is read through the buffer 5. In KEC's HBS system, as described in the above-mentioned document, information is provided as self address, partner address, control code, number of data, data,
Since it is transmitted in the form of a packet composed of a frame check code, each element of the packet is sent to the serial interface circuit 2 one after another with this read self-address as the head, and after parallel / serial conversion, it is sequentially sent to the home bus 8. Sent out. At this time, in the transmission control device 3,
Collision detection and transmission control are performed by the self-address at the beginning of the packet.

Now, considering the order of serial data sent to the home bus 8, the MSB (Most Significant Bi
There is a method of sending from t: most significant bit (hereinafter referred to as MSB sending) and a method of sending from LSB (Least Significant Bit: below LSB sending), which is for a commercially available serial interface. Most of the circuits (for example, LSI such as Hitachi HD 6850) are LSB sending, so KEC's HBS
The method also uses LSB feeding. Now, consider the relationship between the self-address on the home bus 8 and the priority. In this example, "0" is set to have priority over the signal "1" on the home bus 8. The collision detection circuit 3 serially fetches the self address from the packet being transmitted on the home bus 8 and compares it with the self address of the device bit by bit. When the bits are compared bit by bit and a mismatch is detected, the device self-address is “1”.
If so, the device is considered to have a lower priority and the data transmission from the serial interface circuit 2 is stopped.

In this case, the order of self-addresses and the order of priority do not match. Table 1 shows the relationship. In Table 1, the self-address 00H (H indicates hexadecimal) has the highest priority, but the second is 80H, the third is 40H, and the order of the self-address does not always match the priority. Therefore, when a user tries to connect a device to such a home bus in consideration of the priority, a correspondence table between the self-address and the priority is required. This is
Considering that not only many users of this system are not experts, but also housewives and children often handle it,
The man-machine interface results in a system with very poor operability.

For example, the self-address of the fire detector is 80H and the self-address of the TV is 20H.
When connecting the smoke detector with a higher priority than the TV, the user cannot intuitively know the address to be set. This not only causes an erroneous operation, but may cause a serious problem in home security such as fire detection and smoke detection.

Further, this is a problem that occurs in a general communication system using a transmission medium in which a plurality of devices can simultaneously transmit regardless of the home bus system, when the transmission control is performed by using the self address.

[Object of the Invention]

It is an object of the present invention to eliminate the drawbacks of the prior art and to match the order of self-addresses with the priority on the transmission medium.

SUMMARY OF THE INVENTION According to the present invention, when the self address set by the self address setting means is output as serial data from the LSB-sending serial interface circuit to the bus, the self address is a packet fetched from the bus by the collision detection circuit. When the self-address of the device is compared with the self-address of the self-device, the conversion means is provided to convert the self-address so that the priorities are the same and then input the serial interface circuit.

Example of Invention

 Hereinafter, the present invention will be described in detail based on examples.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals, and 9 is a data conversion circuit of an element block according to the present invention. As described above, when collision detection and transmission control are performed using the self address on the LSB-sending home bus 8, the order of the self address and the priority on the bus do not necessarily match. Therefore, the conversion circuit 9 performs data conversion of the self address so that the self address set by the switch 4 matches the priority on the bus.

Next, a specific circuit that realizes the conversion circuit 9 will be described. The simplest circuit that realizes the conversion circuit 9 according to the present invention is, as shown in FIG.
The data bus (Dφ-D) of the CPU is reversed by reversing the order of S7).
It is a circuit connected to 7). That is, the Sφ bit indicating the self address is connected to the D7 bit of the CPU data bus, the S1 bit of the self address is connected to the D6 of the CPU, and so on. Therefore, for example, in the case of FIG. 3, the self address is set to 53H by the switch 4, but the CPU recognizes the converted CAH, and the home bus 8
The self address at the beginning of the packet sent to is CAH. The relationship between the set self address on the home bus 8 and the priority when the conversion is performed in this way is as follows.
As shown in Table 2, the self-address order and the priority order match.

That is, the self-address 00H has the highest priority, 0
1H is second, and FFH has the lowest priority. The conversion circuit of FIG. 4 can be easily realized,
It is very effective in a simple system in which the self address and the other party address are simply set and information is sent. However, this order is not necessarily the same as the priority on the bus because the converted self address is recognized inside the CPU. Therefore, when transmitting by comparing the priority of the self address with the transmission address, C
PU requires complicated processing. FIG. 4 is another embodiment of the present invention which solves this problem.

In FIG. 4, 10 and 11 are 3-state buffers, 12 is an inverter, and 13 is a control signal of the conversion circuit 9 from the CPU. When the control signal 13 is set to "H" and the buffer 10 is selected, the same operation as in FIG. 3 is performed. Meanwhile, the control signal
When 13 is set to "L" and buffer 11 is selected, CPU
Reads the set self address as it is, so CP
It is possible to match the relationship between the self address and the priority inside the U. Therefore, the value read with the control signal 13 set to "H" is used for the self address when transmitting data on the home bus, and the control signal 13 is used for the comparison of priority inside the CPU and its calculation. It is only necessary to use the value read as "L".

FIG. 5 shows a ROM (Read Only Memo) as the conversion circuit 9.
This is an example in which ry) is used. The figure shows the case where a 512-byte ROM (for example, NEC μPB425C) is used, and the self address set by the switch 4 is R
It is connected to the address terminals (Aφ to A7) of the OM. ROM
In this case, the data having the priority corresponding to the self address may be recorded in advance. For example, in order to perform the same conversion as in FIG. 4, the contents as shown in Table 3 may be written. is there. That is, the first half of the address (000H to 0
The lower 8 bits of the address are written as they are in FFH), and the lower 8 bits of the address (100H to 1FFH) are written in the latter half.
The value is written by reversing the order of the bit string of bits. When the ROM is used as the conversion circuit 9 as described above, the relationship between the self-address and the priority can be arbitrarily set depending on the contents. Further, if a RAM (Random Access Memory) is used instead of the ROM, the relationship between the self address and the priority can be freely set or changed by the CPU. In this case, the device 1 (for example, smoke detector) and the device 2 (for example, TV) are connected to the bus, and in order to increase the priority of the device 1, if the device 1 is set by the self address setting switch, The transmitted self address is converted to 80H. Further, when a switch is set in the device 2, it is possible to easily realize that the self address is converted into 20H having a lower priority than 80H.
Although a 512-byte memory is used in FIG. 5, a 256-byte memory may be used as long as it realizes the same function as in Table 2. Further, a memory of 256 bytes may be used only on the buffer 10 side for converting data in FIG.

Although the above embodiment has shown the example in which the data conversion of the self-address is performed by hardware, the conversion may be performed by software using an arithmetic processing unit. In this case, the CPU 1 may be used as the arithmetic processing device, or the arithmetic processing device may be separately provided for conversion. The conversion method by software is roughly divided into 2
There are two ways. One is a method of holding a conversion table and referencing it, and the other is a method of directly converting according to a conversion rule (for example, reversing the order of bit strings). FIG. 6 is a diagram showing a flow chart in the case of performing conversion by referring to the conversion table, and Table 4 is a diagram showing an example of the conversion table. For example, when the self-address is 53, the conversion table of Table 4 is immediately converted to the value CA. FIG. 7 shows a flowchart for directly converting the order of bit strings. This is a method of reading the self-address into A, extracting one bit at a time from the lower order of A, putting it in order from the higher order of B, and reversing the order of the bit string.
When Hitachi HD6809 is used as the arithmetic processing unit, it can be realized by using the commands ASRA and ROLB.

In FIG. 3, the arithmetic processing unit 1, the serial interface circuit 2, the bus control circuit 3, and the buffer 5 are shown as 1
Chip microcomputer (eg Hitachi HD6
801, HD6805, etc.). When the data conversion of the self address is performed by software, it is possible to use this one-chip microcomputer.

As described above, in the embodiment of the present invention, the conversion circuit is the switch 4
The case where the conversion circuit 9 is provided between the three-state buffer 5 and the three-state buffer 5 and the case where the arithmetic processing device performs the conversion circuit 9
Needless to say, the function of the three-state buffer 5 may be incorporated in the memory. The point is that the order of the set addresses and the priority on the bus are matched between the home bus and the self-address setting switch. The conversion means should be provided. Further, in the above example, the description is limited to the home bus, but this is also applicable to other transmission media that can be simultaneously transmitted by a plurality of devices.

〔The invention's effect〕

According to the present invention, in a system in which transmission control is performed using a self-address, the order of self-addresses and the order of priority on a transmission medium can be matched, so that when a user sets a self-address of a device. Moreover, it is sufficient to set only the size of the self-address in consideration of the correspondence table between the self-address and the priority, and a device with few mistakes can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a communication control device according to the prior art, FIG. 2 is a block diagram showing a communication control device according to the present invention, and FIGS. 3, 4, and 5 are data conversion circuits according to the present invention. Block diagrams showing a specific embodiment, FIGS. 6 and 7
The figure is a flow chart when the present invention is implemented in an arithmetic processing unit. 1 ... Arithmetic processing device, 2 ... Serial interface circuit, 3 ... Transmission control circuit, 4 ... Switch, 5 ... 3-state buffer, 8 ... Bus line, 9 ... Conversion circuit.

Claims (1)

[Claims] 1. An address setting means for setting a self-address, a control means for adding the self-address to data to form a packet, and serial-parallel conversion of the information of the packet with the least significant bit priority, and a signal "1". Serial / parallel conversion interface means for inputting / outputting to / from a transmission medium to which a plurality of devices are connected so that “0” is prioritized, and the transmission self-address and the self-address of a packet being transmitted on the transmission medium are set to 1 Bit-by-bit comparison, and if the self-address differs from the transmission self-address in the 1 bit, it is determined that the priority of the self-address of the packet being transmitted is higher than the self-address of the self device,
In a communication control device having collision detection means for stopping output from the serial-parallel conversion interface means to a transmission medium, an address set by the address setting means between the address setting means and the serial-parallel conversion interface means Is provided to the transmission medium via the serial-parallel conversion interface means, and the address converted by the conversion means is provided as a self-address during transmission. apparatus.