JPH0337222B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer method between appropriate devices or devices, and particularly relates to a serial data transfer method in which data is transferred serially. It is something.

[Conventional technology]

Examples of conventional data transfer methods include the following. First, the transmitter side sends a text start code immediately before sending data, and then successively sends byte data in which parity check bits are added to data converted into character codes. And after sending the last byte data,
Data sending is completed by sending a text end code.

On the other hand, after receiving the text start code, the receiver side checks the parity bit of the received byte data that follows, and outputs the data obtained by converting the character code into the original data as valid data. This operation ends upon receipt of a text termination code.

[Problem that the invention seeks to solve]

However, in the conventional data transfer method described above, the transmitter side converts the transmitted data into a character code and adds a parity bit, and the receiver side performs a parity check and converts the character code to data. As described above, the sending and receiving procedures are complicated and require a long calculation processing time, so high-speed calculation means are required to perform high-speed data transfer. Furthermore, since the identity of data is confirmed only by the order of arrival, it is necessary to perform various other checks to improve the reliability of data transfer.

The present invention has been made in view of these points, and it is an object of the present invention to provide a data transfer method that is simple in structure and inexpensive, yet can operate at high speed and reliability.

[Means for solving problems]

The present invention transfers storage address data generated in a fixed order of transferred data in a memory means on a sending side to a receiving side together with the transferred data,
The receiving side is characterized in that the data to be transferred is stored in the memory means with reference to the address data.

[Effect]

According to the present invention, data is transferred with address data as an identifier added in accordance with the sending order of the data to be transferred, and this address data becomes address data in the memory means on the receiving side. This address data is generated in a fixed order and is used for detecting error occurrence in data transfer, etc.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The data transfer method according to the present invention will be described in detail below based on embodiments shown in the accompanying drawings.

FIG. 1 shows an embodiment of the invention. In this figure, the transmitting side 10 includes a sending control 12, a parallel-to-serial converter (hereinafter referred to as "parallel-to-serial converter") 14, a counter 16, and a memory 18. The delivery controller 12 is connected to a parallel-to-serial converter 14 and a counter 16 , and the counter 16 is connected to a parallel-to-serial converter 14 and a memory 18 . This memory 18 is also connected to the parallel to serial converter 14.

Among these, the parallel to serial converter 14 converts parallel data to serial data, and is generally USART
Alternatively, it is commercially available as UART. For example, a 4-bit counter is used as the counter 16, and its output count value becomes the address of the memory 18 and the data input of the parallel-to-serial converter 14. Further, the memory 18 has a storage capacity of, for example, 16 bytes, and stores data to be sent. Activation of this data transfer is controlled by the sending controller 10.

Next, the receiving side 20 uses a serial-parallel converter (hereinafter referred to as
) 22, memory 24, comparator 26, counter 28, and gate 3
0, 32, and a receiving controller 34. The serial-to-parallel converter 22 includes a memory 24, a comparator 26, a counter 28, and AND gates 30, 3.
An appropriate output terminal is connected to counter 2.
8 is connected to the comparator 26. The comparator 26 and AND gates 30, 32 are each connected to a reception controller 34.

Among these, the serial-parallel converter 22 converts serial data into parallel data, and the parallel-serial converter 14
It is also commercially available as USART. The memory 24 stores received data and has a storage capacity of, for example, 16 bytes.

Next, the AND gate 30 acts as a decoder to detect the end of reception from the output of the serial-to-parallel converter 22, and the AND gate 32 similarly acts as a decoder to detect the start of reception. Further, the comparator 26 is connected to the serial-to-parallel converter 2
2 to the memory 24 and the count value of the counter 28.

Note that the transmitting side 10 and the receiving side 20 are connected by a communication line 40.

Next, the overall operation of the above embodiment will be explained.

First, the transmitting side will be explained. It is assumed that the memory 18 already stores data to be transmitted by appropriate means.

First, the output controller 12 outputs a control signal to the counter 16, and the counter 16 is cleared and initialized. On the one hand, the initialized value "0" of the counter 16 is stored in the memory 18.
is input as an address to the parallel to serial converter 14 on the other hand. Furthermore, the data stored at address “0” in the memory 18 is also input to the parallel-to-serial converter 14. That is, as shown in FIG. 2, the data to be transferred consists of, for example, 8 bits, and the data _D0 to _D3 are the original transmission data output from the memory 18, and the data _D4 to _{D7 are the original transmission data output from the memory 18.} The data is sequence code data corresponding to the output of the counter 14, that is, the address data of the memory 18. On the other hand, when the controller 12 issues a sending command to the parallel-to-serial converter 14,
A shift register in the parallel-to-serial converter 14 adds a start bit D _s before D 0 and a stop bit D _p after D ₇ among the D ₀ , D ₁ , _. . . , D ₇ . Then, these D _s , D ₀ , D ₁ , . . . , D ₇ , D _p are transferred to the receiving side 20 via the communication line 40 as transfer data. Thereafter, as the counter 16 counts up according to the command from the sending controller 12, the data at addresses 1, 2, etc. are read out from the memory 18 in order, and the data at the receiving side 20 along with the address data are read out from the memory 18.
will be forwarded to.

Note that in a biphasic type transmitter, a preamble or the like is attached, the data is converted to a Muntier star code, etc., and the data is transmitted serially in the same way.

Next, the serial data transferred to the receiving side is input to the serial-to-parallel converter 22 and converted into parallel data. Specifically, in the serial-to-parallel converter 22, a start bit _Ds is first detected, the following _D0 to _D7 are converted from serial data to parallel data by a shift register, etc., and then one byte, i.e. Completion of reception of 8 bits is detected by AND gate 30, and completion of reception is detected by reception controller 3.
4 will be informed.

FIG. 3 shows parallel-converted data, D ₀ to D ₃ are data to be stored in the memory 24, and D ₄ to D ₇ are data indicating addresses of the memory 24. . First, since the order codes D ₄ , D ₅ , D ₆ , and D ₇ are "0", they are detected by the AND gate 32, and this detection output is input to the counter 28.
is cleared. Furthermore, data D ₀ to D ₃ are stored at address “0” of the memory 24. That is,
Address “0” of memory 24 contains memory 1 on the sending side.
Data similar to that at address "0" of No. 8 will be stored. Similarly, address “1” of the memory 24,
At addresses "2", . . . , the data at the corresponding addresses in the memory 18 are stored one after another. At the same time, the counter 28 is also counted up every time a byte is received.

By the way, the order codes D ₄ D ₅ , D ₆ , D ₇ indicating the addresses in the memory 24, that is, the memory 18
is input to the comparator 26, and the count value of the counter 28 is input to the comparator 26. As mentioned above, the counter 28
is cleared upon reception of the first 1 byte of data, and counts up upon completion of reception of 1 byte of data. Therefore, unless a reception abnormality occurs during data transfer, the inputs of the comparator 26 match. Conversely, when the inputs of the comparator 26 do not match, it means that a reception abnormality has occurred, and when this is detected, a signal to that effect is output to the reception controller 34. The receiving operation is completed when the transfer of the data stored in the memory 18 on the transmitting side is completed. For example, if the address of the last data among the data stored in the memory 18 on the transmitting side is F(H), when this is detected by the AND gate 30, the receiving controller 34 is notified of this fact. and communication is completed.

Note that the present invention is not limited to the above-mentioned embodiments; for example, depending on the transferred data, there may be no problem even if a certain degree of communication abnormality occurs; in such a case, the comparator 26 It is also sufficient to not perform abnormality detection using the counter 28.

Also, when connecting two or more receivers to one transmitter and transferring different data to each receiver, incorporate the receiver address in the data part of the first byte data, If each receiver receives the data when the order code is "0" and the receiver address indicates its own station, a multi-drop system can be achieved.

Furthermore, in order to improve the reliability of data transfer, for example, the last byte data is used as the checksum byte, the data area of the ``0'' to ``15th'' bytes are added, and the lower 4 bits are the data of the 16th byte. By adding a condition that states that the area is normal when the area is the same, data transfer can be performed with higher reliability.

In addition, the circuit configuration can also be changed in design so as to have similar functions, and the present invention is not limited to the above-mentioned embodiments.

〔Effect of the invention〕

As explained above, the data transfer method according to the present invention has the following effects.

Since the configuration on the transmitting side is made up of an extremely simple counter, memory, or parallel-to-serial converter, high-speed operation is possible and the cost is low.

Address data specified in a certain order as an identifier is added to each transferred data, and the entire data is transferred as one unit or one character of data, so the receiving side uses this. Since the address of the storage memory and the start or end of reception can be controlled with a simple circuit configuration, high-speed operation is similarly possible and the cost is low. Furthermore, the reliability of data transfer is improved, and the occurrence of an error can be easily and quickly detected by comparing the order of arrival of data with the identifier added to the data.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of the data transfer method according to the present invention, FIG. 2 is an explanatory diagram showing an example of data transfer generation on the transmitting side, and FIG. 3 is an example of processing of transferred data on the receiving side. FIG. 10... Sending side, 12... Sending controller, 14
...Parallel-serial converter, 16...Counter, 18...Memory, 20...Receiving side, 22...Series-parallel converter, 24
...Memory, 26...Comparator, 28...Counter.

Claims (1)

[Scope of Claims] 1. A data transfer method in which transferred data stored in a first memory means on a transmitting side is transferred to a receiving side and stored in a second memory means on the receiving side, comprising: address data output means for outputting address data specifying addresses in the first memory means in a fixed order; the address data and the transferred data stored at the address of the first memory means specified by the address data; data transmitting means for transmitting data as one unit of data; and address data confirmation for separating address data and transferred data from one unit of data received and confirming whether the address data is specified in the certain order. means, when the address data confirming means does not confirm the address data specified in the certain order, outputs a reception abnormality signal, and when the address data specified in the certain order is confirmed, outputs a reception abnormality signal, and when the address data specified in the certain order is confirmed, the address data and data receiving means for storing the data to be transferred at the address of the second memory means specified by the data transfer method.